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<a href="https://gitlab.rtems.org/matteo.concas">Matteo Concas</a> created a merge request: <a href="https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/548">!548</a>
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Project:Branches: matteo.concas/rtems-gaisler:matteo/backport-add-Smdbltrp-compat to rtems/rtos/rtems:6
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Author: Matteo Concas
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<a href="#summary" aria-hidden="true" class="anchor" id="user-content-summary" style="margin-top: 0; margin-left: -20px; text-decoration: none; outline: none; position: absolute; width: 20px;"></a>Summary</h2>
<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">cpu/riscv: Add Smdbltrp extension compatibility</p>
<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">If the Double Trap Extension is implemented, the MDT bit of the mstatus (or mstatush in RV32) register will be set when a trap is to be taken.</p>
<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">The MIE (Machine Interrupt Enable) bit can only be set to 1 if the MDT bit is zero.</p>
<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">Thus, we need to clear MDT first if we want to enable interrupts when dispatching a thread.</p>
<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">MDT is also cleared in register a1 before restoring the interrupt frame as writing 1 to MDT will cause MIE to be set to 0. In RV64 this happens regardless of the value written to MIE in the same write.</p>
<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">In RV32, MDT is in the mstatush so we do not need to clear during restore as this register is not restored.</p>
<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">With this change all 60 SMP tests pass (compared to 20/60 before the fix). The tests have been run on hardware using two RV64 CPUs that implement the double trap extension.</p>
<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">Close <a href="https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5288" data-reference-type="issue" data-original="#5288" data-link="false" data-link-reference="false" data-issue="29126" data-project="26" data-iid="5288" data-namespace-path="rtems/rtos/rtems" data-project-path="rtems/rtos/rtems" data-issue-type="issue" data-container="body" data-placement="top" title="Backport RISC-V Double Trap extension fix to 6" class="gfm gfm-issue" style="margin-top: 0;">#5288</a></p>
<p dir="auto" style="color: #3a383f; margin: 0;" align="initial">(cherry picked from commit <a href="https://gitlab.rtems.org/rtems/rtos/rtems/-/commit/19f12d2dca02da3072c0c31e2da281f6a447699e" data-reference-type="commit" data-original="19f12d2dca02da3072c0c31e2da281f6a447699e" data-link="false" data-link-reference="false" data-commit="19f12d2dca02da3072c0c31e2da281f6a447699e" data-project="26" data-container="body" data-placement="top" title="cpu/riscv: Add Smdbltrp extension compatibility" class="gfm gfm-commit has-tooltip" style='font-family: "GitLab Mono", "JetBrains Mono", "Menlo", "DejaVu Sans Mono", "Liberation Mono", "Consolas", "Ubuntu Mono", "Courier New", "andale mono", "lucida console", monospace; font-variant-ligatures: none; font-size: 95%; margin-top: 0;'>19f12d2d</a>)</p>
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