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<a href="https://gitlab.rtems.org/D3athSkulll">SHIVAM DEOLANKAR</a>
commented on a
<a href="https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1212#note_148879">discussion</a>:
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<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">The logic issues in previous implmentation is rectified here</p>
<p dir="auto" style="color: #3a383f; margin: 0 0 1rem;" align="initial">Earlier we tried to keep no parity first. then tried to add ODD or EVEN using OR operator and also mixed up the ODD and EVEN logic. In turn this combined multiple values. Thus UART ignored parity settings showing incorrect behaviour.</p>
<p dir="auto" style="color: #3a383f; margin: 0;" align="initial">New logic clears old parity bits and sets exactly one mode. NO, ODD, EVEN. and thus correct behaviour should be observed logically</p>
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