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Issue created by <a href="https://gitlab.rtems.org/sebhub">Sebastian Huber</a>: <a href="https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5688">#5688</a>
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<p dir="auto" style="color: #3a383f; margin: 0px 0px 1rem;" align="initial">The interrupt level of the MIPS port and the interrupt controller of the
<code style="font-size: 90%; color: #18171d; word-wrap: break-word; background-color: #ececef; border-radius: .25rem; margin-top: 0px; font-weight: inherit; overflow-wrap: break-word; white-space: break-spaces; font-family: "GitLab Mono", "JetBrains Mono", "Menlo", "DejaVu Sans Mono", "Liberation Mono", "Consolas", "Ubuntu Mono", "Courier New", "andale mono", "lucida console", monospace; font-variant-ligatures: none; word-break: keep-all; padding: 0.125rem 0.25rem;">jmr3904</code> BSP have several defects. The port does not treat level zero as
"enable all", it derives the level from the wrong status register bits, and it
takes the vector base from the wrong place. The interrupt mask of the BSP is not
visible where the port needs it. The BSP has no interrupt controller at all, so
the interrupt manager cannot enable, disable or raise a vector, and the
processor interrupt sources stay unmasked.</p>
<p dir="auto" style="color: #3a383f; margin: 0px;" align="initial">Found while running the full test suite on the GDB simulator. This description
was created with Claude Code assistance.</p>
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