[PATCH 1/2] bsps/aarch64/raspberrypi: Refactor code base

Utkarsh Verma utkarsh at bitbanged.com
Mon Aug 7 04:49:49 UTC 2023


From: Utkarsh Verma <utkarshverma at protonmail.com>

Refactor the code base for better organization to facilitate future
patches.
---
 .gitignore                                    |   4 +
 bsps/aarch64/raspberrypi/console/console.c    |  42 +-
 bsps/aarch64/raspberrypi/include/bsp.h        |  33 +-
 .../aarch64/raspberrypi/include/bsp/bcm2711.h |  98 ++++
 bsps/aarch64/raspberrypi/include/bsp/irq.h    |  94 ++--
 .../raspberrypi/include/bsp/raspberrypi.h     | 471 ------------------
 .../include/bsp/start/bspstartmmu.h           |   8 +
 bsps/aarch64/raspberrypi/start/bspstart.c     |  18 +-
 .../aarch64/raspberrypi/start/bspstarthooks.c |  26 +-
 bsps/aarch64/raspberrypi/start/bspstartmmu.c  |  66 +--
 spec/build/bsps/aarch64/raspberrypi/abi.yml   |  37 +-
 spec/build/bsps/aarch64/raspberrypi/bsp4b.yml |  23 +
 .../aarch64/raspberrypi/bspraspberrypi4.yml   |  72 ---
 spec/build/bsps/aarch64/raspberrypi/grp.yml   |  49 ++
 spec/build/bsps/aarch64/raspberrypi/grp4b.yml |  26 +
 .../{linkercmds.yml => linkcmds.yml}          |  25 +-
 spec/build/bsps/aarch64/raspberrypi/obj.yml   |  50 ++
 .../aarch64/raspberrypi/objconsolepl011.yml   |  24 +
 .../aarch64/raspberrypi/optclockpl011freq.yml |  23 +
 .../aarch64/raspberrypi/optconsolebaud.yml    |  23 +
 20 files changed, 487 insertions(+), 725 deletions(-)
 create mode 100644 bsps/aarch64/raspberrypi/include/bsp/bcm2711.h
 delete mode 100644 bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h
 create mode 100644 bsps/aarch64/raspberrypi/include/bsp/start/bspstartmmu.h
 create mode 100644 spec/build/bsps/aarch64/raspberrypi/bsp4b.yml
 delete mode 100644 spec/build/bsps/aarch64/raspberrypi/bspraspberrypi4.yml
 create mode 100644 spec/build/bsps/aarch64/raspberrypi/grp.yml
 create mode 100644 spec/build/bsps/aarch64/raspberrypi/grp4b.yml
 rename spec/build/bsps/aarch64/raspberrypi/{linkercmds.yml => linkcmds.yml} (90%)
 create mode 100644 spec/build/bsps/aarch64/raspberrypi/obj.yml
 create mode 100644 spec/build/bsps/aarch64/raspberrypi/objconsolepl011.yml
 create mode 100644 spec/build/bsps/aarch64/raspberrypi/optclockpl011freq.yml
 create mode 100644 spec/build/bsps/aarch64/raspberrypi/optconsolebaud.yml

diff --git a/.gitignore b/.gitignore
index 8b28b186e1..d0144f6737 100644
--- a/.gitignore
+++ b/.gitignore
@@ -12,3 +12,7 @@ Makefile.in
 /testsuites/build/build
 /testsuites/build/wscript
 .waf*
+.clangd
+.clang-format
+compile_commands.json
+.cache/
diff --git a/bsps/aarch64/raspberrypi/console/console.c b/bsps/aarch64/raspberrypi/console/console.c
index 73bb0036ff..4aba0ec73e 100644
--- a/bsps/aarch64/raspberrypi/console/console.c
+++ b/bsps/aarch64/raspberrypi/console/console.c
@@ -3,13 +3,14 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ * @ingroup RTEMSBSPsAArch64RaspberryPi
  *
  * @brief Console Configuration
  */
 
 /*
- * Copyright (C) 2022 Mohd Noor Aman
+ * Copyright (c) 2022 Mohd Noor Aman
+ * Copyright (c) 2023 Utkarsh Verma
  *
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,36 +35,33 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <rtems/bspIo.h>
-
-#include <bsp.h>
-#include <dev/serial/arm-pl011.h>
 #include <bsp/console-termios.h>
-
 #include <bspopts.h>
+#include <dev/serial/arm-pl011.h>
+#include <rtems/bspIo.h>
 
-arm_pl011_context raspberrypi_4_context = {
-  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
-  .regs = (volatile pl011 *) BSP_RPI4_PL011_BASE,
-  .initial_baud = 115200
+#include "bsp.h"
+
+arm_pl011_context uart0 = {
+    .base         = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
+    .regs         = (volatile pl011 *)BSP_UART0_BASE,
+    .initial_baud = BSP_CONSOLE_BAUD,
 };
 
 const console_device console_device_table[] = {
-  {
-    .device_file = "/dev/ttyS0",
-    .probe = console_device_probe_default,
-    .handler = &arm_pl011_fns,
-    .context = &raspberrypi_4_context.base
-  }
+    {
+        .device_file = "/dev/ttyAMA0",
+        .probe       = console_device_probe_default,
+        .handler     = &arm_pl011_fns,
+        .context     = &uart0.base,
+    },
 };
 
 const size_t console_device_count = RTEMS_ARRAY_SIZE(console_device_table);
 
-static void output_char( char c )
-{
-  arm_pl011_write_polled(&raspberrypi_4_context.base, c);
+static void output_char(char c) {
+    arm_pl011_write_polled(&uart0.base, c);
 }
 
-BSP_output_char_function_type BSP_output_char = output_char;
-
+BSP_output_char_function_type BSP_output_char   = output_char;
 BSP_polling_getchar_function_type BSP_poll_char = NULL;
diff --git a/bsps/aarch64/raspberrypi/include/bsp.h b/bsps/aarch64/raspberrypi/include/bsp.h
index 4fa81edd40..0c2b4c98eb 100644
--- a/bsps/aarch64/raspberrypi/include/bsp.h
+++ b/bsps/aarch64/raspberrypi/include/bsp.h
@@ -3,13 +3,14 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ * @ingroup RTEMSBSPsAArch64RaspberryPi
  *
  * @brief Core BSP definitions
  */
 
 /*
  * Copyright (C) 2022 Mohd Noor Aman
+ * Copyright (C) 2023 Utkarsh Verma
  *
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,8 +35,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H
-#define LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H
+#ifndef LIBBSP_AARCH64_RASPBERRYPI_BSP_H
+#define LIBBSP_AARCH64_RASPBERRYPI_BSP_H
 
 /**
  * @addtogroup RTEMSBSPsAArch64
@@ -48,26 +49,18 @@
 #ifndef ASM
 
 #include <bsp/default-initial-extension.h>
-#include <bsp/start.h>
 
-#include <rtems.h>
+#if RTEMS_BSP == raspberrypi4b
+#include "bsp/bcm2711.h"
 
-/*Raspberry pi MMU initialization */
-BSP_START_TEXT_SECTION void raspberrypi_4_setup_mmu_and_cache(void);
+#define BSP_GIC_BASE           BCM2711_GIC_BASE
+#define BSP_GIC_SIZE           BCM2711_GIC_SIZE
+#define BSP_ARM_GIC_CPUIF_BASE BCM2711_GIC_CPUIF_BASE
+#define BSP_ARM_GIC_DIST_BASE  BCM2711_GIC_DIST_BASE
 
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-#define BSP_ARM_GIC_CPUIF_BASE 0xFF842000
-#define BSP_ARM_GIC_DIST_BASE 0xFF841000
-
-#define BSP_RPI4_PL011_BASE 0xFE201000
-#define BSP_RPI4_PL011_LENGTH 0x200
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
+#define BSP_UART0_BASE BCM2711_UART0_BASE
+#define BSP_UART0_SIZE BCM2711_UART0_SIZE
+#endif /* raspberrypi4b */
 
 #endif /* ASM */
 
diff --git a/bsps/aarch64/raspberrypi/include/bsp/bcm2711.h b/bsps/aarch64/raspberrypi/include/bsp/bcm2711.h
new file mode 100644
index 0000000000..885dad8af9
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/include/bsp/bcm2711.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64RaspberryPi
+ *
+ * @brief Register definitions
+ */
+
+/*
+ * Copyright (C) 2022 Mohd Noor Aman
+ * Copyright (C) 2023 Utkarsh Verma
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_AARCH64_RASPBERRYPI_BSP_BCM2711_H
+#define LIBBSP_AARCH64_RASPBERRYPI_BSP_BCM2711_H
+
+#include <stdint.h>
+
+#define BCM2711_REG(addr) (*(uint32_t*)(addr))
+
+/*
+ * NOTE:
+ * Raspberry Pi 4B boots into low peripheral mode by default.
+ * The addresses are specified in the BCM2711 peripherals datashseet in Fig 1.
+ */
+#define BCM2711_PERIPHERAL_BASE 0xfc000000LL
+#define BCM2711_PERIPHERAL_SIZE 0x3800000
+
+/* Mailbox */
+#define BCM2711_MBOX_BASE (BCM2711_PERIPHERAL_BASE + 0x200B880)
+
+/* GPIO */
+#define BCM2711_GPIO_BASE (BCM2711_PERIPHERAL_BASE + 0x2200000)
+#define BCM2711_GPIO_SIZE 0xf4
+
+/* AUX */
+#define BCM2711_AUX_BASE (BCM2711_PERIPHERAL_BASE + 0x2215000)
+#define BCM2711_AUX_SIZE 0x100
+
+/* AUX: Mini UART */
+#define BCM2711_AUX_MU_BASE (BCM2711_AUX_BASE + 0x40)
+#define BCM2711_AUX_MU_SIZE 0x40
+
+#define BCM2711_UART1_BASE BCM2711_AUX_MU_BASE
+#define BCM2711_UART1_SIZE BCM2711_AUX_MU_SIZE
+
+/* PL011 UARTs */
+#define BCM2711_PL011_BASE        (BCM2711_PERIPHERAL_BASE + 0x2201000)
+#define BCM2711_PL011_SIZE        0xc00
+#define BCM2711_PL011_DEVICE_SIZE 0x200
+
+#define BCM2711_UART0_BASE (BCM2711_PL011_BASE + 0x000)
+#define BCM2711_UART0_SIZE BCM2711_PL011_DEVICE_SIZE
+#define BCM2711_UART2_BASE (BCM2711_PL011_BASE + 0x400)
+#define BCM2711_UART2_SIZE BCM2711_PL011_DEVICE_SIZE
+#define BCM2711_UART3_BASE (BCM2711_PL011_BASE + 0x600)
+#define BCM2711_UART3_SIZE BCM2711_PL011_DEVICE_SIZE
+#define BCM2711_UART4_BASE (BCM2711_PL011_BASE + 0x800)
+#define BCM2711_UART4_SIZE BCM2711_PL011_DEVICE_SIZE
+#define BCM2711_UART5_BASE (BCM2711_PL011_BASE + 0xa00)
+#define BCM2711_UART5_SIZE BCM2711_PL011_DEVICE_SIZE
+
+/* ARM Local */
+#define BCM2711_ARM_LOCAL_BASE 0xff800000LL
+#define BCM2711_ARM_LOCAL_SIZE 0x800000
+
+/* Generic interrupt controller */
+#define BCM2711_GIC_BASE (BCM2711_ARM_LOCAL_BASE + 0x40000)
+#define BCM2711_GIC_SIZE 0x8000
+
+#define BCM2711_GIC_DIST_BASE  (BCM2711_GIC_BASE + 0x1000)
+#define BCM2711_GIC_CPUIF_BASE (BCM2711_GIC_BASE + 0x2000)
+
+#endif /* LIBBSP_AARCH64_RASPBERRYPI_BCM2711_H */
diff --git a/bsps/aarch64/raspberrypi/include/bsp/irq.h b/bsps/aarch64/raspberrypi/include/bsp/irq.h
index effec1b040..1e84cd3ea2 100644
--- a/bsps/aarch64/raspberrypi/include/bsp/irq.h
+++ b/bsps/aarch64/raspberrypi/include/bsp/irq.h
@@ -7,8 +7,8 @@
  */
 
 /**
- * Copyright (c) 2013 Alan Cudmore
- * Copyright (c) 2022 Mohd Noor Aman
+ * Copyright (C) 2013 Alan Cudmore
+ * Copyright (C) 2022 Mohd Noor Aman
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
@@ -17,15 +17,15 @@
  *
  */
 
-#ifndef LIBBSP_ARM_RASPBERRYPI_IRQ_H
-#define LIBBSP_ARM_RASPBERRYPI_IRQ_H
+#ifndef LIBBSP_AARCH64_RASPBERRYPI_BSP_IRQ_H
+#define LIBBSP_AARCH64_RASPBERRYPI_BSP_IRQ_H
 
 #ifndef ASM
 
+#include <dev/irq/arm-gic-irq.h>
 #include <rtems.h>
-#include <rtems/irq.h>
 #include <rtems/irq-extension.h>
-#include <dev/irq/arm-gic-irq.h>
+#include <rtems/irq.h>
 
 #if defined(RTEMS_SMP)
 #include <rtems/score/processormask.h>
@@ -39,31 +39,31 @@
  * @brief Interrupt support.
  */
 
-#define BCM2835_INTC_TOTAL_IRQ       (64 + 8)
-
-#define BCM2835_IRQ_SET1_MIN         0
-#define BCM2835_IRQ_SET2_MIN         32
-
-#define BCM2835_IRQ_ID_GPU_TIMER_M0  0
-#define BCM2835_IRQ_ID_GPU_TIMER_M1  1
-#define BCM2835_IRQ_ID_GPU_TIMER_M2  2
-#define BCM2835_IRQ_ID_GPU_TIMER_M3  3
-
-#define BCM2835_IRQ_ID_USB           9
-#define BCM2835_IRQ_ID_AUX           29
-#define BCM2835_IRQ_ID_SPI_SLAVE     43
-#define BCM2835_IRQ_ID_PWA0          45
-#define BCM2835_IRQ_ID_PWA1          46
-#define BCM2835_IRQ_ID_SMI           48
-#define BCM2835_IRQ_ID_GPIO_0        49
-#define BCM2835_IRQ_ID_GPIO_1        50
-#define BCM2835_IRQ_ID_GPIO_2        51
-#define BCM2835_IRQ_ID_GPIO_3        52
-#define BCM2835_IRQ_ID_I2C           53
-#define BCM2835_IRQ_ID_SPI           54
-#define BCM2835_IRQ_ID_PCM           55
-#define BCM2835_IRQ_ID_UART          57
-#define BCM2835_IRQ_ID_SD            62
+#define BCM2835_INTC_TOTAL_IRQ (64 + 8)
+
+#define BCM2835_IRQ_SET1_MIN 0
+#define BCM2835_IRQ_SET2_MIN 32
+
+#define BCM2835_IRQ_ID_GPU_TIMER_M0 0
+#define BCM2835_IRQ_ID_GPU_TIMER_M1 1
+#define BCM2835_IRQ_ID_GPU_TIMER_M2 2
+#define BCM2835_IRQ_ID_GPU_TIMER_M3 3
+
+#define BCM2835_IRQ_ID_USB       9
+#define BCM2835_IRQ_ID_AUX       29
+#define BCM2835_IRQ_ID_SPI_SLAVE 43
+#define BCM2835_IRQ_ID_PWA0      45
+#define BCM2835_IRQ_ID_PWA1      46
+#define BCM2835_IRQ_ID_SMI       48
+#define BCM2835_IRQ_ID_GPIO_0    49
+#define BCM2835_IRQ_ID_GPIO_1    50
+#define BCM2835_IRQ_ID_GPIO_2    51
+#define BCM2835_IRQ_ID_GPIO_3    52
+#define BCM2835_IRQ_ID_I2C       53
+#define BCM2835_IRQ_ID_SPI       54
+#define BCM2835_IRQ_ID_PCM       55
+#define BCM2835_IRQ_ID_UART      57
+#define BCM2835_IRQ_ID_SD        62
 
 #define BCM2835_IRQ_ID_BASIC_BASE_ID 64
 #define BCM2835_IRQ_ID_TIMER_0       64
@@ -74,34 +74,28 @@
 #define BCM2835_IRQ_ID_GPU1_HALTED   69
 #define BCM2835_IRQ_ID_ILL_ACCESS_1  70
 #define BCM2835_IRQ_ID_ILL_ACCESS_0  71
-#define BSP_TIMER_VIRT_PPI 27
-#define BSP_TIMER_PHYS_NS_PPI 30
-#define BSP_VPL011_SPI 32
+#define BSP_TIMER_VIRT_PPI           27
+#define BSP_TIMER_PHYS_NS_PPI        30
+#define BSP_VPL011_SPI               32
 
-#define BSP_INTERRUPT_VECTOR_COUNT    BCM2835_INTC_TOTAL_IRQ
+#define BSP_INTERRUPT_VECTOR_COUNT   BCM2835_INTC_TOTAL_IRQ
 #define BSP_INTERRUPT_VECTOR_INVALID (UINT32_MAX)
 
-#define BSP_IRQ_COUNT               (BCM2835_INTC_TOTAL_IRQ)
+#define BSP_IRQ_COUNT (BCM2835_INTC_TOTAL_IRQ)
 
 #if defined(RTEMS_SMP)
 static inline rtems_status_code bsp_interrupt_set_affinity(
-  rtems_vector_number   vector,
-  const Processor_mask *affinity
-)
-{
-  (void) vector;
-  (void) affinity;
-  return RTEMS_UNSATISFIED;
+    rtems_vector_number vector, const Processor_mask *affinity) {
+    (void)vector;
+    (void)affinity;
+    return RTEMS_UNSATISFIED;
 }
 
 static inline rtems_status_code bsp_interrupt_get_affinity(
-  rtems_vector_number  vector,
-  Processor_mask      *affinity
-)
-{
-  (void) vector;
-  _Processor_mask_From_index( affinity, 0 );
-  return RTEMS_UNSATISFIED;
+    rtems_vector_number vector, Processor_mask *affinity) {
+    (void)vector;
+    _Processor_mask_From_index(affinity, 0);
+    return RTEMS_UNSATISFIED;
 }
 #endif
 
diff --git a/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h
deleted file mode 100644
index 55dd9ed1e9..0000000000
--- a/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h
+++ /dev/null
@@ -1,471 +0,0 @@
-/**
- * @file
- *
- * @ingroup raspberrypi_4_regs
- *
- * @brief Register definitions.
- */
-
-/*
- *  Copyright (c) 2022 Mohd Noor Aman
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *
- *  http://www.rtems.org/license/LICENSE
- *
- */
-
-
-#ifndef LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
-#define LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
-
-
-#include <bspopts.h>
-#include <stdint.h>
-#include <bsp/utility.h>
-
-
-/**
- * @defgroup raspberrypi_reg Register Definitions
- *
- * @ingroup RTEMSBSPsARMRaspberryPi
- *
- * @brief Register Definitions
- *
- * @{
- */
-
-/**
- * @name Register Macros
- *
- * @{
- */
-
-#define BCM2711_REG(x)           (*(volatile uint64_t *)(x))
-#define BCM2711_BIT(n)           (1 << (n))
-
-/** @} */
-
-/**
- * @name Peripheral Base Register Address
- *
- * @{
- */
-
-#define RPI_PERIPHERAL_BASE         0xFE000000
-#define BASE_OFFSET                 0xFE000000
-#define RPI_PERIPHERAL_SIZE         0x01800000
-
-/**
- * @name Bus to Physical address translation
- *       Macro.
- * @{
- */
-#define BUS_TO_PHY(x)            ((x) - BASE_OFFSET)
-
-/** @} */
-
-/**
- * @name Internal ARM Timer Registers
- *
- * @{
- */
-
-#define BCM2711_CLOCK_FREQ       250000000
-
-#define BCM2711_TIMER_BASE       (RPI_PERIPHERAL_BASE + 0xB400)
-
-#define BCM2711_TIMER_LOD        (BCM2711_TIMER_BASE + 0x00)
-#define BCM2711_TIMER_VAL        (BCM2711_TIMER_BASE + 0x04)
-#define BCM2711_TIMER_CTL        (BCM2711_TIMER_BASE + 0x08)
-#define BCM2711_TIMER_CLI        (BCM2711_TIMER_BASE + 0x0C)
-#define BCM2711_TIMER_RIS        (BCM2711_TIMER_BASE + 0x10)
-#define BCM2711_TIMER_MIS        (BCM2711_TIMER_BASE + 0x14)
-#define BCM2711_TIMER_RLD        (BCM2711_TIMER_BASE + 0x18)
-#define BCM2711_TIMER_DIV        (BCM2711_TIMER_BASE + 0x1C)
-#define BCM2711_TIMER_CNT        (BCM2711_TIMER_BASE + 0x20)
-
-#define BCM2711_TIMER_PRESCALE    0xF9
-
-/** @} */
-
-/**
- * @name Power Management and Watchdog  Registers
- *
- * @{
- */
-
-#define BCM2711_PM_PASSWD_MAGIC  0x5a000000
-
-#define BCM2711_PM_BASE          (RPI_PERIPHERAL_BASE + 0x100000)
-
-#define BCM2711_PM_GNRIC         (BCM2711_PM_BASE + 0x00)
-#define BCM2711_PM_GNRIC_POWUP   0x00000001
-#define BCM2711_PM_GNRIC_POWOK   0x00000002
-#define BCM2711_PM_GNRIC_ISPOW   0x00000004
-#define BCM2711_PM_GNRIC_MEMREP  0x00000008
-#define BCM2711_PM_GNRIC_MRDONE  0x00000010
-#define BCM2711_PM_GNRIC_ISFUNC  0x00000020
-#define BCM2711_PM_GNRIC_RSTN    0x00000fc0
-#define BCM2711_PM_GNRIC_ENAB    0x00001000
-#define BCM2711_PM_GNRIC_CFG     0x007f0000
-
-#define BCM2711_PM_AUDIO         (BCM2711_PM_BASE + 0x04)
-#define BCM2711_PM_AUDIO_APSM    0x000fffff
-#define BCM2711_PM_AUDIO_CTRLEN  0x00100000
-#define BCM2711_PM_AUDIO_RSTN    0x00200000
-
-#define BCM2711_PM_STATUS        (BCM2711_PM_BASE + 0x18)
-
-#define BCM2711_PM_RSTC          (BCM2711_PM_BASE + 0x1c)
-#define BCM2711_PM_RSTC_DRCFG    0x00000003
-#define BCM2711_PM_RSTC_WRCFG    0x00000030
-#define BCM2711_PM_RSTC_WRCFG_FULL   0x00000020
-#define BCM2711_PM_RSTC_SRCFG    0x00000300
-#define BCM2711_PM_RSTC_QRCFG    0x00003000
-#define BCM2711_PM_RSTC_FRCFG    0x00030000
-#define BCM2711_PM_RSTC_HRCFG    0x00300000
-
-#define BCM2711_PM_RSTS          (BCM2711_PM_BASE + 0x20)
-#define BCM2711_PM_RSTS_HADDRQ   0x00000001
-#define BCM2711_PM_RSTS_HADDRF   0x00000002
-#define BCM2711_PM_RSTS_HADDRH   0x00000004
-#define BCM2711_PM_RSTS_HADWRQ   0x00000010
-#define BCM2711_PM_RSTS_HADWRF   0x0000002
-#define BCM2711_PM_RSTS_HADWRH   0x00000040
-#define BCM2711_PM_RSTS_HADSRQ   0x00000100
-#define BCM2711_PM_RSTS_HADSRF   0x00000200
-#define BCM2711_PM_RSTS_HADSRH   0x00000400
-#define BCM2711_PM_RSTS_HADPOR   0x00001000
-
-#define BCM2711_PM_WDOG          (BCM2711_PM_BASE + 0x24)
-
-/** @} */
-
-
-/** @} */
-
-/**
- * @name AUX Registers
- *
- * @{
- */
-
-#define BCM2711_AUX_BASE         (RPI_PERIPHERAL_BASE + 0x215000)
-
-#define AUX_ENABLES              (BCM2711_AUX_BASE + 0x04)
-#define AUX_MU_IO_REG            (BCM2711_AUX_BASE + 0x40)
-#define AUX_MU_IER_REG           (BCM2711_AUX_BASE + 0x44)
-#define AUX_MU_IIR_REG           (BCM2711_AUX_BASE + 0x48)
-#define AUX_MU_LCR_REG           (BCM2711_AUX_BASE + 0x4C)
-#define AUX_MU_MCR_REG           (BCM2711_AUX_BASE + 0x50)
-#define AUX_MU_LSR_REG           (BCM2711_AUX_BASE + 0x54)
-#define AUX_MU_MSR_REG           (BCM2711_AUX_BASE + 0x58)
-#define AUX_MU_SCRATCH           (BCM2711_AUX_BASE + 0x5C)
-#define AUX_MU_CNTL_REG          (BCM2711_AUX_BASE + 0x60)
-#define AUX_MU_STAT_REG          (BCM2711_AUX_BASE + 0x64)
-#define AUX_MU_BAUD_REG          (BCM2711_AUX_BASE + 0x68)
-
-/** @} */
-
-
-
-/** @} */
-
-/**
- * @name GPU Timer Registers
- *
- * @{
- */
-
-/**
- * NOTE: The GPU uses Compare registers 0 and 2 for
- *       it's own RTOS. 1 and 3 are available for use in
- *       RTEMS.
- */
-#define BCM2711_GPU_TIMER_BASE       (RPI_PERIPHERAL_BASE + 0x3000)
-
-#define BCM2711_GPU_TIMER_CS         (BCM2711_GPU_TIMER_BASE + 0x00)
-#define BCM2711_GPU_TIMER_CS_M0      0x00000001
-#define BCM2711_GPU_TIMER_CS_M1      0x00000002
-#define BCM2711_GPU_TIMER_CS_M2      0x00000004
-#define BCM2711_GPU_TIMER_CS_M3      0x00000008
-#define BCM2711_GPU_TIMER_CLO        (BCM2711_GPU_TIMER_BASE + 0x04)
-#define BCM2711_GPU_TIMER_CHI        (BCM2711_GPU_TIMER_BASE + 0x08)
-#define BCM2711_GPU_TIMER_C0         (BCM2711_GPU_TIMER_BASE + 0x0C)
-#define BCM2711_GPU_TIMER_C1         (BCM2711_GPU_TIMER_BASE + 0x10)
-#define BCM2711_GPU_TIMER_C2         (BCM2711_GPU_TIMER_BASE + 0x14)
-#define BCM2711_GPU_TIMER_C3         (BCM2711_GPU_TIMER_BASE + 0x18)
-
-/** @} */
-
-/**
- * @name EMMC Registers
- *
- * @{
- */
-
-/**
- * NOTE: Since the SD controller follows the SDHCI standard,
- *       the rtems-libbsd tree already provides the remaining registers.
- */
-
-#define BCM2711_EMMC_BASE           (RPI_PERIPHERAL_BASE + 0x300000)
-
-/** @} */
-
-/**
-* @name Mailbox Registers
-*
-* @{
-*/
-
-#define BCM2711_MBOX_BASE          (RPI_PERIPHERAL_BASE+0xB880)
-
-#define BCM2711_MBOX_READ          (BCM2711_MBOX_BASE+0x00)
-#define BCM2711_MBOX_PEEK          (BCM2711_MBOX_BASE+0x10)
-#define BCM2711_MBOX_SENDER        (BCM2711_MBOX_BASE+0x14)
-#define BCM2711_MBOX_STATUS        (BCM2711_MBOX_BASE+0x18)
-#define BCM2711_MBOX_WRITE         (BCM2711_MBOX_BASE+0x20)
-#define BCM2711_MBOX_CONFIG        (BCM2711_MBOX_BASE+0x1C)
-
-#define BCM2711_MBOX_RESPONSE      0x80000000
-#define BCM2711_MBOX_FULL          0x80000000
-#define BCM2711_MBOX_EMPTY         0x40000000
-
-/** @} */
-
-/**
-* @name Mailbox Channels
-*
-* @{
-*/
-
-/* Power Manager channel */
-#define BCM2711_MBOX_CHANNEL_PM         0
-/* Framebuffer channel */
-#define BCM2711_MBOX_CHANNEL_FB         1
- /* Virtual UART channel */
-#define BCM2711_MBOX_CHANNEL_VUART      2
- /* VCHIQ channel */
-#define BCM2711_MBOX_CHANNEL_VCHIQ      3
- /* LEDs channel */
-#define BCM2711_MBOX_CHANNEL_LED        4
- /* Button channel */
-#define BCM2711_MBOX_CHANNEL_BUTTON     5
- /* Touch screen channel */
-#define BCM2711_MBOX_CHANNEL_TOUCHS     6
-
-#define BCM2711_MBOX_CHANNEL_COUNT      7
-/* Property tags (ARM <-> VC) channel */
-#define BCM2711_MBOX_CHANNEL_PROP_AVC   8
- /* Property tags (VC <-> ARM) channel */
-#define BCM2711_MBOX_CHANNEL_PROP_VCA   9
-
-/** @} */
-
-
-
-/**
- * @name Raspberry Pi 2 Interrupt Register Defines
- *
- * @{
- */
-
-/* Timers interrupt control registers */
-#define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE       0xFF800040
-#define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE       0xFF800044
-#define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE       0xFF800048
-#define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE       0xFF80004C
-
-#define BCM2711_CORE_TIMER_IRQ_CTRL(cpuidx) \
-  (BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
-
-
-/**
- * @name Raspberry Pi 4 ARM_LOCAL registers
- *
- * @{
- */
-
-#define BCM2711_LOCAL_REGS_BASE               0x4C0000000
-#define BCM2711_LOCAL_REGS_SIZE               0x100
-
-#define BCM2711_LOCAL_ARM_CONTROL             (BCM2711_LOCAL_REGS_BASE + 0x00)
-#define BCM2711_LOCAL_CORE_IRQ_CONTROL        (BCM2711_LOCAL_REGS_BASE + 0x0c)
-#define BCM2711_LOCAL_PMU_CONTROL_SET         (BCM2711_LOCAL_REGS_BASE + 0x10)
-#define BCM2711_LOCAL_PMU_CONTROL_CLR         (BCM2711_LOCAL_REGS_BASE + 0x14)
-#define BCM2711_LOCAL_PERI_IRQ_ROUTE0         (BCM2711_LOCAL_REGS_BASE + 0x24)
-#define BCM2711_LOCAL_AXI_QUIET_TIME          (BCM2711_LOCAL_REGS_BASE + 0x30)
-#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL     (BCM2711_LOCAL_REGS_BASE + 0x34)
-#define BCM2711_LOCAL_LOCAL_TIMER_IRQ         (BCM2711_LOCAL_REGS_BASE + 0x38)
-
-#define BCM2711_LOCAL_TIMER_CNTRL0            (BCM2711_LOCAL_REGS_BASE + 0x40)
-#define BCM2711_LOCAL_TIMER_CNTRL1            (BCM2711_LOCAL_REGS_BASE + 0x44)
-#define BCM2711_LOCAL_TIMER_CNTRL2            (BCM2711_LOCAL_REGS_BASE + 0x48)
-#define BCM2711_LOCAL_TIMER_CNTRL3            (BCM2711_LOCAL_REGS_BASE + 0x4c)
-
-#define BCM2711_LOCAL_MAILBOX_CNTRL0          (BCM2711_LOCAL_REGS_BASE + 0x50)
-#define BCM2711_LOCAL_MAILBOX_CNTRL1          (BCM2711_LOCAL_REGS_BASE + 0x54)
-#define BCM2711_LOCAL_MAILBOX_CNTRL2          (BCM2711_LOCAL_REGS_BASE + 0x58)
-#define BCM2711_LOCAL_MAILBOX_CNTRL3          (BCM2711_LOCAL_REGS_BASE + 0x5c)
-
-#define BCM2711_LOCAL_IRQ_SOURCE0             (BCM2711_LOCAL_REGS_BASE + 0x60)
-#define BCM2711_LOCAL_IRQ_SOURCE1             (BCM2711_LOCAL_REGS_BASE + 0x64)
-#define BCM2711_LOCAL_IRQ_SOURCE2             (BCM2711_LOCAL_REGS_BASE + 0x68)
-#define BCM2711_LOCAL_IRQ_SOURCE3             (BCM2711_LOCAL_REGS_BASE + 0x6c)
-
-#define BCM2711_LOCAL_FIQ_SOURCE0             (BCM2711_LOCAL_REGS_BASE + 0x70)
-#define BCM2711_LOCAL_FIQ_SOURCE1             (BCM2711_LOCAL_REGS_BASE + 0x74)
-#define BCM2711_LOCAL_FIQ_SOURCE2             (BCM2711_LOCAL_REGS_BASE + 0x78)
-#define BCM2711_LOCAL_FIQ_SOURCE3             (BCM2711_LOCAL_REGS_BASE + 0x7c)
-
-/**
- * @name Raspberry Pi 4 Mailbox registers
- *
- * @{
- */
-
-
-
-#define BCM2711_MAILBOX_00_WRITE_SET_BASE               0x4C000080
-#define BCM2711_MAILBOX_01_WRITE_SET_BASE               0x4C000084
-#define BCM2711_MAILBOX_02_WRITE_SET_BASE               0x4C000088
-#define BCM2711_MAILBOX_03_WRITE_SET_BASE               0x4C00008C
-#define BCM2711_MAILBOX_04_WRITE_SET_BASE               0x4C000090
-#define BCM2711_MAILBOX_05_WRITE_SET_BASE               0x4C000094
-#define BCM2711_MAILBOX_06_WRITE_SET_BASE               0x4C000098
-#define BCM2711_MAILBOX_07_WRITE_SET_BASE               0x4C00009C
-#define BCM2711_MAILBOX_08_WRITE_SET_BASE               0x4C0000A0
-#define BCM2711_MAILBOX_09_WRITE_SET_BASE               0x4C0000A4
-#define BCM2711_MAILBOX_10_WRITE_SET_BASE               0x4C0000A8
-#define BCM2711_MAILBOX_11_WRITE_SET_BASE               0x4C0000AC
-#define BCM2711_MAILBOX_12_WRITE_SET_BASE               0x4C0000B0
-#define BCM2711_MAILBOX_13_WRITE_SET_BASE               0x4C0000B4
-#define BCM2711_MAILBOX_14_WRITE_SET_BASE               0x4C0000B8
-#define BCM2711_MAILBOX_15_WRITE_SET_BASE               0x4C0000BC
-
-#define BCM2711_MAILBOX_00_READ_CLEAR_BASE              0x4C0000C0
-#define BCM2711_MAILBOX_01_READ_CLEAR_BASE              0x4C0000C4
-#define BCM2711_MAILBOX_02_READ_CLEAR_BASE              0x4C0000C8
-#define BCM2711_MAILBOX_03_READ_CLEAR_BASE              0x4C0000CC
-#define BCM2711_MAILBOX_04_READ_CLEAR_BASE              0x4C0000D0
-#define BCM2711_MAILBOX_05_READ_CLEAR_BASE              0x4C0000D4
-#define BCM2711_MAILBOX_06_READ_CLEAR_BASE              0x4C0000D8
-#define BCM2711_MAILBOX_07_READ_CLEAR_BASE              0x4C0000DC
-#define BCM2711_MAILBOX_08_READ_CLEAR_BASE              0x4C0000E0
-#define BCM2711_MAILBOX_09_READ_CLEAR_BASE              0x4C0000E4
-#define BCM2711_MAILBOX_10_READ_CLEAR_BASE              0x4C0000E8
-#define BCM2711_MAILBOX_11_READ_CLEAR_BASE              0x4C0000EC
-#define BCM2711_MAILBOX_12_READ_CLEAR_BASE              0x4C0000F0
-#define BCM2711_MAILBOX_13_READ_CLEAR_BASE              0x4C0000F4
-#define BCM2711_MAILBOX_14_READ_CLEAR_BASE              0x4C0000F8
-#define BCM2711_MAILBOX_15_READ_CLEAR_BASE              0x4C0000FC
-
-
-/**
- * @name Raspberry Pi 4 ARM_C FIQ and IRQ registers
- *
- * @{
- */
-
-#define BCM2711_ARMC_REGS_BASE                 (RPI_PERIPHERAL_BASE + 0xB200)
-#define BCM2711_ARMC_REGS_SIZE                 0x200
-
-#define BCM2711_ARMC_IRQ0_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x00)
-#define BCM2711_ARMC_IRQ0_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x04)
-#define BCM2711_ARMC_IRQ0_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x08)
-#define BCM2711_ARMC_IRQ0_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x10)
-#define BCM2711_ARMC_IRQ0_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x14)
-#define BCM2711_ARMC_IRQ0_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x18)
-#define BCM2711_ARMC_IRQ0_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x20)
-#define BCM2711_ARMC_IRQ0_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x24)
-#define BCM2711_ARMC_IRQ0_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x28)
-
-#define BCM2711_ARMC_IRQ_STATUS0               (BCM2711_ARMC_REGS_BASE + 0x30)
-#define BCM2711_ARMC_IRQ_STATUS1               (BCM2711_ARMC_REGS_BASE + 0x34)
-#define BCM2711_ARMC_IRQ_STATUS2               (BCM2711_ARMC_REGS_BASE + 0x38)
-
-#define BCM2711_ARMC_IRQ1_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x40)
-#define BCM2711_ARMC_IRQ1_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x44)
-#define BCM2711_ARMC_IRQ1_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x48)
-#define BCM2711_ARMC_IRQ1_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x50)
-#define BCM2711_ARMC_IRQ1_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x54)
-#define BCM2711_ARMC_IRQ1_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x58)
-#define BCM2711_ARMC_IRQ1_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x60)
-#define BCM2711_ARMC_IRQ1_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x64)
-#define BCM2711_ARMC_IRQ1_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x68)
-
-#define BCM2711_ARMC_IRQ2_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x80)
-#define BCM2711_ARMC_IRQ2_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x84)
-#define BCM2711_ARMC_IRQ2_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x88)
-#define BCM2711_ARMC_IRQ2_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x90)
-#define BCM2711_ARMC_IRQ2_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x94)
-#define BCM2711_ARMC_IRQ2_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x98)
-#define BCM2711_ARMC_IRQ2_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0xA0)
-#define BCM2711_ARMC_IRQ2_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0xA4)
-#define BCM2711_ARMC_IRQ2_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0xA8)
-
-#define BCM2711_ARMC_IRQ3_PENDING0             (BCM2711_ARMC_REGS_BASE + 0xC0)
-#define BCM2711_ARMC_IRQ3_PENDING1             (BCM2711_ARMC_REGS_BASE + 0xC4)
-#define BCM2711_ARMC_IRQ3_PENDING2             (BCM2711_ARMC_REGS_BASE + 0xC8)
-#define BCM2711_ARMC_IRQ3_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0xD0)
-#define BCM2711_ARMC_IRQ3_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0xD4)
-#define BCM2711_ARMC_IRQ3_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0xD8)
-#define BCM2711_ARMC_IRQ3_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0xE0)
-#define BCM2711_ARMC_IRQ3_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0xE4)
-#define BCM2711_ARMC_IRQ3_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0xE8)
-
-
-
-#define BCM2711_ARMC_FIQ0_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x100)
-#define BCM2711_ARMC_FIQ0_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x104)
-#define BCM2711_ARMC_FIQ0_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x108)
-#define BCM2711_ARMC_FIQ0_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x110)
-#define BCM2711_ARMC_FIQ0_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x114)
-#define BCM2711_ARMC_FIQ0_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x118)
-#define BCM2711_ARMC_FIQ0_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x120)
-#define BCM2711_ARMC_FIQ0_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x124)
-#define BCM2711_ARMC_FIQ0_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x128)
-
-#define BCM2711_ARMC_FIQ1_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x140)
-#define BCM2711_ARMC_FIQ1_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x144)
-#define BCM2711_ARMC_FIQ1_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x148)
-#define BCM2711_ARMC_FIQ1_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x150)
-#define BCM2711_ARMC_FIQ1_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x154)
-#define BCM2711_ARMC_FIQ1_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x158)
-#define BCM2711_ARMC_FIQ1_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x160)
-#define BCM2711_ARMC_FIQ1_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x164)
-#define BCM2711_ARMC_FIQ1_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x168)
-
-#define BCM2711_ARMC_FIQ2_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x180)
-#define BCM2711_ARMC_FIQ2_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x184)
-#define BCM2711_ARMC_FIQ2_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x188)
-#define BCM2711_ARMC_FIQ2_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x190)
-#define BCM2711_ARMC_FIQ2_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x194)
-#define BCM2711_ARMC_FIQ2_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x198)
-#define BCM2711_ARMC_FIQ2_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x1A0)
-#define BCM2711_ARMC_FIQ2_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x1A4)
-#define BCM2711_ARMC_FIQ2_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x1A8)
-
-#define BCM2711_ARMC_FIQ3_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x1C0)
-#define BCM2711_ARMC_FIQ3_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x1C4)
-#define BCM2711_ARMC_FIQ3_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x1C8)
-#define BCM2711_ARMC_FIQ3_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x1D0)
-#define BCM2711_ARMC_FIQ3_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x1D4)
-#define BCM2711_ARMC_FIQ3_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x1D8)
-#define BCM2711_ARMC_FIQ3_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x1E0)
-#define BCM2711_ARMC_FIQ3_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x1E4)
-#define BCM2711_ARMC_FIQ3_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x1E8)
-
-#define BCM2711_ARMC_SWIRQ_SET                 (BCM2711_ARMC_REGS_BASE + 0x1F0)
-#define BCM2711_ARMC_SWIRQ_CLEAR               (BCM2711_ARMC_REGS_BASE + 0x1F4)
-
-
-
-
-
-/** @} */
-
-#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
diff --git a/bsps/aarch64/raspberrypi/include/bsp/start/bspstartmmu.h b/bsps/aarch64/raspberrypi/include/bsp/start/bspstartmmu.h
new file mode 100644
index 0000000000..cb1b24ac72
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/include/bsp/start/bspstartmmu.h
@@ -0,0 +1,8 @@
+#ifndef LIBBSP_AARCH64_RASPBERRYPI_BSP_START_BSPSTARTMMU_H
+#define LIBBSP_AARCH64_RASPBERRYPI_BSP_START_BSPSTARTMMU_H
+
+#include <bsp/start.h>
+
+BSP_START_TEXT_SECTION void bsp_start_mmu_setup(void);
+
+#endif
diff --git a/bsps/aarch64/raspberrypi/start/bspstart.c b/bsps/aarch64/raspberrypi/start/bspstart.c
index 368c5d0d08..03d5ae4c77 100644
--- a/bsps/aarch64/raspberrypi/start/bspstart.c
+++ b/bsps/aarch64/raspberrypi/start/bspstart.c
@@ -3,13 +3,14 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ * @ingroup RTEMSBSPsAArch64RaspberryPi
  *
- * @brief BSP Startup
+ * @brief BSP startup routines
  */
 
 /*
  * Copyright (C) 2022 Mohd Noor Aman
+ * Copyright (C) 2023 Utkarsh Verma
  *
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,16 +35,13 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <bsp.h>
 #include <bsp/bootcard.h>
 #include <bsp/irq-generic.h>
 #include <bsp/linker-symbols.h>
+#include <stdint.h>
 
-void bsp_start( void )
-{
-  bsp_interrupt_initialize();
-  rtems_cache_coherent_add_area(
-    bsp_section_nocacheheap_begin,
-    (uintptr_t) bsp_section_nocacheheap_size
-  );
+void bsp_start(void) {
+    bsp_interrupt_initialize();
+    rtems_cache_coherent_add_area(bsp_section_nocacheheap_begin,
+                                  (uintptr_t)bsp_section_nocacheheap_size);
 }
diff --git a/bsps/aarch64/raspberrypi/start/bspstarthooks.c b/bsps/aarch64/raspberrypi/start/bspstarthooks.c
index fe0fe77c09..2444767874 100644
--- a/bsps/aarch64/raspberrypi/start/bspstarthooks.c
+++ b/bsps/aarch64/raspberrypi/start/bspstarthooks.c
@@ -3,13 +3,14 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ * @ingroup RTEMSBSPsAArch64RaspberryPi
  *
  * @brief BSP Startup Hooks
  */
 
 /*
  * Copyright (C) 2022 Mohd Noor Aman
+ * Copyright (C) 2023 Utkarsh Verma
  *
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,20 +35,15 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <bsp.h>
-#include <bsp/irq-generic.h>
-#include <bsp/start.h>
-#include <rtems/score/cpu.h>
+#include "bsp/start/bspstartmmu.h"
 
-BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
-{
-  /* Do nothing */
+BSP_START_TEXT_SECTION void bsp_start_hook_0(void) {
+    /* Do nothing */
 }
 
-BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
-{
-  AArch64_start_set_vector_base();
-  bsp_start_copy_sections();
-  raspberrypi_4_setup_mmu_and_cache();
-  bsp_start_clear_bss();
-}
\ No newline at end of file
+BSP_START_TEXT_SECTION void bsp_start_hook_1(void) {
+    AArch64_start_set_vector_base();
+    bsp_start_copy_sections();
+    bsp_start_mmu_setup();
+    bsp_start_clear_bss();
+}
diff --git a/bsps/aarch64/raspberrypi/start/bspstartmmu.c b/bsps/aarch64/raspberrypi/start/bspstartmmu.c
index 18a9a112b0..9a5824e29a 100644
--- a/bsps/aarch64/raspberrypi/start/bspstartmmu.c
+++ b/bsps/aarch64/raspberrypi/start/bspstartmmu.c
@@ -3,13 +3,14 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ * @ingroup RTEMSBSPsAArch64RaspberryPi
  *
  * @brief This source file contains the default MMU tables and setup.
  */
 
 /*
  * Copyright (C) 2022 Mohd Noor Aman
+ * Copyright (C) 2023 Utkarsh Verma
  *
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,51 +35,34 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <bsp.h>
-#include <bsp/start.h>
+#include "bsp/start/bspstartmmu.h"
+
 #include <bsp/aarch64-mmu.h>
-#include <bsp/raspberrypi.h>
-#include <libcpu/mmu-vmsav8-64.h>
 
+#include "bsp.h"
 
 BSP_START_DATA_SECTION static const aarch64_mmu_config_entry
-raspberrypi_4_mmu_config_table[] = {
-  AARCH64_MMU_DEFAULT_SECTIONS,
-
-  { /* RPI peripheral address */
-    .begin = (unsigned)RPI_PERIPHERAL_BASE,
-    .end = (unsigned)RPI_PERIPHERAL_BASE + (unsigned)RPI_PERIPHERAL_SIZE,
-    .flags = AARCH64_MMU_DEVICE
-  },
-
-  { /* RPI ARM local registers */
-    .begin = (unsigned)BCM2711_LOCAL_REGS_BASE,
-    .end = (unsigned)BCM2711_LOCAL_REGS_BASE + (unsigned)BCM2711_LOCAL_REGS_SIZE,
-    .flags = AARCH64_MMU_DEVICE
-  },
-
-  { /* RPI GIC Interface address */
-    .begin = 0xFF800000U,
-    .end = 0xFFA00000U,
-    .flags = AARCH64_MMU_DEVICE
-  }
-
+    bsp_mmu_config_table[] = {
+        AARCH64_MMU_DEFAULT_SECTIONS,
+        {
+            // UART0
+            .begin = BSP_UART0_BASE,
+            .end   = BSP_UART0_BASE + BSP_UART0_SIZE,
+            .flags = AARCH64_MMU_DEVICE,
+        },
+        {
+            /* Interrupts */
+            .begin = BSP_GIC_BASE,
+            .end   = BSP_GIC_BASE + BSP_GIC_SIZE,
+            .flags = AARCH64_MMU_DEVICE,
+        },
 };
-/*
- * Make weak and let the user override.
- */
-BSP_START_TEXT_SECTION void
-raspberrypi_4_setup_mmu_and_cache( void ) __attribute__ ((weak));
 
-BSP_START_TEXT_SECTION void
-raspberrypi_4_setup_mmu_and_cache( void )
-{
-  aarch64_mmu_setup();
+BSP_START_TEXT_SECTION void bsp_start_mmu_setup(void) {
+    aarch64_mmu_setup();
 
-  aarch64_mmu_setup_translation_table(
-    &raspberrypi_4_mmu_config_table[ 0 ],
-    RTEMS_ARRAY_SIZE( raspberrypi_4_mmu_config_table )
-  );
+    aarch64_mmu_setup_translation_table(
+        &bsp_mmu_config_table[0], RTEMS_ARRAY_SIZE(bsp_mmu_config_table));
 
-  aarch64_mmu_enable();
-}
\ No newline at end of file
+    aarch64_mmu_enable();
+}
diff --git a/spec/build/bsps/aarch64/raspberrypi/abi.yml b/spec/build/bsps/aarch64/raspberrypi/abi.yml
index 38a8d8bc8f..63c2afbea6 100644
--- a/spec/build/bsps/aarch64/raspberrypi/abi.yml
+++ b/spec/build/bsps/aarch64/raspberrypi/abi.yml
@@ -1,19 +1,26 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-string: null
-- split: null
-- env-append: null
-build-type: option
 copyrights:
-- Copyright (C) 2022 Mohd Noor Aman
-default:
-- enabled-by: true
-  value:
-  - -mcpu=cortex-a72
-  - -march=armv8-a
-description: |
-  ABI flags
+  - Copyright (C) 2022 Mohd Noor Aman
+  - Copyright (C) 2023 Utkarsh Verma
+
+type: build
 enabled-by: true
-links: []
+
+build-type: option
 name: ABI_FLAGS
-type: build
+description: ABI flags
+
+actions:
+  - get-string: null
+  - split: null
+  - env-append: null
+
+default:
+  - enabled-by:
+      - aarch64/raspberrypi4b
+    value:
+      - -mcpu=cortex-a72
+      - -march=armv8-a
+      - -mstrict-align
+
+links: []
diff --git a/spec/build/bsps/aarch64/raspberrypi/bsp4b.yml b/spec/build/bsps/aarch64/raspberrypi/bsp4b.yml
new file mode 100644
index 0000000000..058f97d1eb
--- /dev/null
+++ b/spec/build/bsps/aarch64/raspberrypi/bsp4b.yml
@@ -0,0 +1,23 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+  - Copyright (C) 2022 Mohd Noor Aman
+  - Copyright (C) 2023 Utkarsh Verma
+
+type: build
+enabled-by: true
+
+build-type: bsp
+arch: aarch64
+bsp: raspberrypi4b
+family: raspberrypi
+cflags: []
+cppflags: []
+includes: []
+install: []
+source: []
+
+links:
+  - role: build-dependency
+    uid: grp4b
+  - role: build-dependency
+    uid: linkcmds
diff --git a/spec/build/bsps/aarch64/raspberrypi/bspraspberrypi4.yml b/spec/build/bsps/aarch64/raspberrypi/bspraspberrypi4.yml
deleted file mode 100644
index a579c094ba..0000000000
--- a/spec/build/bsps/aarch64/raspberrypi/bspraspberrypi4.yml
+++ /dev/null
@@ -1,72 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-arch: aarch64
-bsp: raspberrypi4b
-build-type: bsp
-cflags: []
-copyrights:
-- Copyright (C) 2022 Mohd Noor Aman
-cppflags: []
-enabled-by: true
-family: raspberrypi
-includes: []
-install:
-- destination: ${BSP_INCLUDEDIR}
-  source:
-  - bsps/aarch64/raspberrypi/include/bsp.h
-  - bsps/aarch64/raspberrypi/include/tm27.h
-- destination: ${BSP_INCLUDEDIR}/bsp
-  source:
-  - bsps/aarch64/raspberrypi/include/bsp/irq.h
-  - bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h
-links:
-- role: build-dependency
-  uid: ../grp
-- role: build-dependency
-  uid: ../start
-- role: build-dependency
-  uid: ../optmmupages
-- role: build-dependency
-  uid: ../optgtusevirt
-- role: build-dependency
-  uid: ../optgtuseps
-- role: build-dependency
-  uid: abi
-- role: build-dependency
-  uid: ../../optcachedata
-- role: build-dependency
-  uid: ../../optcacheinst
-- role: build-dependency
-  uid: ../../opto2
-- role: build-dependency
-  uid: ../../bspopts
-- role: build-dependency
-  uid: linkercmds
-- role: build-dependency
-  uid: ../../obj
-- role: build-dependency
-  uid: ../../objirq
-source:
-- bsps/aarch64/raspberrypi/console/console.c
-- bsps/aarch64/raspberrypi/start/bspstart.c
-- bsps/aarch64/raspberrypi/start/bspstarthooks.c
-- bsps/aarch64/raspberrypi/start/bspstartmmu.c
-- bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c
-- bsps/aarch64/shared/cache/cache.c
-- bsps/aarch64/shared/mmu/vmsav8-64.c
-- bsps/shared/dev/clock/arm-generic-timer.c
-- bsps/shared/dev/irq/arm-gicv2.c
-- bsps/shared/dev/irq/arm-gicv2-get-attributes.c
-- bsps/shared/dev/serial/console-termios-init.c
-- bsps/shared/dev/serial/console-termios.c
-- bsps/shared/dev/serial/arm-pl011.c
-- bsps/shared/dev/getentropy/getentropy-cpucounter.c
-- bsps/shared/dev/btimer/btimer-cpucounter.c
-- bsps/shared/irq/irq-default-handler.c
-- bsps/shared/start/bspfatal-default.c
-- bsps/shared/start/bspreset-arm-psci.c
-- bsps/shared/start/gettargethash-default.c
-- bsps/shared/start/sbrk.c
-- bsps/shared/start/wkspaceinitone.c
-- bsps/shared/start/mallocinitmulti.c
-- bsps/shared/start/bspgetworkarea-default.c
-type: build
diff --git a/spec/build/bsps/aarch64/raspberrypi/grp.yml b/spec/build/bsps/aarch64/raspberrypi/grp.yml
new file mode 100644
index 0000000000..4e6b022e3c
--- /dev/null
+++ b/spec/build/bsps/aarch64/raspberrypi/grp.yml
@@ -0,0 +1,49 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+  - Copyright (C) 2022 Mohd Noor Aman
+  - Copyright (C) 2023 Utkarsh Verma
+
+type: build
+enabled-by: true
+
+build-type: group
+cflags: []
+cppflags: []
+cxxflags: []
+includes: []
+install: []
+ldflags: []
+use-after: []
+use-before: []
+
+links:
+  - role: build-dependency
+    uid: abi
+  - role: build-dependency
+    uid: obj
+  - role: build-dependency
+    uid: optclockpl011freq
+  - role: build-dependency
+    uid: optconsolebaud
+  - role: build-dependency
+    uid: ../grp
+  - role: build-dependency
+    uid: ../start
+  - role: build-dependency
+    uid: ../optmmupages
+  - role: build-dependency
+    uid: ../optgtusevirt
+  - role: build-dependency
+    uid: ../optgtuseps
+  - role: build-dependency
+    uid: ../../optcachedata
+  - role: build-dependency
+    uid: ../../optcacheinst
+  - role: build-dependency
+    uid: ../../opto2
+  - role: build-dependency
+    uid: ../../bspopts
+  - role: build-dependency
+    uid: ../../obj
+  - role: build-dependency
+    uid: ../../objirq
diff --git a/spec/build/bsps/aarch64/raspberrypi/grp4b.yml b/spec/build/bsps/aarch64/raspberrypi/grp4b.yml
new file mode 100644
index 0000000000..8a4b8c0370
--- /dev/null
+++ b/spec/build/bsps/aarch64/raspberrypi/grp4b.yml
@@ -0,0 +1,26 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+  - Copyright (C) 2022 Mohd Noor Aman
+  - Copyright (C) 2023 Utkarsh Verma
+
+type: build
+enabled-by: true
+
+build-type: group
+cflags: []
+cppflags: []
+cxxflags: []
+includes: []
+
+install:
+  - destination: ${BSP_INCLUDEDIR}/bsp
+    source:
+      - bsps/aarch64/raspberrypi/include/bsp/bcm2711.h
+
+ldflags: []
+use-after: []
+use-before: []
+
+links:
+  - role: build-dependency
+    uid: grp
diff --git a/spec/build/bsps/aarch64/raspberrypi/linkercmds.yml b/spec/build/bsps/aarch64/raspberrypi/linkcmds.yml
similarity index 90%
rename from spec/build/bsps/aarch64/raspberrypi/linkercmds.yml
rename to spec/build/bsps/aarch64/raspberrypi/linkcmds.yml
index 701f9f935c..6988d54422 100644
--- a/spec/build/bsps/aarch64/raspberrypi/linkercmds.yml
+++ b/spec/build/bsps/aarch64/raspberrypi/linkcmds.yml
@@ -1,10 +1,19 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+  - Copyright (C) 2022 Mohd Noor Aman
+  - Copyright (C) 2023 Utkarsh Verma
+
+type: build
+enabled-by: true
+
 build-type: config-file
+
 content: |
   /* SPDX-License-Identifier: BSD-2-Clause */
 
   /*
    * Copyright (C) 2022 Mohd Noor Aman
+   * Copyright (C) 2023 Utkarsh Verma
    *
    * Redistribution and use in source and binary forms, with or without
    * modification, are permitted provided that the following conditions
@@ -29,8 +38,8 @@ content: |
    */
 
   MEMORY {
-  RAM_MMU  : ORIGIN = 0x0, LENGTH = (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
-  RAM      : ORIGIN = 0x80000, LENGTH = 1024M
+    RAM_MMU  : ORIGIN = 0x0, LENGTH = (CONSTANT(COMMONPAGESIZE) * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
+    RAM      : ORIGIN = 0x80000, LENGTH = 1024M
   }
 
   REGION_ALIAS ("REGION_START",          RAM);
@@ -51,11 +60,11 @@ content: |
   REGION_ALIAS ("REGION_NOCACHE",        RAM);
   REGION_ALIAS ("REGION_NOCACHE_LOAD",   RAM);
 
-  bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
+  bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1K;
 
   bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
 
-  bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 1024;
+  bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 1K;
 
   bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
 
@@ -67,10 +76,8 @@ content: |
   OUTPUT_ARCH (aarch64)
 
   INCLUDE linkcmds.base
-copyrights:
-- Copyright (C) 2022 Mohd Noor Aman
-enabled-by: true
+
 install-path: ${BSP_LIBDIR}
-links: []
 target: linkcmds
-type: build
+
+links: []
diff --git a/spec/build/bsps/aarch64/raspberrypi/obj.yml b/spec/build/bsps/aarch64/raspberrypi/obj.yml
new file mode 100644
index 0000000000..6a57210d36
--- /dev/null
+++ b/spec/build/bsps/aarch64/raspberrypi/obj.yml
@@ -0,0 +1,50 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+  - Copyright (C) 2022 Mohd Noor Aman
+  - Copyright (C) 2023 Utkarsh Verma
+
+type: build
+enabled-by: true
+
+build-type: objects
+cflags: []
+cppflags: []
+cxxflags: []
+includes: []
+
+install:
+  - destination: ${BSP_INCLUDEDIR}
+    source:
+      - bsps/aarch64/raspberrypi/include/bsp.h
+      - bsps/aarch64/raspberrypi/include/tm27.h
+  - destination: ${BSP_INCLUDEDIR}/bsp
+    source:
+      - bsps/aarch64/raspberrypi/include/bsp/irq.h
+
+source:
+  - bsps/aarch64/shared/cache/cache.c
+  - bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c
+  - bsps/aarch64/shared/mmu/vmsav8-64.c
+  - bsps/aarch64/raspberrypi/console/console.c
+  - bsps/aarch64/raspberrypi/start/bspstart.c
+  - bsps/aarch64/raspberrypi/start/bspstarthooks.c
+  - bsps/aarch64/raspberrypi/start/bspstartmmu.c
+  - bsps/shared/dev/clock/arm-generic-timer.c
+  - bsps/shared/dev/irq/arm-gicv2.c
+  - bsps/shared/dev/irq/arm-gicv2-get-attributes.c
+  - bsps/shared/dev/serial/console-termios-init.c
+  - bsps/shared/dev/serial/console-termios.c
+  - bsps/shared/dev/getentropy/getentropy-cpucounter.c
+  - bsps/shared/dev/btimer/btimer-cpucounter.c
+  - bsps/shared/irq/irq-default-handler.c
+  - bsps/shared/start/bspfatal-default.c
+  - bsps/shared/start/bspreset-arm-psci.c
+  - bsps/shared/start/gettargethash-default.c
+  - bsps/shared/start/sbrk.c
+  - bsps/shared/start/wkspaceinitone.c
+  - bsps/shared/start/mallocinitmulti.c
+  - bsps/shared/start/bspgetworkarea-default.c
+
+links:
+  - role: build-dependency
+    uid: objconsolepl011
diff --git a/spec/build/bsps/aarch64/raspberrypi/objconsolepl011.yml b/spec/build/bsps/aarch64/raspberrypi/objconsolepl011.yml
new file mode 100644
index 0000000000..0c5135cdc5
--- /dev/null
+++ b/spec/build/bsps/aarch64/raspberrypi/objconsolepl011.yml
@@ -0,0 +1,24 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+  - Copyright (C) 2022 Mohd Noor Aman
+  - Copyright (C) 2023 Utkarsh Verma
+
+type: build
+enabled-by: true
+
+build-type: objects
+cflags: []
+cppflags: []
+cxxflags: []
+includes: []
+
+install:
+  - destination: ${BSP_INCLUDEDIR}/dev/serial
+    source:
+      - bsps/include/dev/serial/arm-pl011.h
+      - bsps/include/dev/serial/arm-pl011-regs.h
+
+source:
+  - bsps/shared/dev/serial/arm-pl011.c
+
+links: []
diff --git a/spec/build/bsps/aarch64/raspberrypi/optclockpl011freq.yml b/spec/build/bsps/aarch64/raspberrypi/optclockpl011freq.yml
new file mode 100644
index 0000000000..e6432c7010
--- /dev/null
+++ b/spec/build/bsps/aarch64/raspberrypi/optclockpl011freq.yml
@@ -0,0 +1,23 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+  - Copyright (C) 2023 Utkarsh Verma
+
+type: build
+enabled-by: true
+
+build-type: option
+name: BSP_PL011_CLOCK_FREQ
+description: PL011 UART clock frequency in Hz
+
+actions:
+  - get-integer: null
+  - define: null
+
+default:
+  - enabled-by:
+      - aarch64/raspberrypi4b
+    value: 48000000
+
+format: '{}'
+
+links: []
diff --git a/spec/build/bsps/aarch64/raspberrypi/optconsolebaud.yml b/spec/build/bsps/aarch64/raspberrypi/optconsolebaud.yml
new file mode 100644
index 0000000000..bff49ad71a
--- /dev/null
+++ b/spec/build/bsps/aarch64/raspberrypi/optconsolebaud.yml
@@ -0,0 +1,23 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+  - Copyright (C) 2023 Utkarsh Verma
+
+type: build
+enabled-by: true
+
+build-type: option
+name: BSP_CONSOLE_BAUD
+description: Default baudrate for the console device.
+
+actions:
+  - get-integer: null
+  - define: null
+
+default:
+  - enabled-by:
+      - aarch64/raspberrypi4b
+    value: 115200
+
+format: '{}'
+
+links: []
-- 
2.41.0



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