[PATCH] bsp/riscv: Add a new SiFive Unleashed QEMU bsp

[Amna]

This commits add a new SiFive Unleashed bsp which follows the RV64IMAC RISC-V
Architecture. It can be run on QEMU provided by the RTEMS source builder's
devel/qemu bset. This BSP requires a minimum of 128MB (Default) of RAM size
which can be changed using the RISCV_RAM_REGION_SIZE configuration option. RAM
start region is the default 0x80000000. It uses the sifive UART for console.
Maximum 5 cores are present in the BSP.

NOTE: RTEMS_SMP flags needs to be set true in the config.ini when building the
BSP as QEMU requires at least 2 cores for running the Sifive_u machine. When
built with no SMP flag, QEMU would throw random text to the terminal when
running the executable. Same behavior  can be seen when other RV* bsp are built
without SMP flag and machine are having more than 1 core.
---
 spec/build/bsps/riscv/optextirqmax.yml        |  2 ++
 spec/build/bsps/riscv/optramsize.yml          |  2 ++
 spec/build/bsps/riscv/riscv/abi.yml           |  4 +++-
 spec/build/bsps/riscv/riscv/bspsifive_u.yml   | 19 +++++++++++++++++++
 spec/build/bsps/riscv/riscv/optsifiveuart.yml |  1 +
 spec/build/cpukit/optsmp.yml                  |  1 +
 6 files changed, 28 insertions(+), 1 deletion(-)
 create mode 100644 spec/build/bsps/riscv/riscv/bspsifive_u.yml

diff --git a/spec/build/bsps/riscv/optextirqmax.yml b/spec/build/bsps/riscv/optextirqmax.yml
index 5a0fc9a766..7071abda35 100644
--- a/spec/build/bsps/riscv/optextirqmax.yml
+++ b/spec/build/bsps/riscv/optextirqmax.yml
@@ -8,6 +8,8 @@ copyrights:
 default:
 - enabled-by: riscv/mpfs64imafdc
   value: 187
+- enabled-by: riscv/sifive_u
+  value: 53
 - enabled-by: true
   value: 128
 description: |
diff --git a/spec/build/bsps/riscv/optramsize.yml b/spec/build/bsps/riscv/optramsize.yml
index 876a447087..43436adde7 100644
--- a/spec/build/bsps/riscv/optramsize.yml
+++ b/spec/build/bsps/riscv/optramsize.yml
@@ -17,6 +17,8 @@ default:
   value: 0x01000000
 - enabled-by: riscv/kendrytek210
   value: 0x00600000
+- enabled-by: riscv/sifive_u
+  value: 0x8000000
 - enabled-by: true
   value: 0x04000000
 description: ''
diff --git a/spec/build/bsps/riscv/riscv/abi.yml b/spec/build/bsps/riscv/riscv/abi.yml
index bca6512f20..4f55997216 100644
--- a/spec/build/bsps/riscv/riscv/abi.yml
+++ b/spec/build/bsps/riscv/riscv/abi.yml
@@ -22,7 +22,9 @@ default:
   - -march=rv64imafd
   - -mabi=lp64d
   - -mcmodel=medany
-- enabled-by: riscv/rv64imac
+- enabled-by: 
+  - riscv/rv64imac
+  - riscv/sifive_u
   value:
   - -march=rv64imac
   - -mabi=lp64
diff --git a/spec/build/bsps/riscv/riscv/bspsifive_u.yml b/spec/build/bsps/riscv/riscv/bspsifive_u.yml
new file mode 100644
index 0000000000..b732932eaa
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/bspsifive_u.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: sifive_u
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2023 Amna Mannan
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/riscv/riscv/optsifiveuart.yml b/spec/build/bsps/riscv/riscv/optsifiveuart.yml
index 8ff27d0275..ec1fd761e5 100644
--- a/spec/build/bsps/riscv/riscv/optsifiveuart.yml
+++ b/spec/build/bsps/riscv/riscv/optsifiveuart.yml
@@ -9,6 +9,7 @@ default:
 - enabled-by:
   - riscv/kendrytek210
   - riscv/frdme310arty
+  - riscv/sifive_u
   value: true
 - enabled-by: true
   value: false
diff --git a/spec/build/cpukit/optsmp.yml b/spec/build/cpukit/optsmp.yml
index 28b9bd4cd8..0936a42412 100644
--- a/spec/build/cpukit/optsmp.yml
+++ b/spec/build/cpukit/optsmp.yml
@@ -50,6 +50,7 @@ enabled-by:
 - riscv/rv64imafdc_medany
 - riscv/rv64imafd_medany
 - riscv/kendrytek210
+- riscv/sifive_u
 - sparc/erc32
 - sparc/gr712rc
 - sparc/gr740
-- 
2.25.1