Question regarding ARMV7M FPU context switch and ISRs

[Sebastian Huber]

Hello Cedric,

On 08.02.24 10:53, Cedric Berger wrote:
> Hello,
> 
> I've a question: does RTEMS really wants to support FPU operations in ISRs?
> 
> Because if the answer is "no", then I believe that we could simplify the 
> RTEMS code (and for me the mental model of the whole thing) by running 
> the FPU with both FPCCR.ASPEN and FPCCR.LSPEN = 0.
> 
> This mean that during IRQ/exception, the simple exception frame (32 
> bytes) would always be used instead of a combination of the simple and 
> extended frame (32 or 116 bytes).
> 
> This would then improve the real-time guarantees of the system, by 
> having a shorter and more deterministic IRQ response time.

if you don't use the FPU in ISRs, then the overhead is just a space 
overhead with the lazy FPU save/restore. If you switch from an ISR to 
another thread you have to save/restore the volatile FPU context anyway.

> 
> This would also simplify the context switching code, by centralizing of 
> the saving of the FPU context in RTEMS only, and enabling optimisation 
> like only saving/restoring the FPU when switching between tasks defined 
> with RTEMS_FLOATING_POINT.
> 
> What do you think? I'm missing something? would it be a good idea?

 From experience, working with the RTEMS_FLOATING_POINT in applications 
is quite annoying. Is there really a measurable and significant 
performance improvement if you enable the deferred FPU switching? Can 
you guarantee that the compiler will not generate FPU or vector 
instructions for integer operations? In this version or a GCC release in 
the future?

> 
> I would be willing to work on that is there is some kind of agreement here.

If you change the ARMv7-M CPU port to use the deferred FPU switching, 
then you surely break existing applications which then have to use 
RTEMS_FLOATING_POINT. I would do this only if there would be a clear and 
measurable performance improvement. For the measurements we would need a 
benchmark.

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