IIRC Eric Norum was looking at this.<br><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Dec 4, 2012 at 1:19 PM, Joel Sherrill <span dir="ltr"><<a href="mailto:joel.sherrill@oarcorp.com" target="_blank">joel.sherrill@oarcorp.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">On 12/4/2012 11:28 AM, Sebastian Huber wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hello,<br>
<br>
On 04/12/12 16:09, Matthias Goldhoorn wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hello Devel's,<br>
we are currently thinking about using rtems on out Suzaku-S Boards.<br>
This boards carry an Xilinx Spartan FPGA, we currently using an<br>
Microblaze Processor and µCLinux.<br>
We maybe want to swap no rtems.<br>
<br>
First and most important question:<br>
1. Is there any ongoing work to create BSPs for the microblaze arch?,<br>
</blockquote>
I don't know.<br>
</blockquote>
<br></div>
There was some email on the list in the past few months from someone who<br>
appeared to be working on this. Search the email list for that.<br>
<br>
I have a branch in my personal repo with a starting point for a port with a<br>
BSP cut for the simulator in GDB. See <a href="http://git.rtems.org/joel/rtems.git/" target="_blank">http://git.rtems.org/joel/<u></u>rtems.git/</a><div class="im"><br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
I already saw that the gcc-toolchain was already created to build for<br>
this target.<br>
2. If not, how log you are assuming do an Computer Scientist without<br>
any RTEMS knowledge need to create an BSP for this?<br>
<br>
</blockquote>
Lets suppose the tool chain works, then the next step is to do the basic<br>
CPU port. This includes primitive ABI settings like stack alignment and<br>
more complex stuff like context switching and interrupt handling. You<br>
have to do the low level system initialization on a simulator or<br>
evaluation board (set up C runtime environment, cache, memory<br>
controller, PLL, etc.). This is largely operating system independent.<br>
You have to create drivers for basic thinks like the clock tick and<br>
console. You have to learn the development environment for the FPGA.<br>
It is hard to estimate a time frame for all of this. I would say its<br>
more than three weeks. It might be more efficient to hire a company for<br>
basic support.<br>
<br>
</blockquote></div>
Agreed. I have done a lot of ports to new architectures and the time varies<br>
based on availability and ease of use of simulator, what can be done on<br>
the simulator, and how complicated the desired BSP really is.<br>
<br>
I don't like to do marketing on the mailing list but if you want someone to<br>
do this or just consulting on the steps, email me and Sebastian off list.<span class="HOEnZb"><font color="#888888"><br>
<br>
-- <br>
Joel Sherrill, Ph.D. Director of Research & Development<br>
joel.sherrill@OARcorp.com On-Line Applications Research<br>
Ask me about RTEMS: a free RTOS Huntsville AL 35805<br>
Support Available <a href="tel:%28256%29%20722-9985" value="+12567229985" target="_blank">(256) 722-9985</a></font></span><div class="HOEnZb"><div class="h5"><br>
<br>
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