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<body><p dir="ltr">Does this run without faulting on a strict alignment architecture like the MIPS?</p><div class="quote">On Apr 10, 2014 11:24 AM, Ralf Kirchner <ralf.kirchner@embedded-brains.de> wrote:<br type="attribution"></div></body>
<font size="2"><div class="PlainText">---<br>
testsuites/sptests/spcache01/init.c | 81 ++++++++++++++++++++++++++++<br>
testsuites/sptests/spcache01/spcache01.doc | 1 +<br>
testsuites/sptests/spcache01/spcache01.scn | 2 +<br>
3 Dateien geändert, 84 Zeilen hinzugefügt(+)<br>
<br>
diff --git a/testsuites/sptests/spcache01/init.c b/testsuites/sptests/spcache01/init.c<br>
index 2c9d184..4be1040 100644<br>
--- a/testsuites/sptests/spcache01/init.c<br>
+++ b/testsuites/sptests/spcache01/init.c<br>
@@ -37,6 +37,86 @@ const char rtems_test_name[] = "SPCACHE 1";<br>
<br>
CPU_STRUCTURE_ALIGNMENT static int data[1024];<br>
<br>
+static void test_misalignment(void)<br>
+{<br>
+ if (rtems_cache_get_data_line_size() > 0) {<br>
+ rtems_interrupt_lock lock;<br>
+ rtems_interrupt_lock_context lock_context;<br>
+ volatile int *vdata = &data[0];<br>
+ int *tdata = &data[2];<br>
+ const uint32_t LINE_SIZE = rtems_cache_get_data_line_size();<br>
+ int tcount = LINE_SIZE;<br>
+ int vcount = tcount + 3 * LINE_SIZE;<br>
+ size_t tdata_size = tcount * sizeof(data[0]);<br>
+ bool write_through;<br>
+ int i;<br>
+ int end;<br>
+<br>
+ printf("data cache flush and invalidate test with misaligned addresses\n");<br>
+<br>
+ rtems_interrupt_lock_initialize(&lock, "test");<br>
+ rtems_interrupt_lock_acquire(&lock, &lock_context);<br>
+<br>
+ for (i = 0; i < vcount; ++i) {<br>
+ vdata[i] = i;<br>
+ }<br>
+<br>
+ rtems_cache_flush_multiple_data_lines(tdata, tdata_size);<br>
+<br>
+ for (i = 0; i < vcount; ++i) {<br>
+ rtems_test_assert(vdata[i] == i);<br>
+ }<br>
+<br>
+ for (i = 0; i < vcount; ++i) {<br>
+ vdata[i] = ~i;<br>
+ }<br>
+ <br>
+ rtems_cache_invalidate_multiple_data_lines(tdata, tdata_size);<br>
+<br>
+ end = (tdata_size + LINE_SIZE) / sizeof(data[0]);<br>
+<br>
+ write_through = vdata[LINE_SIZE / sizeof(data[0])] == ~LINE_SIZE / sizeof(data[0]);<br>
+ if (write_through) {<br>
+ for (i = 0; i < end; ++i) {<br>
+ rtems_test_assert(vdata[i] == ~i);<br>
+ }<br>
+ } else {<br>
+ for( i = 0; i < end; ++i) {<br>
+ rtems_test_assert(vdata[i] == i);<br>
+ }<br>
+ }<br>
+ i = end;<br>
+ end = i + LINE_SIZE + LINE_SIZE;<br>
+ for( ; i < end; ++i) {<br>
+ rtems_test_assert(vdata[i] == ~i);<br>
+ }<br>
+ <br>
+ for (i = 0; i < vcount; ++i) {<br>
+ vdata[i] = ~i;<br>
+ }<br>
+<br>
+ rtems_cache_flush_multiple_data_lines(tdata, tdata_size);<br>
+ rtems_cache_invalidate_multiple_data_lines(tdata, tdata_size);<br>
+<br>
+ for (i = 0; i < vcount; ++i) {<br>
+ rtems_test_assert(vdata[i] == ~i);<br>
+ }<br>
+<br>
+ rtems_interrupt_lock_release(&lock, &lock_context);<br>
+ rtems_interrupt_lock_destroy(&lock);<br>
+ <br>
+ printf(<br>
+ "data cache operations with misaligned addresses passed the test (%s cache detected)\n",<br>
+ write_through ? "write-through" : "copy-back"<br>
+ );<br>
+ } else {<br>
+ printf(<br>
+ "skip data cache flush and invalidate test with misaligned addresses"<br>
+ " due to cache line size of zero\n"<br>
+ );<br>
+ }<br>
+}<br>
+<br>
static void test_data_flush_and_invalidate(void)<br>
{<br>
if (rtems_cache_get_data_line_size() > 0) {<br>
@@ -376,6 +456,7 @@ static void Init(rtems_task_argument arg)<br>
TEST_BEGIN();<br>
<br>
test_data_flush_and_invalidate();<br>
+ test_misalignment();<br>
test_timing();<br>
<br>
TEST_END();<br>
diff --git a/testsuites/sptests/spcache01/spcache01.doc b/testsuites/sptests/spcache01/spcache01.doc<br>
index bbc8f25..1a56be8 100644<br>
--- a/testsuites/sptests/spcache01/spcache01.doc<br>
+++ b/testsuites/sptests/spcache01/spcache01.doc<br>
@@ -17,3 +17,4 @@ directives:<br>
concepts:<br>
<br>
- Ensure that some cache manager functions work.<br>
+ - Ensure they also work with misaligned addesses<br>
diff --git a/testsuites/sptests/spcache01/spcache01.scn b/testsuites/sptests/spcache01/spcache01.scn<br>
index 8013945..53d3e70 100644<br>
--- a/testsuites/sptests/spcache01/spcache01.scn<br>
+++ b/testsuites/sptests/spcache01/spcache01.scn<br>
@@ -2,6 +2,8 @@<br>
data cache flush and invalidate test<br>
data cache operations by line passed the test<br>
data cache operations by line passed the test (copy-back cache detected)<br>
+data cache flush and invalidate test with misaligned addresses<br>
+data cache operations with misaligned addresses passed the test (copy-back cache detected)<br>
data cache line size 32 bytes<br>
data cache size 262144 bytes<br>
data cache level 1 size 32768 bytes<br>
-- <br>
1.7.10.4<br>
<br>
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