<div dir="ltr">There are not only styles to be corrected. I will send a new version soon.</div><div class="gmail_extra"><br><div class="gmail_quote">2014-09-20 20:41 GMT+02:00 Joel Sherrill <span dir="ltr"><<a href="mailto:joel.sherrill@oarcorp.com" target="_blank">joel.sherrill@oarcorp.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Style comments from me. I will let those who know who the HW comment on that.<br>
<div><div class="h5"><br>
On September 20, 2014 1:23:26 PM CDT, "<a href="mailto:tomasz.gregorek@gmail.com">tomasz.gregorek@gmail.com</a>" <<a href="mailto:tomasz.gregorek@gmail.com">tomasz.gregorek@gmail.com</a>> wrote:<br>
>From: Tomasz Gregorek <<a href="mailto:tomasz.gregorek@gmail.com">tomasz.gregorek@gmail.com</a>><br>
><br>
>Added simple math to caclulate register values for the PLL<br>
>and for the prescalers. It will try to keep 48MHz for the USB OTG FS.<br>
>Also it will slow down Flash memory for the high speeds.<br>
>---<br>
> c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 +<br>
> .../libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h | 41 ++++<br>
> .../libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h | 94 +++++++++<br>
>c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c | 211<br>
>+++++++++++++++++++++<br>
> 4 files changed, 356 insertions(+)<br>
>create mode 100644<br>
>c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h<br>
><br>
>diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h<br>
>b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h<br>
>index 59d13ef..d26f914 100644<br>
>--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h<br>
>+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h<br>
>@@ -55,6 +55,16 @@<br>
><br>
> /** @} */<br>
><br>
>+/**<br>
>+ * @name STM32F4XXXX FLASH<br>
>+ * @{<br>
>+ */<br>
>+<br>
>+#include <bsp/stm32f4xxxx_flash.h><br>
>+#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE +<br>
>0x40023C00))<br>
>+<br>
>+/** @} */<br>
>+<br>
> #include <bsp/stm32_i2c.h><br>
><br>
> /**<br>
>diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h<br>
>b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h<br>
>new file mode 100644<br>
>index 0000000..31b3992<br>
>--- /dev/null<br>
>+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h<br>
>@@ -0,0 +1,41 @@<br>
>+/**<br>
>+ * @file<br>
>+ * @ingroup stm32f4_flash<br>
>+ * @brief STM32F4XXXX FLASH support.<br>
>+ */<br>
>+<br>
>+/*<br>
>+ * Copyright (c) 2014 Tomasz Gregorek. All rights reserved.<br>
>+ *<br>
>+ * <<a href="mailto:tomasz.gregorek@gmial.com">tomasz.gregorek@gmial.com</a>><br>
>+ *<br>
>+ * The license and distribution terms for this file may be<br>
>+ * found in the file LICENSE in this distribution or at<br>
>+ * <a href="http://www.rtems.org/license/LICENSE" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
>+ */<br>
>+<br>
>+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H<br>
>+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H<br>
>+<br>
>+#include <bsp/utility.h><br>
>+<br>
>+/**<br>
>+ * @defgroup stm32f10xxx_flash STM32F4XXXX FLASH Support<br>
>+ * @ingroup stm32f4_flash<br>
>+ * @brief STM32F4FXXX FLASH Support<br>
>+ * @{<br>
>+ */<br>
>+<br>
>+typedef struct {<br>
>+ uint32_t acr;<br>
>+ uint32_t keyr;<br>
>+ uint32_t optkeyr;<br>
>+ uint32_t sr;<br>
>+ uint32_t cr;<br>
>+ uint32_t optcr;<br>
>+ uint32_t optcr1;<br>
>+} stm32f4_flash;<br>
>+<br>
>+/** @} */<br>
>+<br>
>+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */<br>
>diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h<br>
>b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h<br>
>index 8126340..ce85b8e 100644<br>
>--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h<br>
>+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h<br>
>@@ -56,4 +56,98 @@ typedef struct {<br>
><br>
> /** @} */<br>
><br>
>+#define RCC_CR_HSION BSP_BIT32(0)<br>
>+#define RCC_CR_HSIRDY BSP_BIT32(1)<br>
>+#define RCC_CR_HSITRIM 3<br>
>+#define RCC_CR_HSICAL 8<br>
>+#define RCC_CR_HSEON BSP_BIT32(16)<br>
>+#define RCC_CR_HSERDY BSP_BIT32(17)<br>
>+#define RCC_CR_HSEBYP BSP_BIT32(18)<br>
>+#define RCC_CR_CSSON BSP_BIT32(19)<br>
>+#define RCC_CR_PLLON BSP_BIT32(24)<br>
>+#define RCC_CR_PLLRDY BSP_BIT32(25)<br>
>+#define RCC_CR_PLLI2SON BSP_BIT32(26)<br>
>+#define RCC_CR_PLLI2SRDY BSP_BIT32(27)<br>
>+<br>
>+<br>
>+#define RCC_PLLCFGR_PLLM 0<br>
>+#define RCC_PLLCFGR_PLLN 6<br>
>+#define RCC_PLLCFGR_PLLP 16<br>
>+<br>
>+#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32(22)<br>
>+#define RCC_PLLCFGR_PLLSRC_HSI 0<br>
>+<br>
>+#define RCC_PLLCFGR_PLLQ 24<br>
>+<br>
>+<br>
>+#define RCC_CFGR_SW 0<br>
>+#define RCC_CFGR_SW_MASK 3<br>
>+#define RCC_CFGR_SW_HSI 0<br>
>+#define RCC_CFGR_SW_HSE 1<br>
>+#define RCC_CFGR_SW_PLL 2<br>
>+<br>
>+#define RCC_CFGR_SWS 2<br>
>+#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS)<br>
>+<br>
>+#define RCC_CFGR_SWS_HSI 0<br>
>+#define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS)<br>
>+#define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS)<br>
>+<br>
>+#define RCC_CFGR_HPRE 4<br>
>+#define RCC_CFGR_HPRE_BY_1 0<br>
>+#define RCC_CFGR_HPRE_BY_2 ( 8 << RCC_CFGR_HPRE)<br>
>+#define RCC_CFGR_HPRE_BY_4 ( 9 << RCC_CFGR_HPRE)<br>
>+#define RCC_CFGR_HPRE_BY_8 (10 << RCC_CFGR_HPRE)<br>
>+#define RCC_CFGR_HPRE_BY_16 (11 << RCC_CFGR_HPRE)<br>
>+#define RCC_CFGR_HPRE_BY_64 (12 << RCC_CFGR_HPRE)<br>
>+#define RCC_CFGR_HPRE_BY_128 (13 << RCC_CFGR_HPRE)<br>
>+#define RCC_CFGR_HPRE_BY_256 (14 << RCC_CFGR_HPRE)<br>
>+#define RCC_CFGR_HPRE_BY_512 (15 << RCC_CFGR_HPRE)<br>
>+<br>
>+#define RCC_CFGR_PPRE1 10<br>
>+#define RCC_CFGR_PPRE1_BY_1 0<br>
>+#define RCC_CFGR_PPRE1_BY_2 (4 << RCC_CFGR_PPRE1)<br>
>+#define RCC_CFGR_PPRE1_BY_4 (5 << RCC_CFGR_PPRE1)<br>
>+#define RCC_CFGR_PPRE1_BY_8 (6 << RCC_CFGR_PPRE1)<br>
>+#define RCC_CFGR_PPRE1_BY_16 (7 << RCC_CFGR_PPRE1)<br>
>+<br>
>+#define RCC_CFGR_PPRE2 13<br>
>+#define RCC_CFGR_PPRE2_BY_1 0<br>
>+#define RCC_CFGR_PPRE2_BY_2 (4 << RCC_CFGR_PPRE2)<br>
>+#define RCC_CFGR_PPRE2_BY_4 (5 << RCC_CFGR_PPRE2)<br>
>+#define RCC_CFGR_PPRE2_BY_8 (6 << RCC_CFGR_PPRE2)<br>
>+#define RCC_CFGR_PPRE2_BY_16 (7 << RCC_CFGR_PPRE2)<br>
>+<br>
>+#define RCC_CFGR_RTCPRE 16<br>
>+#define RCC_CFGR_RTCPRE_SET(a) (a << RCC_CFGR_RTCPRE)<br>
>+<br>
>+#define RCC_CFGR_MCO1 21<br>
>+#define RCC_CFGR_MCO1_HSI 0<br>
>+#define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1)<br>
>+#define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1)<br>
>+#define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1)<br>
>+<br>
>+#define RCC_CFGR_I2SSRC BSP_BIT32(23)<br>
>+<br>
>+#define RCC_CFGR_MCO1PRE 24<br>
>+#define RCC_CFGR_MCO1PRE_BY_1 0<br>
>+#define RCC_CFGR_MCO1PRE_BY_2 (4 << RCC_CFGR_MCO1PRE)<br>
>+#define RCC_CFGR_MCO1PRE_BY_3 (5 << RCC_CFGR_MCO1PRE)<br>
>+#define RCC_CFGR_MCO1PRE_BY_4 (6 << RCC_CFGR_MCO1PRE)<br>
>+#define RCC_CFGR_MCO1PRE_BY_5 (7 << RCC_CFGR_MCO1PRE)<br>
>+<br>
>+#define RCC_CFGR_MCO2PRE 27<br>
>+#define RCC_CFGR_MCO2PRE_BY_1 0<br>
>+#define RCC_CFGR_MCO2PRE_BY_2 (4 << RCC_CFGR_MCO2PRE)<br>
>+#define RCC_CFGR_MCO2PRE_BY_3 (5 << RCC_CFGR_MCO2PRE)<br>
>+#define RCC_CFGR_MCO2PRE_BY_4 (6 << RCC_CFGR_MCO2PRE)<br>
>+#define RCC_CFGR_MCO2PRE_BY_5 (7 << RCC_CFGR_MCO2PRE)<br>
>+<br>
>+#define RCC_CFGR_MCO2 30<br>
>+#define RCC_CFGR_MCO2_SYSCLK 0<br>
>+#define RCC_CFGR_MCO2_PLLI2S (1 << RCC_CFGR_MCO2)<br>
>+#define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2)<br>
>+#define RCC_CFGR_MCO2_PLL (3 << RCC_CFGR_MCO2)<br>
>+<br>
>+<br>
> #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */<br>
>diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c<br>
>b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c<br>
>index d337d3a..31823d1 100644<br>
>--- a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c<br>
>+++ b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c<br>
>@@ -17,9 +17,220 @@<br>
> #include <bsp/irq.h><br>
> #include <bsp/bootcard.h><br>
> #include <bsp/irq-generic.h><br>
>+#include <bsp/stm32f4.h><br>
>+#include <bsp/stm32f4xxxx_rcc.h><br>
>+#include <bsp/stm32f4xxxx_flash.h><br>
>+<br>
>+static rtems_status_code set_system_clk(uint32_t sysclk, uint32_t<br>
>hseclk, uint32_t hseflag);<br>
>+<br>
>+static void init_main_osc(void)<br>
>+{<br>
>+ volatile stm32f4_rcc *rcc = STM32F4_RCC;<br>
>+<br>
>+ /* Revert to reset values */<br>
>+ rcc->cr |= RCC_CR_HSION; /* turn on HSI */<br>
>+ while (! (rcc->cr & RCC_CR_HSIRDY) );<br>
>+<br>
>+ rcc->cfgr &= 0x00000300; /* all prescalers to 0, clock source to HSI<br>
>*/<br>
>+<br>
>+ rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI<br>
>*/<br>
>+<br>
>+ set_system_clk(STM32F4_SYSCLK / 1000000L, STM32F4_HSE_OSCILLATOR /<br>
>1000000L, 1);<br>
>+}<br>
>+<br>
>+<br>
>+/*<br>
>+ * Sets up clocks configuration to achieve desired system clock<br>
>+ * as close as possible with simple math<br>
>+ */<br>
>+static rtems_status_code set_system_clk(uint32_t sysclk, uint32_t<br>
>hseclk, uint32_t hseflag)<br>
>+{<br>
>+ volatile stm32f4_rcc *rcc = STM32F4_RCC;<br>
>+ volatile stm32f4_flash *flash = STM32F4_FLASH;<br>
>+ rtems_interrupt_level level;<br>
>+ long timeout = 0;<br>
>+ const long timeoutset = 10000000L;<br>
>+<br>
>+ int srcclk = 0;<br>
>+<br>
>+ int pll_m = 0;<br>
>+ int pll_n = 0;<br>
>+ int pll_p = 0;<br>
>+ int pll_q = 0;<br>
>+ //int cr;<br>
<br>
</div></div>No C++ style comments and no commented out code without good reason.<br>
<div><div class="h5"><br>
>+ int ahbpre = 0;<br>
>+ int apbpre1 = 0;<br>
>+ int apbpre2 = 0;<br>
>+<br>
>+ if (sysclk == 16) {<br>
>+ /* Revert to reset values */<br>
>+ rcc->cr |= 0x00000001; /* turn on HSI */<br>
>+ while (! (rcc->cr & (1 << RCC_CR_HSIRDY)) );<br>
>+<br>
>+ rcc->cfgr &= 0x00000300; /* all prescalers to 0, clock source to<br>
>HSI */<br>
>+<br>
>+ rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI<br>
>*/<br>
>+<br>
>+ flash->acr = 0; /* slow clock so no cache, no prefetch, no latency<br>
>*/<br>
>+<br>
>+ return RTEMS_SUCCESSFUL;<br>
>+ }<br>
>+<br>
>+ if (hseclk == 0 || hseflag == 0) {<br>
>+ srcclk = 16;<br>
>+ hseflag = 0;<br>
>+ }<br>
>+ else {<br>
>+ srcclk = hseclk;<br>
>+ }<br>
>+<br>
>+ if (sysclk > 180) {<br>
>+ return RTEMS_INVALID_NUMBER;<br>
>+ }<br>
>+ else if (sysclk > 96) {<br>
>+ pll_n = sysclk; /* multpily by the desired speed in MHz */<br>
>+ pll_p = 0; /* divide by 2 */<br>
>+ }<br>
>+ else if (sysclk > 48) {<br>
>+ pll_n = sysclk >> 1; /* multpily by 2x the desired speed in MHz */<br>
>+ pll_p = 1; /* divide by 4 */<br>
>+ }<br>
>+ else if (sysclk > 24) {<br>
>+ pll_n = sysclk >> 2; /* multpily by 4x the desired speed in MHz */<br>
>+ pll_p = 3; /* divide by 8 */<br>
>+ }<br>
>+ else {<br>
>+ return RTEMS_INVALID_NUMBER;<br>
>+ }<br>
>+<br>
>+ /*<br>
>+ * Lets use 1MHz input for PLL so we get higher VCO output<br>
>+ * this way we get better value for the PLL_Q divader for the USB<br>
>+ *<br>
>+ * Though you might want to use 2MHz as per CPU specification:<br>
>+ *<br>
>+ * Caution:The software has to set these bits correctly to ensure<br>
>+ * that the VCO input frequency ranges from 1 to 2 MHz.<br>
>+ * It is recommended to select a frequency of 2 MHz to limit PLL<br>
>jitter.<br>
>+ */<br>
>+ pll_m = srcclk; /* divide by the oscilator speed in MHz */<br>
>+ pll_n <<= 1; /* multiply by requested clock x2 */<br>
>+<br>
>+ /* pll_q is a prescaler from VCO for the USB OTG FS, SDIO and RNG,<br>
>+ * should result in the 48MHz for the USB<br>
>+ */<br>
>+ pll_q = ((long)(srcclk * pll_n + srcclk * pll_n / 2)) / pll_m / 48;<br>
>+<br>
>+ if (pll_q < 2)<br>
>+ {<br>
>+ pll_q = 2;<br>
>+ }<br>
>+<br>
<br>
<br>
</div></div>Pull the { up.<br>
<div><div class="h5"><br>
>+ /* APB1 prescaler, APB1 clock must be < 42MHz */<br>
>+ apbpre1 = (sysclk * 100) / 42;<br>
>+ if (apbpre1 <= 100) {<br>
>+ apbpre1 = RCC_CFGR_PPRE1_BY_1;<br>
>+ }<br>
>+ else if (apbpre1 <= 200) {<br>
>+ apbpre1 = RCC_CFGR_PPRE1_BY_2;<br>
>+ }<br>
>+ else if (apbpre1 <= 400) {<br>
>+ apbpre1 = RCC_CFGR_PPRE1_BY_4;<br>
>+ }<br>
>+ else if (apbpre1 <= 800) {<br>
>+ apbpre1 = RCC_CFGR_PPRE1_BY_8;<br>
>+ }<br>
>+ else if (apbpre1) {<br>
>+ apbpre1 = RCC_CFGR_PPRE1_BY_16;<br>
>+ }<br>
>+<br>
>+ /* APB2 prescaler, APB2 clock must be < 84MHz */<br>
>+ apbpre2 = (sysclk * 100) / 84;<br>
>+ if (apbpre2 <= 100) {<br>
>+ apbpre2 = RCC_CFGR_PPRE2_BY_1;<br>
>+ }<br>
>+ else if (apbpre2 <= 200) {<br>
>+ apbpre2 = RCC_CFGR_PPRE2_BY_2;<br>
>+ }<br>
>+ else if (apbpre2 <= 400) {<br>
>+ apbpre2 = RCC_CFGR_PPRE2_BY_4;<br>
>+ }<br>
>+ else if (apbpre2 <= 800) {<br>
>+ apbpre2 = RCC_CFGR_PPRE2_BY_8;<br>
>+ }<br>
>+ else {<br>
>+ apbpre2 = RCC_CFGR_PPRE2_BY_16;<br>
>+ }<br>
>+<br>
<br>
</div></div>I thought RTEMS style had } else and } else if. Is that right?<br>
<br>
If so adjust style.<br>
<div><div class="h5"><br>
>+ rtems_interrupt_disable(level);<br>
>+<br>
>+ rcc->cr |= RCC_CR_HSION; /* turn on HSI */<br>
>+ timeout = timeoutset;<br>
>+ while ((! (rcc->cr & RCC_CR_HSIRDY) ) && timeout--);<br>
>+<br>
>+ if (timeout == 0) while(1);<br>
>+<br>
>+ /* all prescalers to 0, clock source to HSI */<br>
>+ rcc->cfgr &= 0x00000300;<br>
>+ rcc->cfgr |= RCC_CFGR_SW_HSI;<br>
>+<br>
>+ timeout = timeoutset;<br>
>+ while ( ( (rcc->cfgr & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI ) &&<br>
>--timeout );<br>
>+<br>
>+ if (timeout == 0) while(1);<br>
>+<br>
>+ /* turn off PLL */<br>
>+ rcc->cr &= ~ (RCC_CR_PLLON | RCC_CR_PLLRDY);<br>
>+<br>
>+ if (hseflag) {<br>
>+ rcc->cr |= RCC_CR_HSEON;<br>
>+ timeout = timeoutset;<br>
>+ while ((! (rcc->cr & RCC_CR_HSERDY) ) && timeout--);<br>
>+ }<br>
>+<br>
>+ rcc->pllcfgr &= 0xF0BC8000; /* clear PLL prescalers */<br>
>+<br>
>+ /* set pll parameters */<br>
>+ rcc->pllcfgr |=(pll_m << RCC_PLLCFGR_PLLM) // input divider<br>
>+ | (pll_n << RCC_PLLCFGR_PLLN) // multiplier<br>
>+ | (pll_p << RCC_PLLCFGR_PLLP) // output divider from<br>
>table<br>
>+ // HSE v HSI<br>
>+ | (hseflag ? RCC_PLLCFGR_PLLSRC_HSE :<br>
>RCC_PLLCFGR_PLLSRC_HSI)<br>
>+ | (pll_q << RCC_PLLCFGR_PLLQ); // PLLQ<br>
>+<br>
>+ /* set prescalers for the internal busses */<br>
>+ rcc->cfgr |= apbpre1<br>
>+ | apbpre2<br>
>+ | ahbpre;<br>
>+<br>
>+ /* set flash parameters, hard coded for now for fast system clocks<br>
>*/<br>
>+ flash->acr |= 5 // latency<br>
>+ | (1 << 9) // instruction cache<br>
>+ | (1 << 10);// data cache<br>
>+<br>
>+ /* turn on PLL */<br>
>+ rcc->cr |= RCC_CR_PLLON;<br>
>+ timeout = timeoutset;<br>
>+ while ( (! (rcc->cr & RCC_CR_PLLRDY) ) && --timeout );<br>
>+<br>
>+ if (timeout == 0) while(1);<br>
>+<br>
>+ /* clock source to PLL */<br>
>+ rcc->cfgr = (rcc->cfgr & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_PLL;<br>
>+ timeout = timeoutset;<br>
>+ while ( ((rcc->cfgr & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) &&<br>
>--timeout );<br>
>+ //if (timeout == 0) while(1);<br>
>+<br>
>+ rtems_interrupt_enable(level);<br>
>+<br>
>+ return RTEMS_SUCCESSFUL;<br>
>+}<br>
>+<br>
><br>
> void bsp_start(void)<br>
> {<br>
>+ init_main_osc();<br>
>+<br>
> stm32f4_gpio_set_config_array(&stm32f4_start_config_gpio [0]);<br>
><br>
> bsp_interrupt_initialize();<br>
>--<br>
>2.1.0<br>
><br>
</div></div>>_______________________________________________<br>
>devel mailing list<br>
><a href="mailto:devel@rtems.org">devel@rtems.org</a><br>
><a href="http://lists.rtems.org/mailman/listinfo/devel" target="_blank">http://lists.rtems.org/mailman/listinfo/devel</a><br>
<br>
</blockquote></div><br></div>