<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">2014-09-21 20:07 GMT+02:00 <span dir="ltr"><<a href="mailto:tomasz.gregorek@gmail.com" target="_blank">tomasz.gregorek@gmail.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">From: Tomasz Gregorek <<a href="mailto:tomasz.gregorek@gmail.com">tomasz.gregorek@gmail.com</a>><br>
<br>
Added simple math to caclulate register values for the PLL<br>
and for the prescalers. It will try to keep 48MHz for the USB OTG FS.<br>
Also it will set latency on the Flash memory for the high speeds.<br>
<br>
Limitations:<br>
It is assumed that 1MHz resolution is enough.<br>
Best fits for the clocks are achieved with multiplies of 42MHz.<br>
Even though APB1, APB2 and AHB are calculated user is still required<br>
to provide correct values for the bsp configuration for the:<br>
STM32F4_PCLK1<br>
STM32F4_PCLK2<br>
STM32F4_HCLK (= system clock)<br>
as those are used for the peripheral clocking calculations.<br>
---<br>
c/src/lib/libbsp/arm/stm32f4/Makefile.am | 1 +<br>
c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 +<br>
.../libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h | 54 ++++<br>
.../libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h | 150 +++++++++--<br>
c/src/lib/libbsp/arm/stm32f4/<a href="http://preinstall.am" target="_blank">preinstall.am</a> | 4 +<br>
c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c | 280 ++++++++++++++++++++-<br>
6 files changed, 475 insertions(+), 24 deletions(-)<br>
create mode 100644 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h<br>
<br>
diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am b/c/src/lib/libbsp/arm/stm32f4/Makefile.am<br>
index 027fcad..055a0b1 100644<br>
--- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am<br>
+++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am<br>
@@ -51,6 +51,7 @@ include_bsp_HEADERS += include/stm32f10xxx_rcc.h<br>
include_bsp_HEADERS += include/stm32f10xxx_exti.h<br>
include_bsp_HEADERS += include/stm32f4xxxx_gpio.h<br>
include_bsp_HEADERS += include/stm32f4xxxx_rcc.h<br>
+include_bsp_HEADERS += include/stm32f4xxxx_flash.h<br>
include_bsp_HEADERS += include/stm32_i2c.h<br>
include_bsp_HEADERS += include/i2c.h<br>
include_bsp_HEADERS += include/stm32_usart.h<br>
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h<br>
index 59d13ef..d26f914 100644<br>
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h<br>
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h<br>
@@ -55,6 +55,16 @@<br>
<br>
/** @} */<br>
<br>
+/**<br>
+ * @name STM32F4XXXX FLASH<br>
+ * @{<br>
+ */<br>
+<br>
+#include <bsp/stm32f4xxxx_flash.h><br>
+#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE + 0x40023C00))<br>
+<br>
+/** @} */<br>
+<br>
#include <bsp/stm32_i2c.h><br>
<br>
/**<br>
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h<br>
new file mode 100644<br>
index 0000000..55d9dc6<br>
--- /dev/null<br>
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h<br>
@@ -0,0 +1,54 @@<br>
+/**<br>
+ * @file<br>
+ *<br>
+ * @ingroup stm32f4_flash<br>
+ *<br>
+ * @brief STM32F4XXXX FLASH support.<br>
+ *<br>
+ * Contains structure desribing registers responsible for the flash memory<br>
+ * configuration.<br>
+ */<br>
+<br>
+/*<br>
+ * Copyright (c) 2014 Tomasz Gregorek. All rights reserved.<br>
+ *<br>
+ * <<a href="mailto:tomasz.gregorek@gmail.com">tomasz.gregorek@gmail.com</a>><br>
+ *<br>
+ * The license and distribution terms for this file may be<br>
+ * found in the file LICENSE in this distribution or at<br>
+ * <a href="http://www.rtems.org/license/LICENSE" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
+ */<br>
+<br>
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H<br>
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H<br>
+<br>
+#include <bsp/utility.h><br>
+<br>
+/**<br>
+ * @defgroup stm32f10xxx_flash STM32F4XXXX FLASH Support<br>
+ * @ingroup stm32f4_flash<br>
+ * @brief STM32F4FXXX FLASH Support<br>
+ * @{<br>
+ */<br>
+<br>
+typedef struct {<br>
+ uint32_t acr;<br>
+ uint32_t keyr;<br>
+ uint32_t optkeyr;<br>
+ uint32_t sr;<br>
+ uint32_t cr;<br>
+ uint32_t optcr;<br>
+ uint32_t optcr1;<br>
+} stm32f4_flash;<br>
+<br>
+/** @} */<br>
+<br>
+#define FLASH_ACR_LATENCY( val ) BSP_FLD32( val, 0, 3 )<br>
+#define FLASH_ACR_LATENCY_MSK BSP_MSK32( 0, 3 )<br>
+#define FLASH_ACR_PRFTEN BSP_BIT32( 8 )<br>
+#define FLASH_ACR_ICEN BSP_BIT32( 9 )<br>
+#define FLASH_ACR_DCEN BSP_BIT32( 10 )<br>
+#define FLASH_ACR_ICRST BSP_BIT32( 11 )<br>
+#define FLASH_ACR_DCRST BSP_BIT32( 12 )<br>
+<br>
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */<br>
\ No newline at end of file<br>
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h<br>
index 8126340..311e484 100644<br>
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h<br>
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h<br>
@@ -31,29 +31,135 @@<br>
*/<br>
<br>
typedef struct {<br>
- uint32_t cr;<br>
- uint32_t pllcfgr;<br>
- uint32_t cfgr;<br>
- uint32_t cir;<br>
- uint32_t ahbrstr [3];<br>
- uint32_t reserved_1c;<br>
- uint32_t apbrstr [2];<br>
- uint32_t reserved_28 [2];<br>
- uint32_t ahbenr [3];<br>
- uint32_t reserved_3c;<br>
- uint32_t apbenr [2];<br>
- uint32_t reserved_48 [2];<br>
- uint32_t ahblpenr [3];<br>
- uint32_t reserved_5c;<br>
- uint32_t apblpenr [2];<br>
- uint32_t reserved_68 [2];<br>
- uint32_t bdcr;<br>
- uint32_t csr;<br>
- uint32_t reserved_78 [2];<br>
- uint32_t sscgr;<br>
- uint32_t plli2scfgr;<br>
+ uint32_t cr;<br>
+ uint32_t pllcfgr;<br>
+ uint32_t cfgr;<br>
+ uint32_t cir;<br>
+ uint32_t ahbrstr[ 3 ];<br>
+ uint32_t reserved_1c;<br>
+ uint32_t apbrstr[ 2 ];<br>
+ uint32_t reserved_28[ 2 ];<br>
+ uint32_t ahbenr[ 3 ];<br>
+ uint32_t reserved_3c;<br>
+ uint32_t apbenr[ 2 ];<br>
+ uint32_t reserved_48[ 2 ];<br>
+ uint32_t ahblpenr[ 3 ];<br>
+ uint32_t reserved_5c;<br>
+ uint32_t apblpenr[ 2 ];<br>
+ uint32_t reserved_68[ 2 ];<br>
+ uint32_t bdcr;<br>
+ uint32_t csr;<br>
+ uint32_t reserved_78[ 2 ];<br>
+ uint32_t sscgr;<br>
+ uint32_t plli2scfgr;<br>
} stm32f4_rcc;<br>
<br>
/** @} */<br>
<br>
-#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */<br>
+#define RCC_CR_HSION BSP_BIT32( 0 )<br>
+#define RCC_CR_HSIRDY BSP_BIT32( 1 )<br>
+#define RCC_CR_HSITRIM( val ) BSP_FLD32( val, 3, 7 )<br>
+#define RCC_CR_HSITRIM_MSK BSP_MSK32( 3, 7 )<br>
+#define RCC_CR_HSICAL( val ) BSP_FLD32( val, 8, 15 )<br>
+#define RCC_CR_HSICAL_MSK BSP_MSK32( 8, 15 )<br>
+#define RCC_CR_HSEON BSP_BIT32( 16 )<br>
+#define RCC_CR_HSERDY BSP_BIT32( 17 )<br>
+#define RCC_CR_HSEBYP BSP_BIT32( 18 )<br>
+#define RCC_CR_CSSON BSP_BIT32( 19 )<br>
+#define RCC_CR_PLLON BSP_BIT32( 24 )<br>
+#define RCC_CR_PLLRDY BSP_BIT32( 25 )<br>
+#define RCC_CR_PLLI2SON BSP_BIT32( 26 )<br>
+#define RCC_CR_PLLI2SRDY BSP_BIT32( 27 )<br>
+<br>
+#define RCC_PLLCFGR_PLLM( val ) BSP_FLD32( val, 0, 5 )<br>
+#define RCC_PLLCFGR_PLLM_MSK BSP_MSK32( 0, 5 )<br>
+#define RCC_PLLCFGR_PLLN( val ) BSP_FLD32( val, 6, 14 )<br>
+#define RCC_PLLCFGR_PLLN_MSK BSP_MSK32( 6, 14 )<br>
+<br>
+#define RCC_PLLCFGR_PLLP 16<br>
+#define RCC_PLLCFGR_PLLP_MSK BSP_MSK32( 16, 17 )<br>
+#define RCC_PLLCFGR_PLLP_BY_2 0<br>
+#define RCC_PLLCFGR_PLLP_BY_4 BSP_FLD32( 1, 16, 17 )<br>
+#define RCC_PLLCFGR_PLLP_BY_6 BSP_FLD32( 2, 16, 17 )<br>
+#define RCC_PLLCFGR_PLLP_BY_8 BSP_FLD32( 3, 16, 17 )<br>
+<br>
+#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32( 22 )<br>
+#define RCC_PLLCFGR_PLLSRC_HSI 0<br>
+<br>
+#define RCC_PLLCFGR_PLLQ( val ) BSP_FLD32( val, 24, 27 )<br>
+#define RCC_PLLCFGR_PLLQ_MSK BSP_MSK32( 24, 27 )<br>
+<br>
+#define RCC_CFGR_SW 0<br>
+#define RCC_CFGR_SW_MSK BSP_MSK32( 0, 1 )<br>
+#define RCC_CFGR_SW_HSI 0<br>
+#define RCC_CFGR_SW_HSE 1<br>
+#define RCC_CFGR_SW_PLL 2<br>
+<br>
+#define RCC_CFGR_SWS 2<br>
+#define RCC_CFGR_SWS_MSK BSP_MSK32( 2, 3 )<br>
+#define RCC_CFGR_SWS_HSI 0<br>
+#define RCC_CFGR_SWS_HSE BSP_FLD32( 1, 2, 3 )<br>
+#define RCC_CFGR_SWS_PLL BSP_FLD32( 2, 2, 3 )<br>
+<br>
+#define RCC_CFGR_HPRE 4<br>
+#define RCC_CFGR_HPRE_BY_1 0<br>
+#define RCC_CFGR_HPRE_BY_2 BSP_FLD32( 8, 4, 7 )<br>
+#define RCC_CFGR_HPRE_BY_4 BSP_FLD32( 9, 4, 7 )<br>
+#define RCC_CFGR_HPRE_BY_8 BSP_FLD32( 10, 4, 7 )<br>
+#define RCC_CFGR_HPRE_BY_16 BSP_FLD32( 11, 4, 7 )<br>
+#define RCC_CFGR_HPRE_BY_64 BSP_FLD32( 12, 4, 7 )<br>
+#define RCC_CFGR_HPRE_BY_128 BSP_FLD32( 13, 4, 7 )<br>
+#define RCC_CFGR_HPRE_BY_256 BSP_FLD32( 14, 4, 7 )<br>
+#define RCC_CFGR_HPRE_BY_512 BSP_FLD32( 15, 4, 7 )<br>
+<br>
+#define RCC_CFGR_PPRE1 10<br>
+#define RCC_CFGR_PPRE1_BY_1 0<br>
+#define RCC_CFGR_PPRE1_BY_2 BSP_FLD32( 4, 10, 12 )<br>
+#define RCC_CFGR_PPRE1_BY_4 BSP_FLD32( 5, 10, 12 )<br>
+#define RCC_CFGR_PPRE1_BY_8 BSP_FLD32( 6, 10, 12 )<br>
+#define RCC_CFGR_PPRE1_BY_16 BSP_FLD32( 7, 10, 12 )<br>
+<br>
+#define RCC_CFGR_PPRE2 13<br>
+#define RCC_CFGR_PPRE2 BSP_MSK32( 13, 15 )<br>
+#define RCC_CFGR_PPRE2_BY_1 0<br>
+#define RCC_CFGR_PPRE2_BY_2 BSP_FLD32( 4, 13, 15 )<br>
+#define RCC_CFGR_PPRE2_BY_4 BSP_FLD32( 5, 13, 15 )<br>
+#define RCC_CFGR_PPRE2_BY_8 BSP_FLD32( 6, 13, 15 )<br>
+#define RCC_CFGR_PPRE2_BY_16 BSP_FLD32( 7, 13, 15 )<br>
+<br>
+#define RCC_CFGR_RTCPRE( val ) BSP_FLD32( val, 16, 20 )<br>
+#define RCC_CFGR_RTCPRE_MSK BSP_MSK32( 16, 20 )<br>
+<br>
+#define RCC_CFGR_MCO1 21<br>
+#define RCC_CFGR_MCO1_MSK BSP_MSK32( 21, 22 )<br>
+#define RCC_CFGR_MCO1_HSI 0<br>
+#define RCC_CFGR_MCO1_LSE BSP_FLD32( 1, 21, 22 )<br>
+#define RCC_CFGR_MCO1_HSE BSP_FLD32( 2, 21, 22 )<br>
+#define RCC_CFGR_MCO1_PLL BSP_FLD32( 3, 21, 22 )<br>
+<br>
+#define RCC_CFGR_I2SSRC BSP_BIT32( 23 )<br>
+<br>
+#define RCC_CFGR_MCO1PRE 24<br>
+#define RCC_CFGR_MCO1PRE_MSK BSP_MSK32( 24, 26 )<br>
+#define RCC_CFGR_MCO1PRE_BY_1 0<br>
+#define RCC_CFGR_MCO1PRE_BY_2 BSP_FLD32( 4, 24, 26 )<br>
+#define RCC_CFGR_MCO1PRE_BY_3 BSP_FLD32( 5, 24, 26 )<br>
+#define RCC_CFGR_MCO1PRE_BY_4 BSP_FLD32( 6, 24, 26 )<br>
+#define RCC_CFGR_MCO1PRE_BY_5 BSP_FLD32( 7, 24, 26 )<br>
+<br>
+#define RCC_CFGR_MCO2PRE 27<br>
+#define RCC_CFGR_MCO2PRE_MSK BSP_MSK32( 27, 29 )<br>
+#define RCC_CFGR_MCO2PRE_BY_1 0<br>
+#define RCC_CFGR_MCO2PRE_BY_2 BSP_FLD32( 4, 27, 29 )<br>
+#define RCC_CFGR_MCO2PRE_BY_3 BSP_FLD32( 5, 27, 29 )<br>
+#define RCC_CFGR_MCO2PRE_BY_4 BSP_FLD32( 6, 27, 29 )<br>
+#define RCC_CFGR_MCO2PRE_BY_5 BSP_FLD32( 7, 27, 29 )<br>
+<br>
+#define RCC_CFGR_MCO2 30<br>
+#define RCC_CFGR_MCO2_MSK BSP_MSK32( 30, 31 )<br>
+#define RCC_CFGR_MCO2_SYSCLK 0<br>
+#define RCC_CFGR_MCO2_PLLI2S BSP_FLD32( 1, 30, 31 )<br>
+#define RCC_CFGR_MCO2_HSE BSP_FLD32( 2, 30, 31 )<br>
+#define RCC_CFGR_MCO2_PLL BSP_FLD32( 3, 30, 31 )<br>
+<br>
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */<br>
\ No newline at end of file<br>
diff --git a/c/src/lib/libbsp/arm/stm32f4/<a href="http://preinstall.am" target="_blank">preinstall.am</a> b/c/src/lib/libbsp/arm/stm32f4/<a href="http://preinstall.am" target="_blank">preinstall.am</a><br>
index fd1604d..fe9a3b0 100644<br>
--- a/c/src/lib/libbsp/arm/stm32f4/<a href="http://preinstall.am" target="_blank">preinstall.am</a><br>
+++ b/c/src/lib/libbsp/arm/stm32f4/<a href="http://preinstall.am" target="_blank">preinstall.am</a><br>
@@ -121,6 +121,10 @@ $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h: include/stm32f4xxxx_rcc.h $(PROJECT_IN<br>
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h<br>
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h<br>
<br>
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h: include/stm32f4xxxx_flash.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)<br>
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h<br>
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h<br>
+<br>
$(PROJECT_INCLUDE)/bsp/stm32_i2c.h: include/stm32_i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)<br>
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32_i2c.h<br>
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32_i2c.h<br>
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c<br>
index d337d3a..0d08458 100644<br>
--- a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c<br>
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c<br>
@@ -17,10 +17,286 @@<br>
#include <bsp/irq.h><br>
#include <bsp/bootcard.h><br>
#include <bsp/irq-generic.h><br>
+#include <assert.h><br>
+#include <bsp/stm32f4.h><br>
<br>
-void bsp_start(void)<br>
+#ifdef STM32F4_FAMILY_F4XXXX<br>
+<br>
+#include <bsp/stm32f4xxxx_rcc.h><br>
+#include <bsp/stm32f4xxxx_flash.h><br>
+<br>
+static rtems_status_code set_system_clk(<br>
+ uint32_t sys_clk,<br>
+ uint32_t hse_clk,<br>
+ uint32_t hse_flag<br>
+);<br>
+<br>
+static void init_main_osc( void )<br>
+{<br>
+ volatile stm32f4_rcc *rcc = STM32F4_RCC;<br>
+ rtems_status_code status;<br>
+<br>
+ /* Revert to reset values */<br>
+ rcc->cr |= RCC_CR_HSION; /* turn on HSI */<br>
+<br>
+ while ( !( rcc->cr & RCC_CR_HSIRDY ) ) ;<br>
+<br>
+ rcc->cfgr &= 0x00000300; /* all prescalers to 0, clock source to HSI */<br>
+<br>
+ rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI */<br>
+<br>
+ status = set_system_clk( STM32F4_SYSCLK / 1000000L,<br>
+ STM32F4_HSE_OSCILLATOR / 1000000L,<br>
+ 1 );<br>
+<br>
+ assert( rtems_is_status_successful( status ) );<br>
+}<br>
+<br>
+/**<br>
+ * @brief Sets up clocks configuration.<br>
+ *<br>
+ * Set up clocks configuration to achieve desired system clock<br>
+ * as close as possible with simple math.<br>
+ *<br>
+ * Limitations:<br>
+ * It is assumed that 1MHz resolution is enough.<br>
+ * Best fits for the clocks are achieved with multiplies of 42MHz.<br>
+ * Even though APB1, APB2 and AHB are calculated user is still required<br>
+ * to provide correct values for the bsp configuration for the:<br>
+ * STM32F4_PCLK1<br>
+ * STM32F4_PCLK2<br>
+ * STM32F4_HCLK<br>
+ * as those are used for the peripheral clocking calculations.<br>
+ *<br>
+ * @param sys_clk Desired system clock in MHz.<br>
+ * @param hse_clk External clock speed in MHz.<br>
+ * @param hse_flag Flag determining which clock source to use, 1 for HSE,<br>
+ * 0 for HSI.<br>
+ *<br>
+ * @retval RTEMS_SUCCESSFUL Configuration has been succesfully aplied for the<br>
+ * requested clock speed.<br>
+ * @retval RTEMS_TIMEOUT HSE clock didn't start or PLL didn't lock.<br>
+ * @retval RTEMS_INVALID_NUMBER Requested clock speed is out of range.<br>
+ */<br>
+static rtems_status_code set_system_clk(<br>
+ uint32_t sys_clk,<br>
+ uint32_t hse_clk,<br>
+ uint32_t hse_flag<br>
+)<br>
+{<br>
+ volatile stm32f4_rcc *rcc = STM32F4_RCC;<br>
+ volatile stm32f4_flash *flash = STM32F4_FLASH;<br>
+ long timeout = 0;<br>
+<br>
+ int src_clk = 0;<br>
+<br>
+ uint32_t pll_m = 0;<br>
+ uint32_t pll_n = 0;<br>
+ uint32_t pll_p = 0;<br>
+ uint32_t pll_q = 0;<br>
+<br>
+ uint32_t ahbpre = 0;<br>
+ uint32_t apbpre1 = 0;<br>
+ uint32_t apbpre2 = 0;<br>
+<br>
+ if ( sys_clk == 16 && hse_clk != 16 ) {<br>
+ /* Revert to reset values */<br>
+ rcc->cr |= RCC_CR_HSION; /* turn on HSI */<br>
+<br>
+ while ( !( rcc->cr & RCC_CR_HSIRDY ) ) ;<br>
+<br>
+ /* all prescalers to 0, clock source to HSI */<br>
+ rcc->cfgr &= 0x00000300 | RCC_CFGR_SW_HSI;<br>
+ rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI */<br>
+ flash->acr = 0; /* slow clock so no cache, no prefetch, no latency */<br>
+<br>
+ return RTEMS_SUCCESSFUL;<br>
+ }<br>
+<br>
+ if ( sys_clk == hse_clk ) {<br>
+ /* Revert to reset values */<br>
+ rcc->cr |= RCC_CR_HSEON; /* turn on HSE */<br>
+ timeout = 400;<br>
+<br>
+ while ( !( rcc->cr & RCC_CR_HSERDY ) && --timeout ) ;<br>
+<br>
+ assert( timeout != 0 );<br>
+<br>
+ if ( timeout == 0 ) {<br>
+ return RTEMS_TIMEOUT;<br>
+ }<br>
+<br>
+ /* all prescalers to 0, clock source to HSE */<br>
+ rcc->cfgr &= 0x00000300;<br>
+ rcc->cfgr |= RCC_CFGR_SW_HSE;<br>
+ /* turn off all clocks and PLL except HSE */<br>
+ rcc->cr &= 0xF0F0FFFC | RCC_CR_HSEON;<br>
+ flash->acr = 0; /* slow clock so no cache, no prefetch, no latency */<br>
+<br>
+ return RTEMS_SUCCESSFUL;<br>
+ }<br>
+<br>
+ /*<br>
+ * Lets use 1MHz input for PLL so we get higher VCO output<br>
+ * this way we get better value for the PLL_Q divader for the USB<br>
+ *<br>
+ * Though you might want to use 2MHz as per CPU specification:<br>
+ *<br>
+ * Caution:The software has to set these bits correctly to ensure<br>
+ * that the VCO input frequency ranges from 1 to 2 MHz.<br>
+ * It is recommended to select a frequency of 2 MHz to limit PLL jitter.<br>
+ */<br>
+<br>
+ if ( sys_clk > 180 ) {<br>
+ return RTEMS_INVALID_NUMBER;<br>
+ } else if ( sys_clk >= 96 ) {<br>
+ pll_n = sys_clk << 1;<br>
+ pll_p = RCC_PLLCFGR_PLLP_BY_2;<br>
+ } else if ( sys_clk >= 48 ) {<br>
+ pll_n = sys_clk << 2;<br>
+ pll_p = RCC_PLLCFGR_PLLP_BY_4;<br>
+ } else if ( sys_clk >= 24 ) {<br>
+ pll_n = sys_clk << 3;<br>
+ pll_p = RCC_PLLCFGR_PLLP_BY_8;<br>
+ } else {<br>
+ return RTEMS_INVALID_NUMBER;<br>
+ }<br>
+<br>
+ if ( hse_clk == 0 || hse_flag == 0 ) {<br>
+ src_clk = 16;<br>
+ hse_flag = 0;<br>
+ } else {<br>
+ src_clk = hse_clk;<br>
+ }<br>
+<br>
+ pll_m = src_clk; /* divide by the oscilator speed in MHz */<br>
+<br>
+ /* pll_q is a prescaler from VCO for the USB OTG FS, SDIO and RNG,<br>
+ * best if results in the 48MHz for the USB<br>
+ */<br>
+ pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) ) / pll_m / 48;<br>
+<br>
+ if ( pll_q < 2 ) {<br>
+ pll_q = 2;<br>
+ }<br>
+<br>
+ /* APB1 prescaler, APB1 clock must be < 42MHz */<br>
+ apbpre1 = ( sys_clk * 100 ) / 42;<br>
+<br>
+ if ( apbpre1 <= 100 ) {<br>
+ apbpre1 = RCC_CFGR_PPRE1_BY_1;<br>
+ } else if ( apbpre1 <= 200 ) {<br>
+ apbpre1 = RCC_CFGR_PPRE1_BY_2;<br>
+ } else if ( apbpre1 <= 400 ) {<br>
+ apbpre1 = RCC_CFGR_PPRE1_BY_4;<br>
+ } else if ( apbpre1 <= 800 ) {<br>
+ apbpre1 = RCC_CFGR_PPRE1_BY_8;<br>
+ } else if ( apbpre1 ) {<br>
+ apbpre1 = RCC_CFGR_PPRE1_BY_16;<br>
+ }<br>
+<br>
+ /* APB2 prescaler, APB2 clock must be < 84MHz */<br>
+ apbpre2 = ( sys_clk * 100 ) / 84;<br>
+<br>
+ if ( apbpre2 <= 100 ) {<br>
+ apbpre2 = RCC_CFGR_PPRE2_BY_1;<br>
+ } else if ( apbpre2 <= 200 ) {<br>
+ apbpre2 = RCC_CFGR_PPRE2_BY_2;<br>
+ } else if ( apbpre2 <= 400 ) {<br>
+ apbpre2 = RCC_CFGR_PPRE2_BY_4;<br>
+ } else if ( apbpre2 <= 800 ) {<br>
+ apbpre2 = RCC_CFGR_PPRE2_BY_8;<br>
+ } else {<br>
+ apbpre2 = RCC_CFGR_PPRE2_BY_16;<br>
+ }<br>
+<br>
+ rcc->cr |= RCC_CR_HSION; /* turn on HSI */<br>
+<br>
+ while ( ( !( rcc->cr & RCC_CR_HSIRDY ) ) ) ;<br>
+<br>
+ /* all prescalers to 0, clock source to HSI */<br>
+ rcc->cfgr &= 0x00000300;<br>
+ rcc->cfgr |= RCC_CFGR_SW_HSI;<br>
+<br>
+ while ( ( ( rcc->cfgr & RCC_CFGR_SWS_MSK ) != RCC_CFGR_SWS_HSI ) ) ;<br>
+<br>
+ /* turn off PLL */<br>
+ rcc->cr &= ~( RCC_CR_PLLON | RCC_CR_PLLRDY );<br>
+<br>
+ /* turn on HSE */<br>
+ if ( hse_flag ) {<br>
+ rcc->cr |= RCC_CR_HSEON;<br>
+ timeout = 400;<br>
+<br>
+ while ( ( !( rcc->cr & RCC_CR_HSERDY ) ) && timeout-- ) ;<br>
+<br>
+ assert( timeout != 0 );<br>
+<br>
+ if ( timeout == 0 ) {<br>
+ return RTEMS_TIMEOUT;<br>
+ }<br>
+ }<br>
+<br>
+ rcc->pllcfgr &= 0xF0BC8000; /* clear PLL prescalers */<br>
+<br>
+ /* set pll parameters */<br>
+ rcc->pllcfgr |= RCC_PLLCFGR_PLLM( pll_m ) | /* input divider */<br>
+ RCC_PLLCFGR_PLLN( pll_n ) | /* multiplier */<br>
+ pll_p | /* output divider from table */<br>
+ /* HSE v HSI */<br>
+ ( hse_flag ? RCC_PLLCFGR_PLLSRC_HSE : RCC_PLLCFGR_PLLSRC_HSI )<br>
+ |<br>
+ RCC_PLLCFGR_PLLQ( pll_q ); /* PLLQ divider */<br>
+<br>
+ /* set prescalers for the internal busses */<br>
+ rcc->cfgr |= apbpre1 |<br>
+ apbpre2 |<br>
+ ahbpre;<br>
+<br>
+ /*<br>
+ * Set flash parameters, hard coded for now for fast system clocks.<br>
+ * TODO implement some math to use flash on as low latancy as possible<br>
+ */<br>
+ flash->acr = FLASH_ACR_LATENCY( 5 ) | /* latency */<br>
+ FLASH_ACR_ICEN | /* instruction cache */<br>
+ FLASH_ACR_DCEN; /* data cache */<br>
+<br>
+ /* turn on PLL */<br>
+ rcc->cr |= RCC_CR_PLLON;<br>
+ timeout = 40000;<br>
+<br>
+ while ( ( !( rcc->cr & RCC_CR_PLLRDY ) ) && --timeout ) ;<br>
+<br>
+ assert( timeout != 0 );<br>
+<br>
+ if ( timeout == 0 ) {<br>
+ return RTEMS_TIMEOUT;<br>
+ }<br>
+<br>
+ /* clock source to PLL */<br>
+ rcc->cfgr = ( rcc->cfgr & ~RCC_CFGR_SW_MSK ) | RCC_CFGR_SW_PLL;<br>
+<br>
+ while ( ( ( rcc->cfgr & RCC_CFGR_SWS_MSK ) != RCC_CFGR_SWS_PLL ) ) ;<br>
+<br>
+ return RTEMS_SUCCESSFUL;<br>
+}<br>
+<br>
+#endif /* STM32F4_FAMILY_F4XXXX */<br>
+<br>
+#ifdef STM32F4_FAMILY_F10XXX<br>
+<br>
+static void init_main_osc( void )<br>
+{<br>
+<br>
+}<br>
+<br>
+#endif /* STM32F4_FAMILY_F10XXX */<br>
+<br>
+void bsp_start( void )<br>
{<br>
- stm32f4_gpio_set_config_array(&stm32f4_start_config_gpio [0]);<br>
+ init_main_osc();<br>
+<br>
+ stm32f4_gpio_set_config_array( &stm32f4_start_config_gpio[ 0 ] );<br>
<br>
bsp_interrupt_initialize();<br>
}<br>
<span class=""><font color="#888888">--<br>
2.1.0<br>
<br>
</font></span></blockquote></div><br></div><div class="gmail_extra">Hi<div><br></div><div>Any chance for someone to take a look at this patch?</div><div><br></div><div>Cheers</div><div>Tomasz</div></div></div>