<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Oct 13, 2014 at 7:03 PM, Joel Sherrill <span dir="ltr"><<a href="mailto:joel.sherrill@oarcorp.com" target="_blank">joel.sherrill@oarcorp.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000">
<br>
<div>On 10/13/2014 11:45 AM, Hesham Moustafa
wrote:<br>
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<blockquote type="cite">
<div dir="ltr">Missed patch?</div>
<div class="gmail_extra"><br>
</div>
</blockquote>
Yep. Committed now. This should address a bunch of the or1ksim<br>
build warnings. I fixed another in console/uart.c for an unused<br>
variable.<br>
<br></div></blockquote><div>Thanks. There is another patch I submitted earlier that fixes some uart.c warnings, part of it this unused variable. I will reply to it. </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div bgcolor="#FFFFFF" text="#000000">
Starting another build of all BSPs to see if I fixed all
"-Wunused-variables"<br>
cases.<br>
<br>
Thanks.<div><div class="h5"><br>
<blockquote type="cite">
<div class="gmail_extra">
<div class="gmail_quote">On Fri, Oct 10, 2014 at 7:23 PM, Hesham
ALMatary <span dir="ltr"><<a href="mailto:heshamelmatary@gmail.com" target="_blank">heshamelmatary@gmail.com</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">---<br>
c/src/lib/libcpu/or1k/shared/cache/cache.c | 16
++++++++--------<br>
c/src/lib/libcpu/or1k/shared/cache/cache_.h | 1 +<br>
2 files changed, 9 insertions(+), 8 deletions(-)<br>
<br>
diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c
b/c/src/lib/libcpu/or1k/shared/cache/cache.c<br>
index 039be36..afc8859 100644<br>
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c<br>
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c<br>
@@ -71,7 +71,7 @@ static inline void
_CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)<br>
<br>
_ISR_Disable (level);<br>
<br>
- _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr);<br>
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr);<br>
<br>
_ISR_Enable(level);<br>
}<br>
@@ -81,7 +81,7 @@ static inline void
_CPU_OR1K_Cache_data_block_flush(const void *d_addr)<br>
ISR_Level level;<br>
_ISR_Disable (level);<br>
<br>
- _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr);<br>
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);<br>
<br>
_ISR_Enable(level);<br>
}<br>
@@ -91,7 +91,7 @@ static inline void
_CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)<br>
ISR_Level level;<br>
_ISR_Disable (level);<br>
<br>
- _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr);<br>
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);<br>
<br>
_ISR_Enable(level);<br>
}<br>
@@ -101,7 +101,7 @@ static inline void
_CPU_OR1K_Cache_data_block_writeback(const void *d_addr)<br>
ISR_Level level;<br>
_ISR_Disable (level);<br>
<br>
- _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr);<br>
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);<br>
<br>
_ISR_Enable(level);<br>
}<br>
@@ -111,7 +111,7 @@ static inline void
_CPU_OR1K_Cache_data_block_lock(const void *d_addr)<br>
ISR_Level level;<br>
_ISR_Disable (level);<br>
<br>
- _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr);<br>
+ _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);<br>
<br>
_ISR_Enable(level);<br>
}<br>
@@ -122,7 +122,7 @@ static inline void
_CPU_OR1K_Cache_instruction_block_prefetch<br>
ISR_Level level;<br>
_ISR_Disable (level);<br>
<br>
- _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr);<br>
+ _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);<br>
<br>
_ISR_Enable(level);<br>
}<br>
@@ -133,7 +133,7 @@ static inline void
_CPU_OR1K_Cache_instruction_block_invalidate<br>
ISR_Level level;<br>
_ISR_Disable (level);<br>
<br>
- _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr);<br>
+ _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);<br>
<br>
_ISR_Enable(level);<br>
}<br>
@@ -144,7 +144,7 @@ static inline void
_CPU_OR1K_Cache_instruction_block_lock<br>
ISR_Level level;<br>
_ISR_Disable (level);<br>
<br>
- _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr);<br>
+ _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);<br>
<br>
_ISR_Enable(level);<br>
}<br>
diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h
b/c/src/lib/libcpu/or1k/shared/cache/cache_.h<br>
index 5f08410..0ea939f 100644<br>
--- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h<br>
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h<br>
@@ -6,6 +6,7 @@<br>
#define __OR1K_CACHE_H<br>
<br>
#include <bsp/cache_.h><br>
+#include <libcpu/cache.h><br>
<br>
#endif<br>
/* end of include file */<br>
<span><font color="#888888">--<br>
1.9.3<br>
<br>
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</div></div><span class="HOEnZb"><font color="#888888"><pre cols="72">--
Joel Sherrill, Ph.D. Director of Research & Development
<a href="mailto:joel.sherrill@OARcorp.com" target="_blank">joel.sherrill@OARcorp.com</a> On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985</pre>
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