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<div class="moz-cite-prefix">Hi,<br>
<br>
On 18/10/2014 3:45 AM, Tomasz Gregorek wrote:<br>
</div>
<blockquote
cite="mid:CAMPqik4YJKsSD+CGBDKdDumjVN0he5eJirEV1rAN5ULrPFQYkg@mail.gmail.com"
type="cite">
<div dir="ltr">Hi Chris
<div><br>
</div>
<div><span style="color:rgb(0,0,0);font-family:'Courier
New',Courier,monospace;font-size:14px;white-space:pre-wrap">-
pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) )
/ pll_m / 48;
+ pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48;</span><br>
</div>
<div><span style="color:rgb(0,0,0);font-family:'Courier
New',Courier,monospace;font-size:14px;white-space:pre-wrap"><br>
</span></div>
<div>Your fix for the PLL_Q calculation is correct.</div>
<div>It supposed to be rounding from <=X.5 to X and from
>X.5 to (X+1) but first I messed up the equation second
this clock should not exceed 48MHz so rounding up is not
necessarily the best idea.</div>
</div>
</blockquote>
A check for clock <= 48MHz would be good. Even better if we can
check if USB is used and warn if it is not exactly 48MHz..<br>
<br>
<blockquote
cite="mid:CAMPqik4YJKsSD+CGBDKdDumjVN0he5eJirEV1rAN5ULrPFQYkg@mail.gmail.com"
type="cite">
<div dir="ltr">
<div><br>
</div>
<div><br>
</div>
<div>
<div><span style="color:rgb(0,0,0);font-family:'Courier
New',Courier,monospace;font-size:14px;white-space:pre-wrap">-#define
FLASH_ACR_LATENCY( val ) BSP_FLD32( val, 0, 3 )
-#define FLASH_ACR_LATENCY_MSK BSP_MSK32( 0, 3 )</span><br>
</div>
<div><br>
</div>
<div><span style="color:rgb(0,0,0);font-family:'Courier
New',Courier,monospace;font-size:14px;white-space:pre-wrap">+#define
STM32F4_FLASH_ACR_LATENCY(val) BSP_FLD32(val, 0, 2) //
Flash access latency
+#define STM32F4_FLASH_ACR_LATENCY_GET(reg)
BSP_FLD32GET(reg, 0, 2)
+#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val)
BSP_FLD32SET(reg, val, 0, 2)</span></div>
</div>
<div><span style="color:rgb(0,0,0);font-family:'Courier
New',Courier,monospace;font-size:14px;white-space:pre-wrap"><br>
</span></div>
<div>I would argue about the STM32F4_FLASH_ACR_LATENCY where you
use 3LSB of ACR (up to 7 wait states) which is correct for
the STM32F405xx/07xx and STM32F415xx/17xx while for
the STM32F42xxx and STM32F43xxx there are 4LSBs in use (up to
15 wait states). </div>
<div>I am not sure how to deal with it. Do we need to
distinguish for which chip we are compiling?</div>
</div>
</blockquote>
I think it should be safe to use 3 bits as it was. It's a pretty low
risk that someone will accidentally set a flash latency > 7 and
it is pretty likely a write to that bit would be ignored in the
hardware anyway.<br>
<br>
Ideally yes when we support STM42xxx etc. as well we should add a
build option, but there may be more we need to add, like the
operating chip voltage. Honesty my priority so far is first adding
register maps and example projects to make RTEMS more useful out of
the box for standard boards like STM32F4Discovery. <br>
<br>
<blockquote
cite="mid:CAMPqik4YJKsSD+CGBDKdDumjVN0he5eJirEV1rAN5ULrPFQYkg@mail.gmail.com"
type="cite">
<div dir="ltr">
<div><br>
</div>
<div><br>
</div>
<div>Thanks and regards</div>
<div>Tomasz</div>
<div><br>
</div>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">2014-10-18 11:06 GMT+02:00 Chris Nott <span
dir="ltr"><<a moz-do-not-send="true"
href="mailto:chrisn@vl.com.au" target="_blank">chrisn@vl.com.au</a>></span>:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">Hi,<br>
<br>
I sent these header file changes previously, they didn't get
picked up.<br>
<br>
I re-merged with the head, cleaned up formatting and fixed a
bug with PLL_Q setting not generating the right auxiliary
clock frequency for USB peripheral - Tomasz this was your
change, could you please review my fix.<br>
<br>
Regards,<br>
Chris.<br>
<br>
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</blockquote>
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<br>
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</blockquote>
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