<div dir="ltr">There is no documentation or information from forums I can find to get a lead. I suppose i will go ahead with mailboxes. Each core has 4 mailboxes, usage being left to us. One of the mailboxes can be used here.<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Aug 9, 2015 at 2:28 AM, Joel Sherrill <span dir="ltr"><<a href="mailto:joel.sherrill@oarcorp.com" target="_blank">joel.sherrill@oarcorp.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class=""><br>
<br>
On August 8, 2015 3:17:01 PM CDT, Rohini Kulkarni <<a href="mailto:krohini1593@gmail.com">krohini1593@gmail.com</a>> wrote:<br>
>Can mailboxes be useful here? Nothing else that is coming to my mind<br>
><br>
<br>
</span>They may be and I am seeing references to ARM's own mpcore which uses the GIC. This appears to be SOC specific but ARM has recommendations which may be followed by the SOC manufacturer<br>
<div class="HOEnZb"><div class="h5"><br>
>On Sun, Aug 9, 2015 at 1:44 AM, Rohini Kulkarni <<a href="mailto:krohini1593@gmail.com">krohini1593@gmail.com</a>><br>
>wrote:<br>
><br>
>Hi,<br>
><br>
>I am stuck at how to set up IPI for Pi 2. This is a document I have<br>
>referred to get an idea of interrupts. Would be great to get some help<br>
>on how to proceed.<br>
><br>
><br>
>On Fri, Jul 31, 2015 at 7:33 PM, Joel Sherrill<br>
><<a href="mailto:joel.sherrill@oarcorp.com">joel.sherrill@oarcorp.com</a>> wrote:<br>
><br>
><br>
><br>
>On 7/31/2015 8:11 AM, Rohini Kulkarni wrote:<br>
><br>
>Hi,<br>
><br>
>How is the number of processors to be used for an application<br>
>specified?<br>
>The used count minimum of that supported in hardware and that<br>
>configured. How to specify the latter?<br>
><br>
><br>
><a href="https://docs.rtems.org/doc-current/share/rtems/html/c_user/Configuring-a-System-SMP-Specific-Configuration-Parameters.html#Configuring-a-System-SMP-Specific-Configuration-Parameters" rel="noreferrer" target="_blank">https://docs.rtems.org/doc-current/share/rtems/html/c_user/Configuring-a-System-SMP-Specific-Configuration-Parameters.html#Configuring-a-System-SMP-Specific-Configuration-Parameters</a><br>
><br>
>and see the smptests. Many of which do specify the maximum.<br>
><br>
>Thanks.<br>
><br>
>On 29 Jul 2015 15:29, "Sebastian Huber"<br>
><<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a><br>
><mailto:<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a>>> wrote:<br>
><br>
><br>
><br>
> On 29/07/15 11:52, Rohini Kulkarni wrote:<br>
><br>
><br>
><br>
>On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber<br>
><<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a><br>
><mailto:<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a>><br>
><mailto:<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a><br>
><mailto:<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a>>>> wrote:<br>
><br>
> Hello Rohini,<br>
><br>
> please use the devel list.<br>
><br>
> On 28/07/15 07:41, Rohini Kulkarni wrote:<br>
><br>
> Hi,<br>
><br>
> I wish to understand where the interprocessor interrupts are<br>
> used during the boot process. During final initialization of<br>
> SMP I can see<br>
><br>
> rtems_interrupt_handler_install(<br>
> ARM_GIC_IRQ_SGI_0,<br>
> "IPI",<br>
> RTEMS_INTERRUPT_UNIQUE,<br>
> bsp_inter_processor_interrupt,<br>
> NULL<br>
> );<br>
><br>
> Raspberry Pi 2 does not have the generic interrupt controller.<br>
> Interrupt routing will have to be handled differently. So I<br>
> wish to understand how/ where it is used. I suppose this might<br>
> be the problem.<br>
><br>
><br>
> Sorry, that the documentation is so scattered. I think we should<br>
> move everything into the CPU Architecture Supplement. It would be<br>
> nice if you can help to improve the documentation since you have a<br>
> different view point.<br>
><br>
> You must install the IPI during the system initialization. It is<br>
> raised via the _CPU_SMP_Send_interrupt() function, for an example<br>
> see arm-a9mpcore-smp.c.<br>
><br>
>I could locate the function in arm-a9mpcore-smp.c. but it would be<br>
>helpful if I can know where this being called from, a deeper call<br>
>hierarchy, so that I can ascertain this is a problem. I can see a<br>
>Send_messgae function call this. But don't know where the send message<br>
>is being called from.<br>
><br>
><br>
>You can run one of the SMP tests on the realview_pbx_a9_qemu_smp BSP on<br>
>Qemu and set a break point to _CPU_SMP_Send_interrupt() if you want to<br>
>know how it is used.<br>
><br>
> --<br>
> Sebastian Huber, embedded brains GmbH<br>
><br>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany<br>
> Phone : +49 89 189 47 41-16<br>
> Fax : +49 89 189 47 41-09<br>
><br>
>E-Mail : <a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a><br>
><mailto:<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a>><br>
> PGP : Public key available on request.<br>
><br>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.<br>
><br>
><br>
>--<br>
>Joel Sherrill, Ph.D. Director of Research & Development<br>
>joel.sherrill@OARcorp.com On-Line Applications Research<br>
>Ask me about RTEMS: a free RTOS Huntsville AL 35805<br>
>Support Available (256) 722-9985<br>
><br>
><br>
><br>
><br>
>--<br>
><br>
>Rohini Kulkarni<br>
><br>
><br>
><br>
><br>
>--<br>
><br>
>Rohini Kulkarni<br>
<br>
</div></div><span class="HOEnZb"><font color="#888888">--joel<br>
</font></span></blockquote></div><br><br clear="all"><br>-- <br><div class="gmail_signature"><div dir="ltr">Rohini Kulkarni</div></div>
</div>