<div dir="ltr"><div>Hi,<br><br></div>It would be great if somebody can help here. <br><div><div><div>[1] How are the mailbox registers available for each core of Pi2
to be used. <br><br></div>[2] Another thing is that I
don't know which registers of Pi 1 are available for Pi2 as well. The ones in this <a href="https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf">link</a> , are quite different from the ones for Pi 1. <br><br></div><div>[3] Can the same mailbox interface as Pi1 be used?<br></div><div><br></div><div>Thanks.<br></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Aug 12, 2015 at 1:29 AM, Joel Sherrill <span dir="ltr"><<a href="mailto:joel.sherrill@oarcorp.com" target="_blank">joel.sherrill@oarcorp.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class=""><br>
<br>
On 8/11/2015 2:06 PM, Rohini Kulkarni wrote:<br>
</span><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi,<br>
<br><span class="">
I would have to register the related mailbox interrupt and associate it with a handler that should be same as _SMP_Inter_processor_interrupt_handler(). Am I right?<br>
</span></blockquote>
<br>
That sounds correct.<span class=""><br>
<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
From where can I get a reference of how to do this?<br>
</blockquote>
<br></span>
I would look at the Xilinx code that registers interrupts. The API<br>
should be the same. Also the clock driver, etc. The actual handler<br>
and IRQ number will vary.<br>
<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">
On 11 Aug 2015 00:41, "Joel Sherrill" <<a href="mailto:joel.sherrill@oarcorp.com" target="_blank">joel.sherrill@oarcorp.com</a> <mailto:<a href="mailto:joel.sherrill@oarcorp.com" target="_blank">joel.sherrill@oarcorp.com</a>>> wrote:<br>
<br>
The source for the CPU supplement is in doc/cpu_supplement in<br>
the RTEMS tree.<br>
<br>
I do not know when the latest online was built so reading it<br>
there is probably safest.<br>
<br>
To build it, you will likely have to install some texinfo and<br>
texlive tools.<br>
<br>
cd $r/doc<br>
../bootstrap<br>
cd ../..<br>
mkdir b-doc<br>
cd b-doc<br>
$r/doc/configure --enable-maintainer-mode \<br>
--prefix=DIRECTORY<br>
make<br>
make install<br>
<br>
That should be similar to how it is built.<br>
<br>
--joel<br>
<br>
<br>
On 8/10/2015 1:35 PM, Rohini Kulkarni wrote:<br>
<br>
The documentation that Sebastian was referring to.<br>
<br></span><span class="">
On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber <<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>>>> wrote:<br>
<br>
Hello Rohini,<br>
<br>
please use the devel list.<br>
<br>
On 28/07/15 07:41, Rohini Kulkarni wrote:<br>
<br>
Hi,<br>
<br>
I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see<br>
<br>
rtems_interrupt_handler_install(<br>
ARM_GIC_IRQ_SGI_0,<br>
"IPI",<br>
RTEMS_INTERRUPT_UNIQUE,<br>
bsp_inter_processor_interrupt,<br>
NULL<br>
);<br>
<br>
Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem.<br>
<br>
<br>
Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point.<br>
<br>
What is the CPU Architecture Supplement?<br>
<br>
<br>
You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c.<br>
<br>
<br>
<br>
Thanks.<br>
<br></span><span class="">
On Wed, Jul 22, 2015 at 7:08 PM, Rohini Kulkarni <<a href="mailto:krohini1593@gmail.com" target="_blank">krohini1593@gmail.com</a> <mailto:<a href="mailto:krohini1593@gmail.com" target="_blank">krohini1593@gmail.com</a>> <mailto:<a href="mailto:krohini1593@gmail.com" target="_blank">krohini1593@gmail.com</a> <mailto:<a href="mailto:krohini1593@gmail.com" target="_blank">krohini1593@gmail.com</a>>> <mailto:<a href="mailto:krohini1593@gmail.com" target="_blank">krohini1593@gmail.com</a> <mailto:<a href="mailto:krohini1593@gmail.com" target="_blank">krohini1593@gmail.com</a>> <mailto:<a href="mailto:krohini1593@gmail.com" target="_blank">krohini1593@gmail.com</a> <mailto:<a href="mailto:krohini1593@gmail.com" target="_blank">krohini1593@gmail.com</a>>>>> wrote:<br>
<br>
Ok. Qemu suggestion seems helpful for the cache configuration<br>
issue though. I am trying with Pi 1.<br>
<br>
Thanks.<br>
<br>
On 22 Jul 2015 18:59, "Sebastian Huber"<br>
<<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>>><br></span><span class="">
<mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>>>>> wrote:<br>
<br>
Sorry, I cannot help you here since I never worked with a<br>
Raspberry Pi.<br>
<br>
-- Sebastian Huber, embedded brains GmbH<br>
<br>
Address : Dornierstr. 4, D-82178 Puchheim, Germany<br>
Phone : +49 89 189 47 41-16<br>
Fax : +49 89 189 47 41-09<br>
E-Mail : <a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>>><br></span>
<mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>>>><span class=""><br>
PGP : Public key available on request.<br>
<br>
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne<br>
des EHUG.<br>
<br>
<br>
<br>
<br>
--<br>
Rohini Kulkarni<br>
<br>
<br>
--<br>
Sebastian Huber, embedded brains GmbH<br>
<br>
Address : Dornierstr. 4, D-82178 Puchheim, Germany<br>
Phone : +49 89 189 47 41-16<br>
Fax : +49 89 189 47 41-09<br>
E-Mail : <a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a> <mailto:<a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a>>><br>
PGP : Public key available on request.<br>
<br>
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.<br>
<br>
<br>
<br>
<br>
--<br>
Rohini Kulkarni<br>
<br>
<br>
--<br></span><span class="">
Joel Sherrill, Ph.D. Director of Research & Development<br>
joel.sherrill@OARcorp.com On-Line Applications Research<br>
Ask me about RTEMS: a free RTOS Huntsville AL 35805<br>
Support Available (256) 722-9985<br>
<br>
</span></blockquote><div class="HOEnZb"><div class="h5">
<br>
-- <br>
Joel Sherrill, Ph.D. Director of Research & Development<br>
joel.sherrill@OARcorp.com On-Line Applications Research<br>
Ask me about RTEMS: a free RTOS Huntsville AL 35805<br>
Support Available (256) 722-9985<br>
</div></div></blockquote></div><br><br clear="all"><br>-- <br><div class="gmail_signature"><div dir="ltr">Rohini Kulkarni</div></div>
</div>