<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Jan 3, 2016 at 8:02 PM, Gedare Bloom <span dir="ltr"><<a href="mailto:gedare@rtems.org" target="_blank">gedare@rtems.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The process should also (eventually) submit the removal of the tools<br>
from gcc upstream?<br>
<div class="HOEnZb"><div class="h5"><br></div></div></blockquote><div>Yep. Trying to sweep one thing at a time. These should only update the tickets</div><div>not close them. I haven't looked but the new tcp/ip stack and some other repos</div><div>may have references.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">
On Sun, Jan 3, 2016 at 4:27 PM, Joel Sherrill <<a href="mailto:joel@rtems.org">joel@rtems.org</a>> wrote:<br>
> From: Joel Sherrill <<a href="mailto:joel.sherrill@oarcorp.com">joel.sherrill@oarcorp.com</a>><br>
><br>
> updates #2446.<br>
> ---<br>
> c/src/aclocal/rtems-cpu-subdirs.m4 | 1 -<br>
> c/src/lib/libbsp/m32r/Makefile.am | 9 -<br>
> c/src/lib/libbsp/m32r/acinclude.m4 | 8 -<br>
> c/src/lib/libbsp/m32r/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a> | 20 -<br>
> cpukit/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a> | 4 +-<br>
> cpukit/libcsupport/src/newlibc_exit.c | 4 +-<br>
> .../libdl/include/arch/m32r/machine/elf_machdep.h | 39 -<br>
> cpukit/libdl/rtl-mdreloc-m32r.c | 156 ---<br>
> cpukit/libdl/rtl-shell.c | 2 +-<br>
> cpukit/librpc/src/xdr/xdr_float.c | 1 -<br>
> cpukit/score/cpu/Makefile.am | 1 -<br>
> cpukit/score/cpu/m32r/Makefile.am | 22 -<br>
> cpukit/score/cpu/m32r/context_init.c | 61 -<br>
> cpukit/score/cpu/m32r/context_switch.S | 67 -<br>
> cpukit/score/cpu/m32r/cpu.c | 125 --<br>
> cpukit/score/cpu/m32r/cpu_asm.c | 106 --<br>
> cpukit/score/cpu/m32r/m32r-exception-frame-print.c | 24 -<br>
> cpukit/score/cpu/m32r/<a href="http://preinstall.am" rel="noreferrer" target="_blank">preinstall.am</a> | 54 -<br>
> cpukit/score/cpu/m32r/rtems/asm.h | 127 --<br>
> cpukit/score/cpu/m32r/rtems/score/cpu.h | 1272 --------------------<br>
> cpukit/score/cpu/m32r/rtems/score/cpu_asm.h | 72 --<br>
> cpukit/score/cpu/m32r/rtems/score/cpuatomic.h | 14 -<br>
> cpukit/score/cpu/m32r/rtems/score/m32r.h | 70 --<br>
> cpukit/score/cpu/m32r/rtems/score/types.h | 52 -<br>
> cpukit/score/src/threadglobalconstruction.c | 4 +-<br>
> doc/cpu_supplement/Makefile.am | 8 +-<br>
> doc/cpu_supplement/cpu_supplement.texi | 2 -<br>
> doc/cpu_supplement/m32r.t | 11 -<br>
> doc/user/preface.texi | 3 +-<br>
> testsuites/libtests/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a> | 3 +-<br>
> 30 files changed, 7 insertions(+), 2335 deletions(-)<br>
> delete mode 100644 c/src/lib/libbsp/m32r/Makefile.am<br>
> delete mode 100644 c/src/lib/libbsp/m32r/acinclude.m4<br>
> delete mode 100644 c/src/lib/libbsp/m32r/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
> delete mode 100644 cpukit/libdl/include/arch/m32r/machine/elf_machdep.h<br>
> delete mode 100644 cpukit/libdl/rtl-mdreloc-m32r.c<br>
> delete mode 100644 cpukit/score/cpu/m32r/Makefile.am<br>
> delete mode 100644 cpukit/score/cpu/m32r/context_init.c<br>
> delete mode 100644 cpukit/score/cpu/m32r/context_switch.S<br>
> delete mode 100644 cpukit/score/cpu/m32r/cpu.c<br>
> delete mode 100644 cpukit/score/cpu/m32r/cpu_asm.c<br>
> delete mode 100644 cpukit/score/cpu/m32r/m32r-exception-frame-print.c<br>
> delete mode 100644 cpukit/score/cpu/m32r/<a href="http://preinstall.am" rel="noreferrer" target="_blank">preinstall.am</a><br>
> delete mode 100644 cpukit/score/cpu/m32r/rtems/asm.h<br>
> delete mode 100644 cpukit/score/cpu/m32r/rtems/score/cpu.h<br>
> delete mode 100644 cpukit/score/cpu/m32r/rtems/score/cpu_asm.h<br>
> delete mode 100644 cpukit/score/cpu/m32r/rtems/score/cpuatomic.h<br>
> delete mode 100644 cpukit/score/cpu/m32r/rtems/score/m32r.h<br>
> delete mode 100644 cpukit/score/cpu/m32r/rtems/score/types.h<br>
> delete mode 100644 doc/cpu_supplement/m32r.t<br>
><br>
> diff --git a/c/src/aclocal/rtems-cpu-subdirs.m4 b/c/src/aclocal/rtems-cpu-subdirs.m4<br>
> index 524edac..3cb28b1 100644<br>
> --- a/c/src/aclocal/rtems-cpu-subdirs.m4<br>
> +++ b/c/src/aclocal/rtems-cpu-subdirs.m4<br>
> @@ -18,7 +18,6 @@ _RTEMS_CPU_SUBDIR([h8300],[$1]);;<br>
> _RTEMS_CPU_SUBDIR([i386],[$1]);;<br>
> _RTEMS_CPU_SUBDIR([lm32],[$1]);;<br>
> _RTEMS_CPU_SUBDIR([m32c],[$1]);;<br>
> -_RTEMS_CPU_SUBDIR([m32r],[$1]);;<br>
> _RTEMS_CPU_SUBDIR([m68k],[$1]);;<br>
> _RTEMS_CPU_SUBDIR([mips],[$1]);;<br>
> _RTEMS_CPU_SUBDIR([moxie],[$1]);;<br>
> diff --git a/c/src/lib/libbsp/m32r/Makefile.am b/c/src/lib/libbsp/m32r/Makefile.am<br>
> deleted file mode 100644<br>
> index f504c03..0000000<br>
> --- a/c/src/lib/libbsp/m32r/Makefile.am<br>
> +++ /dev/null<br>
> @@ -1,9 +0,0 @@<br>
> -ACLOCAL_AMFLAGS = -I ../../../aclocal<br>
> -<br>
> -## Descend into the @RTEMS_BSP_FAMILY@ directory<br>
> -SUBDIRS = @RTEMS_BSP_FAMILY@<br>
> -<br>
> -EXTRA_DIST =<br>
> -<br>
> -include $(top_srcdir)/../../../automake/<a href="http://subdirs.am" rel="noreferrer" target="_blank">subdirs.am</a><br>
> -include $(top_srcdir)/../../../automake/<a href="http://local.am" rel="noreferrer" target="_blank">local.am</a><br>
> diff --git a/c/src/lib/libbsp/m32r/acinclude.m4 b/c/src/lib/libbsp/m32r/acinclude.m4<br>
> deleted file mode 100644<br>
> index 296a6f7..0000000<br>
> --- a/c/src/lib/libbsp/m32r/acinclude.m4<br>
> +++ /dev/null<br>
> @@ -1,8 +0,0 @@<br>
> -# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY)<br>
> -AC_DEFUN([RTEMS_CHECK_BSPDIR],<br>
> -[<br>
> - case "$1" in<br>
> - *)<br>
> - AC_MSG_ERROR([Invalid BSP]);;<br>
> - esac<br>
> -])<br>
> diff --git a/c/src/lib/libbsp/m32r/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a> b/c/src/lib/libbsp/m32r/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
> deleted file mode 100644<br>
> index 362e534..0000000<br>
> --- a/c/src/lib/libbsp/m32r/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
> +++ /dev/null<br>
> @@ -1,20 +0,0 @@<br>
> -## Process this file with autoconf to produce a configure script.<br>
> -<br>
> -AC_PREREQ([2.69])<br>
> -AC_INIT([rtems-c-src-lib-libbsp-m32r],[_RTEMS_VERSION],[<a href="https://devel.rtems.org/newticket" rel="noreferrer" target="_blank">https://devel.rtems.org/newticket</a>])<br>
> -AC_CONFIG_SRCDIR([Makefile.am])<br>
> -RTEMS_TOP(../../../../..)<br>
> -<br>
> -RTEMS_CANONICAL_TARGET_CPU<br>
> -AM_INIT_AUTOMAKE([no-define foreign 1.12.2])<br>
> -AM_MAINTAINER_MODE<br>
> -<br>
> -RTEMS_ENV_RTEMSBSP<br>
> -<br>
> -RTEMS_PROJECT_ROOT<br>
> -<br>
> -RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY])<br>
> -<br>
> -# Explicitly list all Makefiles here<br>
> -AC_CONFIG_FILES([Makefile])<br>
> -AC_OUTPUT<br>
> diff --git a/cpukit/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a> b/cpukit/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
> index f1589a8..8436c91 100644<br>
> --- a/cpukit/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
> +++ b/cpukit/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
> @@ -388,8 +388,7 @@ AM_CONDITIONAL([RPCTOOLS],[test "$RPCGEN" = rpcgen \<br>
> # reloc backends<br>
> AC_MSG_CHECKING([whether CPU supports libdl])<br>
> case $RTEMS_CPU in<br>
> - arm | i386 | m32r | m68k | mips | \<br>
> - moxie | powerpc | sparc)<br>
> + arm | i386 | m68k | mips | moxie | powerpc | sparc)<br>
> HAVE_LIBDL=yes ;;<br>
> # bfin has an issue to resolve with libdl. See ticket #2252<br>
> bfin)<br>
> @@ -463,7 +462,6 @@ score/cpu/i386/Makefile<br>
> score/cpu/lm32/Makefile<br>
> score/cpu/m68k/Makefile<br>
> score/cpu/m32c/Makefile<br>
> -score/cpu/m32r/Makefile<br>
> score/cpu/mips/Makefile<br>
> score/cpu/moxie/Makefile<br>
> score/cpu/nios2/Makefile<br>
> diff --git a/cpukit/libcsupport/src/newlibc_exit.c b/cpukit/libcsupport/src/newlibc_exit.c<br>
> index fad7f76..c093bb2 100644<br>
> --- a/cpukit/libcsupport/src/newlibc_exit.c<br>
> +++ b/cpukit/libcsupport/src/newlibc_exit.c<br>
> @@ -22,9 +22,7 @@<br>
> /* FIXME: These defines are a blatant hack */<br>
><br>
> #if defined(__USE_INIT_FINI__)<br>
> - #if defined(__m32r__)<br>
> - #define FINI_SYMBOL __fini<br>
> - #elif defined(__ARM_EABI__)<br>
> + #if defined(__ARM_EABI__)<br>
> #define FINI_SYMBOL __libc_fini_array<br>
> #else<br>
> #define FINI_SYMBOL _fini<br>
> diff --git a/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h b/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h<br>
> deleted file mode 100644<br>
> index 3f531cf..0000000<br>
> --- a/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h<br>
> +++ /dev/null<br>
> @@ -1,39 +0,0 @@<br>
> -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB<br>
> -<br>
> -#define ELF32_MACHDEP_ID_CASES \<br>
> - case EM_M32R: \<br>
> - break;<br>
> -<br>
> -#define ELF32_MACHDEP_ID EM_M32R<br>
> -<br>
> -#define ARCH_ELFSIZE 32<br>
> -<br>
> -#define R_M32R_NONE 0<br>
> -/*-----------OLD TYPE-------------*/<br>
> -#define R_M32R_16 1<br>
> -#define R_M32R_32 2<br>
> -#define R_M32R_24 3<br>
> -#define R_M32R_10_PCREL 4<br>
> -#define R_M32R_18_PCREL 5<br>
> -#define R_M32R_26_PCREL 6<br>
> -#define R_M32R_HI16_ULO 7<br>
> -#define R_M32R_HI16_SLO 8<br>
> -#define R_M32R_LO16 9<br>
> -#define R_M32R_SDA16 10<br>
> -#define R_M32R_GNU_VTINHERIT 11<br>
> -#define R_M32R_GNU_VTENTRY 12<br>
> -/*--------------------------------*/<br>
> -<br>
> -#define R_M32R_16_RELA 33<br>
> -#define R_M32R_32_RELA 34<br>
> -#define R_M32R_24_RELA 35<br>
> -#define R_M32R_18_PCREL_RELA 37<br>
> -#define R_M32R_26_PCREL_RELA 38<br>
> -#define R_M32R_HI16_ULO_RELA 39<br>
> -#define R_M32R_HI16_SLO_RELA 40<br>
> -#define R_M32R_LO16_RELA 41<br>
> -#define R_M32R_SDA16_RELA 42<br>
> -#define R_M32R_RELA_GNU_VTINHERIT 43<br>
> -#define R_M32R_RELA_GNU_VTENTRY 44<br>
> -<br>
> -#define R_TYPE(name) __CONCAT(R_M32R_,name)<br>
> diff --git a/cpukit/libdl/rtl-mdreloc-m32r.c b/cpukit/libdl/rtl-mdreloc-m32r.c<br>
> deleted file mode 100644<br>
> index 265e9cb..0000000<br>
> --- a/cpukit/libdl/rtl-mdreloc-m32r.c<br>
> +++ /dev/null<br>
> @@ -1,156 +0,0 @@<br>
> -#include <sys/cdefs.h><br>
> -<br>
> -#include <errno.h><br>
> -#include <stdio.h><br>
> -#include <sys/types.h><br>
> -#include <sys/stat.h><br>
> -<br>
> -#include <rtems/rtl/rtl.h><br>
> -#include "rtl-elf.h"<br>
> -#include "rtl-error.h"<br>
> -#include "rtl-trace.h"<br>
> -<br>
> -static inline Elf_Addr<br>
> -load_ptr(void *where)<br>
> -{<br>
> - Elf_Addr res;<br>
> -<br>
> - memcpy(&res, where, sizeof(res));<br>
> -<br>
> - return (res);<br>
> -}<br>
> -<br>
> -static inline void<br>
> -store_ptr(void *where, Elf_Addr val)<br>
> -{<br>
> - memcpy(where, &val, sizeof(val));<br>
> -}<br>
> -<br>
> -bool<br>
> -rtems_rtl_elf_rel_resolve_sym (Elf_Word type)<br>
> -{<br>
> - return true;<br>
> -}<br>
> -<br>
> -bool<br>
> -rtems_rtl_elf_relocate_rela (const rtems_rtl_obj_t* obj,<br>
> - const Elf_Rela* rela,<br>
> - const rtems_rtl_obj_sect_t* sect,<br>
> - const char* symname,<br>
> - const Elf_Byte syminfo,<br>
> - const Elf_Word symvalue)<br>
> -{<br>
> -<br>
> - Elf_Addr *where;<br>
> - Elf_Word tmp;<br>
> -<br>
> - where = (Elf_Addr *)(sect->base + rela->r_offset);<br>
> - if (rtems_rtl_trace (RTEMS_RTL_TRACE_RELOC)) {<br>
> - printf("relocated address 0x%08lx\n", (Elf_Addr)where);<br>
> - }<br>
> -<br>
> - switch (ELF_R_TYPE(rela->r_info)) {<br>
> - case R_TYPE(NONE):<br>
> - break;<br>
> -<br>
> - case R_TYPE(16_RELA):<br>
> - /*<br>
> - * half16: S + A<br>
> - */<br>
> - *(uint16_t *)where = (symvalue + rela->r_addend) & 0xffff;<br>
> - break;<br>
> -<br>
> - case R_TYPE(24_RELA):<br>
> - /*<br>
> - * imm24: (S + A) & 0xFFFFFF<br>
> - */<br>
> - tmp = symvalue + rela->r_addend;<br>
> - if (((Elf_Sword)tmp > 0x7fffff) || ((Elf_Sword)tmp < -0x800000)) {<br>
> - printf("24_RELA Overflow\n");<br>
> - return false;<br>
> - }<br>
> - *where = (*where & 0xff000000) | (tmp & 0xffffff);<br>
> - break;<br>
> -<br>
> - case R_TYPE(32_RELA):<br>
> - /*<br>
> - * word32: S + A<br>
> - */<br>
> - *where += symvalue + rela->r_addend;<br>
> - break;<br>
> -<br>
> - case R_TYPE(26_PCREL_RELA):<br>
> - /*<br>
> - * disp24: ((S + A - P) >> 2) & 0xFFFFFF<br>
> - */<br>
> - tmp = symvalue + rela->r_addend - (Elf_Addr)where;<br>
> - tmp = (Elf_Sword)tmp >> 2;<br>
> - if (((Elf_Sword)tmp > 0x7fffff) || ((Elf_Sword)tmp < -0x800000)) {<br>
> - printf("26_PCREL_RELA Overflow\n");<br>
> - return false;<br>
> - }<br>
> -<br>
> - *where = (*where & 0xff000000) | (tmp & 0xffffff);<br>
> - break;<br>
> -<br>
> - case R_TYPE(18_PCREL_RELA):<br>
> - /*<br>
> - * disp16: ((S + A - P) >> 2) & 0xFFFFFF<br>
> - */<br>
> - tmp = symvalue + rela->r_addend - (Elf_Addr)where;<br>
> - tmp = (Elf_Sword)tmp >> 2;<br>
> - if (((Elf_Sword)tmp > 0x7fff) || ((Elf_Sword)tmp < -0x8000)) {<br>
> - printf("18_PCREL_RELA Overflow\n");<br>
> - return false;<br>
> - }<br>
> -<br>
> - *where = (*where & 0xffff0000) | (tmp & 0xffff);<br>
> - break;<br>
> -<br>
> - case R_TYPE(HI16_ULO_RELA):<br>
> - /*<br>
> - * imm16: ((S + A) >> 16)<br>
> - */<br>
> - tmp = *where;<br>
> - tmp += ((symvalue + rela->r_addend) >> 16) & 0xffff;<br>
> - *where = tmp;<br>
> - break;<br>
> -<br>
> - case R_TYPE(HI16_SLO_RELA):<br>
> - /*<br>
> - * imm16: ((S + A) >> 16) or ((S + A + 0x10000) >> 16)<br>
> - */<br>
> - tmp = symvalue + rela->r_addend;<br>
> - if (tmp & 0x8000) tmp += 0x10000;<br>
> - tmp = (tmp >> 16) & 0xffff;<br>
> - *where += tmp;<br>
> - break;<br>
> -<br>
> - case R_TYPE(LO16_RELA):<br>
> - /*<br>
> - * imm16: (S + A) & 0xFFFF<br>
> - */<br>
> - tmp = symvalue + rela->r_addend;<br>
> - *where = (*where & 0xffff0000) | (tmp & 0xffff);<br>
> - break;<br>
> -<br>
> - default:<br>
> - rtems_rtl_set_error (EINVAL, "rela type record not supported");<br>
> - printf("Unsupported rela reloc types\n");<br>
> - return false;<br>
> - }<br>
> - return true;<br>
> -}<br>
> -<br>
> -bool<br>
> -rtems_rtl_elf_relocate_rel (const rtems_rtl_obj_t* obj,<br>
> - const Elf_Rel* rel,<br>
> - const rtems_rtl_obj_sect_t* sect,<br>
> - const char* symname,<br>
> - const Elf_Byte syminfo,<br>
> - const Elf_Word symvalue)<br>
> -{<br>
> -<br>
> - rtems_rtl_set_error (EINVAL, "rel type record not supported");<br>
> - return true;<br>
> -}<br>
> diff --git a/cpukit/libdl/rtl-shell.c b/cpukit/libdl/rtl-shell.c<br>
> index 20a6aab..a10c931 100644<br>
> --- a/cpukit/libdl/rtl-shell.c<br>
> +++ b/cpukit/libdl/rtl-shell.c<br>
> @@ -25,7 +25,7 @@<br>
> * Flag the targets where off_t is 32 bits. This is not a compiler type<br>
> * so we can't rely on prerdefines.<br>
> */<br>
> -#if defined(__m32r__) || defined(__moxie__)<br>
> +#if defined(__moxie__)<br>
> #define PRIdoff_t PRIo32<br>
> #else<br>
> #define PRIdoff_t PRIo64<br>
> diff --git a/cpukit/librpc/src/xdr/xdr_float.c b/cpukit/librpc/src/xdr/xdr_float.c<br>
> index ac8c46d..5d6b4ea 100644<br>
> --- a/cpukit/librpc/src/xdr/xdr_float.c<br>
> +++ b/cpukit/librpc/src/xdr/xdr_float.c<br>
> @@ -77,7 +77,6 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00<br>
> defined(__AVR__) || \<br>
> defined(__BFIN__) || \<br>
> defined(__m32c__) || \<br>
> - defined(__M32R__) || \<br>
> defined(__v850)<br>
><br>
> #include <rtems/endian.h><br>
> diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am<br>
> index 7279d38..4438e3f 100644<br>
> --- a/cpukit/score/cpu/Makefile.am<br>
> +++ b/cpukit/score/cpu/Makefile.am<br>
> @@ -9,7 +9,6 @@ DIST_SUBDIRS += h8300<br>
> DIST_SUBDIRS += i386<br>
> DIST_SUBDIRS += lm32<br>
> DIST_SUBDIRS += m32c<br>
> -DIST_SUBDIRS += m32r<br>
> DIST_SUBDIRS += m68k<br>
> DIST_SUBDIRS += mips<br>
> DIST_SUBDIRS += moxie<br>
> diff --git a/cpukit/score/cpu/m32r/Makefile.am b/cpukit/score/cpu/m32r/Makefile.am<br>
> deleted file mode 100644<br>
> index dcf0871..0000000<br>
> --- a/cpukit/score/cpu/m32r/Makefile.am<br>
> +++ /dev/null<br>
> @@ -1,22 +0,0 @@<br>
> -include $(top_srcdir)/automake/<a href="http://compile.am" rel="noreferrer" target="_blank">compile.am</a><br>
> -<br>
> -include_HEADERS =<br>
> -<br>
> -include_rtemsdir = $(includedir)/rtems<br>
> -include_rtems_HEADERS = rtems/asm.h<br>
> -<br>
> -include_rtems_scoredir = $(includedir)/rtems/score<br>
> -include_rtems_score_HEADERS = rtems/score/cpu.h<br>
> -include_rtems_score_HEADERS += rtems/score/m32r.h<br>
> -include_rtems_score_HEADERS += rtems/score/cpu_asm.h<br>
> -include_rtems_score_HEADERS += rtems/score/types.h<br>
> -include_rtems_score_HEADERS += rtems/score/cpuatomic.h<br>
> -<br>
> -noinst_LIBRARIES = libscorecpu.a<br>
> -libscorecpu_a_SOURCES = cpu.c cpu_asm.c context_switch.S context_init.c<br>
> -libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c<br>
> -libscorecpu_a_SOURCES += m32r-exception-frame-print.c<br>
> -libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)<br>
> -<br>
> -include $(srcdir)/<a href="http://preinstall.am" rel="noreferrer" target="_blank">preinstall.am</a><br>
> -include $(top_srcdir)/automake/<a href="http://local.am" rel="noreferrer" target="_blank">local.am</a><br>
> diff --git a/cpukit/score/cpu/m32r/context_init.c b/cpukit/score/cpu/m32r/context_init.c<br>
> deleted file mode 100644<br>
> index 90f582a..0000000<br>
> --- a/cpukit/score/cpu/m32r/context_init.c<br>
> +++ /dev/null<br>
> @@ -1,61 +0,0 @@<br>
> -/**<br>
> - * @file<br>
> - *<br>
> - * @brief M32R CPU Context Initialize<br>
> - */<br>
> -<br>
> -/*<br>
> - * COPYRIGHT (c) 1989-2008.<br>
> - * On-Line Applications Research Corporation (OAR).<br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - */<br>
> -<br>
> -#ifdef HAVE_CONFIG_H<br>
> -#include "config.h"<br>
> -#endif<br>
> -<br>
> -#include <stdint.h><br>
> -#include <rtems/system.h><br>
> -<br>
> -typedef struct {<br>
> - uint32_t marker;<br>
> -} Starting_Frame;<br>
> -<br>
> -#define _get_r12( _r12 ) \<br>
> - __asm__ volatile( "mv r12, %0" : "=r" (_r12))<br>
> -<br>
> -void _CPU_Context_Initialize(<br>
> - Context_Control *the_context,<br>
> - uint32_t *stack_base,<br>
> - uint32_t size,<br>
> - uint32_t new_level,<br>
> - void *entry_point,<br>
> - bool is_fp,<br>
> - void *tls_area<br>
> -)<br>
> -{<br>
> - void *stackEnd = stack_base;<br>
> - Starting_Frame *frame;<br>
> - uint32_t r12;<br>
> -<br>
> - stackEnd += size;<br>
> -<br>
> - frame = (Starting_Frame *)stackEnd;<br>
> - frame--;<br>
> - frame->marker = 0xa5a5a5a5;<br>
> -<br>
> - _get_r12( r12 );<br>
> -<br>
> - the_context->r8 = 0x88888888;<br>
> - the_context->r9 = 0x99999999;<br>
> - the_context->r10 = 0xaaaaaaaa;<br>
> - the_context->r11 = 0xbbbbbbbb;<br>
> - the_context->r12 = r12;<br>
> - the_context->r13_fp = 0;<br>
> - the_context->r14_lr = (uintptr_t) entry_point;<br>
> - the_context->r15_sp = (uintptr_t) frame;<br>
> -<br>
> -}<br>
> diff --git a/cpukit/score/cpu/m32r/context_switch.S b/cpukit/score/cpu/m32r/context_switch.S<br>
> deleted file mode 100644<br>
> index 9f52090..0000000<br>
> --- a/cpukit/score/cpu/m32r/context_switch.S<br>
> +++ /dev/null<br>
> @@ -1,67 +0,0 @@<br>
> -/*<br>
> - * Context switch for the Reneas M32C<br>
> - *<br>
> - * COPYRIGHT (c) 1989-2008.<br>
> - * On-Line Applications Research Corporation (OAR).<br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - */<br>
> -<br>
> -#ifdef HAVE_CONFIG_H<br>
> -#include "config.h"<br>
> -#endif<br>
> -<br>
> -#define ARG_EXECUTING 8<br>
> -#define ARG_HEIR 12<br>
> -<br>
> -#define CONTEXT_R8 0x00<br>
> -#define CONTEXT_R9 0x04<br>
> -#define CONTEXT_R10 0x08<br>
> -#define CONTEXT_R11 0x0C<br>
> -#define CONTEXT_R12 0x10<br>
> -#define CONTEXT_R13_FP 0x14<br>
> -#define CONTEXT_R14_LR 0x18<br>
> -#define CONTEXT_R15_SP 0x1C<br>
> -#define CONTEXT_ACC_LOW 0x20<br>
> -#define CONTEXT_ACC_HIGH 0x24<br>
> -<br>
> - .file "context_switch.S"<br>
> - .text<br>
> - .global _CPU_Context_switch<br>
> - .type _CPU_Context_switch, @function<br>
> -_CPU_Context_switch:<br>
> - st r8, @(CONTEXT_R8,r0)<br>
> - st r9, @(CONTEXT_R9,r0)<br>
> - st r10, @(CONTEXT_R10,r0)<br>
> - st r11, @(CONTEXT_R11,r0)<br>
> - st r12, @(CONTEXT_R12,r0)<br>
> - st r13, @(CONTEXT_R13_FP,r0)<br>
> - st r14, @(CONTEXT_R14_LR,r0)<br>
> - st r15, @(CONTEXT_R15_SP,r0)<br>
> - mvfaclo r2<br>
> - st r2, @(CONTEXT_ACC_LOW,r0)<br>
> - mvfachi r2<br>
> - st r2, @(CONTEXT_ACC_HIGH,r0)<br>
> -<br>
> -restore:<br>
> - ld r8, @(CONTEXT_R8,r1)<br>
> - ld r9, @(CONTEXT_R9,r1)<br>
> - ld r10, @(CONTEXT_R10,r1)<br>
> - ld r11, @(CONTEXT_R11,r1)<br>
> - ld r12, @(CONTEXT_R12,r1)<br>
> - ld r13, @(CONTEXT_R13_FP,r1)<br>
> - ld r14, @(CONTEXT_R14_LR,r1)<br>
> - ld r15, @(CONTEXT_R15_SP,r1)<br>
> - ld r2, @(CONTEXT_ACC_LOW,r1)<br>
> - mvtaclo r2<br>
> - ld r2, @(CONTEXT_ACC_HIGH,r1)<br>
> - mvtachi r2<br>
> - jmp lr<br>
> -<br>
> - .global _CPU_Context_Restart_self<br>
> - .type _CPU_Context_Restart_self, @function<br>
> -_CPU_Context_Restart_self:<br>
> - mv r1, r0<br>
> - bra restore<br>
> diff --git a/cpukit/score/cpu/m32r/cpu.c b/cpukit/score/cpu/m32r/cpu.c<br>
> deleted file mode 100644<br>
> index 7bdf490..0000000<br>
> --- a/cpukit/score/cpu/m32r/cpu.c<br>
> +++ /dev/null<br>
> @@ -1,125 +0,0 @@<br>
> -/**<br>
> - * @file<br>
> - *<br>
> - * @brief M32R CPU Support<br>
> - */<br>
> -<br>
> -/*<br>
> - * COPYRIGHT (c) 1989-2008.<br>
> - * On-Line Applications Research Corporation (OAR).<br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - */<br>
> -<br>
> -#ifdef HAVE_CONFIG_H<br>
> -#include "config.h"<br>
> -#endif<br>
> -<br>
> -#include <rtems/system.h><br>
> -#include <rtems/score/isr.h><br>
> -<br>
> -/* _CPU_Initialize<br>
> - *<br>
> - * This routine performs processor dependent initialization.<br>
> - *<br>
> - * INPUT PARAMETERS: NONE<br>
> - *<br>
> - * NO_CPU Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -<br>
> -void _CPU_Initialize(void)<br>
> -{<br>
> -}<br>
> -<br>
> -/*<br>
> - * This routine returns the current interrupt level.<br>
> - *<br>
> - * NO_CPU Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -<br>
> -uint32_t _CPU_ISR_Get_level( void )<br>
> -{<br>
> - return 0;<br>
> -}<br>
> -<br>
> -/*<br>
> - * _CPU_ISR_install_raw_handler<br>
> - *<br>
> - * NO_CPU Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -<br>
> -void _CPU_ISR_install_raw_handler(<br>
> - uint32_t vector,<br>
> - proc_ptr new_handler,<br>
> - proc_ptr *old_handler<br>
> -)<br>
> -{<br>
> - /*<br>
> - * This is where we install the interrupt handler into the "raw" interrupt<br>
> - * table used by the CPU to dispatch interrupt handlers.<br>
> - */<br>
> - /* _set_var_vect(new_handler,vector); */<br>
> -}<br>
> -<br>
> -/*<br>
> - * _CPU_ISR_install_vector<br>
> - *<br>
> - * This kernel routine installs the RTEMS handler for the<br>
> - * specified vector.<br>
> - *<br>
> - * Input parameters:<br>
> - * vector - interrupt vector number<br>
> - * old_handler - former ISR for this vector number<br>
> - * new_handler - replacement ISR for this vector number<br>
> - *<br>
> - * Output parameters: NONE<br>
> - *<br>
> - *<br>
> - * NO_CPU Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -<br>
> -void _CPU_ISR_install_vector(<br>
> - uint32_t vector,<br>
> - proc_ptr new_handler,<br>
> - proc_ptr *old_handler<br>
> -)<br>
> -{<br>
> - *old_handler = _ISR_Vector_table[ vector ];<br>
> -<br>
> - /*<br>
> - * If the interrupt vector table is a table of pointer to isr entry<br>
> - * points, then we need to install the appropriate RTEMS interrupt<br>
> - * handler for this vector number.<br>
> - */<br>
> -<br>
> - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );<br>
> -<br>
> - /*<br>
> - * We put the actual user ISR address in '_ISR_vector_table'. This will<br>
> - * be used by the _ISR_Handler so the user gets control.<br>
> - */<br>
> -<br>
> - _ISR_Vector_table[ vector ] = new_handler;<br>
> -}<br>
> -<br>
> -/*<br>
> - * _CPU_Install_interrupt_stack<br>
> - *<br>
> - * NO_CPU Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -<br>
> -void _CPU_Install_interrupt_stack( void )<br>
> -{<br>
> -}<br>
> diff --git a/cpukit/score/cpu/m32r/cpu_asm.c b/cpukit/score/cpu/m32r/cpu_asm.c<br>
> deleted file mode 100644<br>
> index f808f42..0000000<br>
> --- a/cpukit/score/cpu/m32r/cpu_asm.c<br>
> +++ /dev/null<br>
> @@ -1,106 +0,0 @@<br>
> -/**<br>
> - * @file<br>
> - *<br>
> - * @brief M32R ISR Handler<br>
> - *<br>
> - * cpu_asm.c ===> cpu_asm.S or cpu_asm.s<br>
> - *<br>
> - * @note This is supposed to be a .S or .s file NOT a C file.<br>
> - *<br>
> - * M32R does not yet have interrupt support. When this functionality<br>
> - * is written, this file should become obsolete.<br>
> - *<br>
> - */<br>
> -<br>
> -/*<br>
> - * COPYRIGHT (c) 1989-2008.<br>
> - * On-Line Applications Research Corporation (OAR).<br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - */<br>
> -<br>
> -#ifdef HAVE_CONFIG_H<br>
> -#include "config.h"<br>
> -#endif<br>
> -<br>
> -#include <rtems/system.h><br>
> -#include <rtems/score/cpu.h><br>
> -<br>
> -/*<br>
> - * Prototypes<br>
> - */<br>
> -void _ISR_Handler(void);<br>
> -<br>
> -/* void __ISR_Handler()<br>
> - *<br>
> - * This routine provides the RTEMS interrupt management.<br>
> - *<br>
> - * NO_CPU Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -<br>
> -void _ISR_Handler(void)<br>
> -{<br>
> - /*<br>
> - * This discussion ignores a lot of the ugly details in a real<br>
> - * implementation such as saving enough registers/state to be<br>
> - * able to do something real. Keep in mind that the goal is<br>
> - * to invoke a user's ISR handler which is written in C and<br>
> - * uses a certain set of registers.<br>
> - *<br>
> - * Also note that the exact order is to a large extent flexible.<br>
> - * Hardware will dictate a sequence for a certain subset of<br>
> - * _ISR_Handler while requirements for setting<br>
> - */<br>
> -<br>
> - /*<br>
> - * At entry to "common" _ISR_Handler, the vector number must be<br>
> - * available. On some CPUs the hardware puts either the vector<br>
> - * number or the offset into the vector table for this ISR in a<br>
> - * known place. If the hardware does not give us this information,<br>
> - * then the assembly portion of RTEMS for this port will contain<br>
> - * a set of distinct interrupt entry points which somehow place<br>
> - * the vector number in a known place (which is safe if another<br>
> - * interrupt nests this one) and branches to _ISR_Handler.<br>
> - *<br>
> - * save some or all context on stack<br>
> - * may need to save some special interrupt information for exit<br>
> - *<br>
> - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )<br>
> - * if ( _ISR_Nest_level == 0 )<br>
> - * switch to software interrupt stack<br>
> - * #endif<br>
> - *<br>
> - * _ISR_Nest_level++;<br>
> - *<br>
> - * _Thread_Dispatch_disable_level++;<br>
> - *<br>
> - * (*_ISR_Vector_table[ vector ])( vector );<br>
> - *<br>
> - * _Thread_Dispatch_disable_level--;<br>
> - *<br>
> - * --_ISR_Nest_level;<br>
> - *<br>
> - * if ( _ISR_Nest_level )<br>
> - * goto the label "exit interrupt (simple case)"<br>
> - *<br>
> - * if ( _Thread_Dispatch_disable_level )<br>
> - * goto the label "exit interrupt (simple case)"<br>
> - *<br>
> - * if ( _Thread_Dispatch_necessary ) {<br>
> - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch<br>
> - * prepare to get out of interrupt<br>
> - * return from interrupt (maybe to _ISR_Dispatch)<br>
> - *<br>
> - * LABEL "exit interrupt (simple case):<br>
> - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )<br>
> - * if outermost interrupt<br>
> - * restore stack<br>
> - * #endif<br>
> - * prepare to get out of interrupt<br>
> - * return from interrupt<br>
> - */<br>
> -}<br>
> diff --git a/cpukit/score/cpu/m32r/m32r-exception-frame-print.c b/cpukit/score/cpu/m32r/m32r-exception-frame-print.c<br>
> deleted file mode 100644<br>
> index 71e7e1c..0000000<br>
> --- a/cpukit/score/cpu/m32r/m32r-exception-frame-print.c<br>
> +++ /dev/null<br>
> @@ -1,24 +0,0 @@<br>
> -/*<br>
> - * Copyright (c) 2012 embedded brains GmbH. All rights reserved.<br>
> - *<br>
> - * embedded brains GmbH<br>
> - * Obere Lagerstr. 30<br>
> - * 82178 Puchheim<br>
> - * Germany<br>
> - * <<a href="mailto:rtems@embedded-brains.de">rtems@embedded-brains.de</a>><br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - */<br>
> -<br>
> -#ifdef HAVE_CONFIG_H<br>
> - #include "config.h"<br>
> -#endif<br>
> -<br>
> -#include <rtems/score/cpu.h><br>
> -<br>
> -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )<br>
> -{<br>
> - /* TODO */<br>
> -}<br>
> diff --git a/cpukit/score/cpu/m32r/<a href="http://preinstall.am" rel="noreferrer" target="_blank">preinstall.am</a> b/cpukit/score/cpu/m32r/<a href="http://preinstall.am" rel="noreferrer" target="_blank">preinstall.am</a><br>
> deleted file mode 100644<br>
> index 3d76b74..0000000<br>
> --- a/cpukit/score/cpu/m32r/<a href="http://preinstall.am" rel="noreferrer" target="_blank">preinstall.am</a><br>
> +++ /dev/null<br>
> @@ -1,54 +0,0 @@<br>
> -## Automatically generated by ampolish3 - Do not edit<br>
> -<br>
> -if AMPOLISH3<br>
> -$(srcdir)/<a href="http://preinstall.am" rel="noreferrer" target="_blank">preinstall.am</a>: Makefile.am<br>
> - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/<a href="http://preinstall.am" rel="noreferrer" target="_blank">preinstall.am</a><br>
> -endif<br>
> -<br>
> -PREINSTALL_DIRS =<br>
> -DISTCLEANFILES = $(PREINSTALL_DIRS)<br>
> -<br>
> -all-am: $(PREINSTALL_FILES)<br>
> -<br>
> -PREINSTALL_FILES =<br>
> -CLEANFILES = $(PREINSTALL_FILES)<br>
> -<br>
> -$(PROJECT_INCLUDE)/$(dirstamp):<br>
> - @$(MKDIR_P) $(PROJECT_INCLUDE)<br>
> - @: > $(PROJECT_INCLUDE)/$(dirstamp)<br>
> -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)<br>
> -<br>
> -$(PROJECT_INCLUDE)/rtems/$(dirstamp):<br>
> - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems<br>
> - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)<br>
> -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)<br>
> -<br>
> -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)<br>
> - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h<br>
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h<br>
> -<br>
> -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):<br>
> - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score<br>
> - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)<br>
> -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)<br>
> -<br>
> -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)<br>
> - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h<br>
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h<br>
> -<br>
> -$(PROJECT_INCLUDE)/rtems/score/m32r.h: rtems/score/m32r.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)<br>
> - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/m32r.h<br>
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/m32r.h<br>
> -<br>
> -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)<br>
> - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h<br>
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h<br>
> -<br>
> -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)<br>
> - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h<br>
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h<br>
> -<br>
> -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)<br>
> - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h<br>
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h<br>
> -<br>
> diff --git a/cpukit/score/cpu/m32r/rtems/asm.h b/cpukit/score/cpu/m32r/rtems/asm.h<br>
> deleted file mode 100644<br>
> index 11f5b87..0000000<br>
> --- a/cpukit/score/cpu/m32r/rtems/asm.h<br>
> +++ /dev/null<br>
> @@ -1,127 +0,0 @@<br>
> -/**<br>
> - * @file<br>
> - *<br>
> - * @brief Address the Problems Caused by Incompatible Flavor of<br>
> - * Assemblers and Toolsets<br>
> - *<br>
> - * This include file attempts to address the problems<br>
> - * caused by incompatible flavors of assemblers and<br>
> - * toolsets. It primarily addresses variations in the<br>
> - * use of leading underscores on symbols and the requirement<br>
> - * that register names be preceded by a %.<br>
> - *<br>
> - * NOTE: The spacing in the use of these macros<br>
> - * is critical to them working as advertised.<br>
> - */<br>
> -<br>
> -/*<br>
> - * COPYRIGHT:<br>
> - *<br>
> - * This file is based on similar code found in newlib available<br>
> - * from <a href="http://ftp.cygnus.com" rel="noreferrer" target="_blank">ftp.cygnus.com</a>. The file which was used had no copyright<br>
> - * notice. This file is freely distributable as long as the source<br>
> - * of the file is noted. This file is:<br>
> - *<br>
> - * COPYRIGHT (c) 1994-2006.<br>
> - * On-Line Applications Research Corporation (OAR).<br>
> - */<br>
> -<br>
> -#ifndef _RTEMS_ASM_H<br>
> -#define _RTEMS_ASM_H<br>
> -<br>
> -/*<br>
> - * Indicate we are in an assembly file and get the basic CPU definitions.<br>
> - */<br>
> -<br>
> -#ifndef ASM<br>
> -#define ASM<br>
> -#endif<br>
> -#include <rtems/score/cpuopts.h><br>
> -#include <rtems/score/m32r.h><br>
> -<br>
> -#ifndef __USER_LABEL_PREFIX__<br>
> -/**<br>
> - * Recent versions of GNU cpp define variables which indicate the<br>
> - * need for underscores and percents. If not using GNU cpp or<br>
> - * the version does not support this, then you will obviously<br>
> - * have to define these as appropriate.<br>
> - *<br>
> - * This symbol is prefixed to all C program symbols.<br>
> - */<br>
> -#define __USER_LABEL_PREFIX__ _<br>
> -#endif<br>
> -<br>
> -#ifndef __REGISTER_PREFIX__<br>
> -/**<br>
> - * Recent versions of GNU cpp define variables which indicate the<br>
> - * need for underscores and percents. If not using GNU cpp or<br>
> - * the version does not support this, then you will obviously<br>
> - * have to define these as appropriate.<br>
> - *<br>
> - * This symbol is prefixed to all register names.<br>
> - */<br>
> -#define __REGISTER_PREFIX__<br>
> -#endif<br>
> -<br>
> -#include <rtems/concat.h><br>
> -<br>
> -/** Use the right prefix for global labels. */<br>
> -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)<br>
> -<br>
> -/** Use the right prefix for registers. */<br>
> -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)<br>
> -<br>
> -/*<br>
> - * define macros for all of the registers on this CPU<br>
> - *<br>
> - * EXAMPLE: #define d0 REG (d0)<br>
> - */<br>
> -<br>
> -/*<br>
> - * Define macros to handle section beginning and ends.<br>
> - */<br>
> -<br>
> -<br>
> -/** This macro is used to denote the beginning of a code declaration. */<br>
> -#define BEGIN_CODE_DCL .text<br>
> -/** This macro is used to denote the end of a code declaration. */<br>
> -#define END_CODE_DCL<br>
> -/** This macro is used to denote the beginning of a data declaration section. */<br>
> -#define BEGIN_DATA_DCL .data<br>
> -/** This macro is used to denote the end of a data declaration section. */<br>
> -#define END_DATA_DCL<br>
> -/** This macro is used to denote the beginning of a code section. */<br>
> -#define BEGIN_CODE .text<br>
> -/** This macro is used to denote the end of a code section. */<br>
> -#define END_CODE<br>
> -/** This macro is used to denote the beginning of a data section. */<br>
> -#define BEGIN_DATA<br>
> -/** This macro is used to denote the end of a data section. */<br>
> -#define END_DATA<br>
> -/**<br>
> - * This macro is used to denote the beginning of the<br>
> - * unitialized data section.<br>
> - */<br>
> -#define BEGIN_BSS<br>
> -/** This macro is used to denote the end of the unitialized data section. */<br>
> -#define END_BSS<br>
> -/** This macro is used to denote the end of the assembly file. */<br>
> -#define END<br>
> -<br>
> -/**<br>
> - * This macro is used to declare a public global symbol.<br>
> - *<br>
> - * NOTE: This must be tailored for a particular flavor of the C compiler.<br>
> - * They may need to put underscores in front of the symbols.<br>
> - */<br>
> -#define PUBLIC(sym) .globl SYM (sym)<br>
> -<br>
> -/**<br>
> - * This macro is used to prototype a public global symbol.<br>
> - *<br>
> - * NOTE: This must be tailored for a particular flavor of the C compiler.<br>
> - * They may need to put underscores in front of the symbols.<br>
> - */<br>
> -#define EXTERN(sym) .globl SYM (sym)<br>
> -<br>
> -#endif<br>
> diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu.h b/cpukit/score/cpu/m32r/rtems/score/cpu.h<br>
> deleted file mode 100644<br>
> index 9ad41cd..0000000<br>
> --- a/cpukit/score/cpu/m32r/rtems/score/cpu.h<br>
> +++ /dev/null<br>
> @@ -1,1272 +0,0 @@<br>
> -/**<br>
> - * @file<br>
> - *<br>
> - * @brief Intel M32R CPU Dependent Source<br>
> - *<br>
> - * This include file contains information pertaining to the XXX<br>
> - * processor.<br>
> - *<br>
> - * NOTE: This file is part of a porting template that is intended<br>
> - * to be used as the starting point when porting RTEMS to a new<br>
> - * CPU family. The following needs to be done when using this as<br>
> - * the starting point for a new port:<br>
> - *<br>
> - * + Anywhere there is an XXX, it should be replaced<br>
> - * with information about the CPU family being ported to.<br>
> - *<br>
> - * + At the end of each comment section, there is a heading which<br>
> - * says "Port Specific Information:". When porting to RTEMS,<br>
> - * add CPU family specific information in this section<br>
> - */<br>
> -<br>
> -/*<br>
> - * COPYRIGHT (c) 1989-2008.<br>
> - * On-Line Applications Research Corporation (OAR).<br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - */<br>
> -<br>
> -#ifndef _RTEMS_SCORE_CPU_H<br>
> -#define _RTEMS_SCORE_CPU_H<br>
> -<br>
> -#ifdef __cplusplus<br>
> -extern "C" {<br>
> -#endif<br>
> -<br>
> -#include <rtems/score/types.h><br>
> -#include <rtems/score/m32r.h><br>
> -<br>
> -/* conditional compilation parameters */<br>
> -<br>
> -/**<br>
> - * Should the calls to @ref _Thread_Enable_dispatch be inlined?<br>
> - *<br>
> - * If TRUE, then they are inlined.<br>
> - * If FALSE, then a subroutine call is made.<br>
> - *<br>
> - * This conditional is an example of the classic trade-off of size<br>
> - * versus speed. Inlining the call (TRUE) typically increases the<br>
> - * size of RTEMS while speeding up the enabling of dispatching.<br>
> - *<br>
> - * NOTE: In general, the @ref _Thread_Dispatch_disable_level will<br>
> - * only be 0 or 1 unless you are in an interrupt handler and that<br>
> - * interrupt handler invokes the executive.] When not inlined<br>
> - * something calls @ref _Thread_Enable_dispatch which in turns calls<br>
> - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then<br>
> - * one subroutine call is avoided entirely.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_INLINE_ENABLE_DISPATCH FALSE<br>
> -<br>
> -/**<br>
> - * Does RTEMS manage a dedicated interrupt stack in software?<br>
> - *<br>
> - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.<br>
> - * If FALSE, nothing is done.<br>
> - *<br>
> - * If the CPU supports a dedicated interrupt stack in hardware,<br>
> - * then it is generally the responsibility of the BSP to allocate it<br>
> - * and set it up.<br>
> - *<br>
> - * If the CPU does not support a dedicated interrupt stack, then<br>
> - * the porter has two options: (1) execute interrupts on the<br>
> - * stack of the interrupted task, and (2) have RTEMS manage a dedicated<br>
> - * interrupt stack.<br>
> - *<br>
> - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.<br>
> - *<br>
> - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and<br>
> - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is<br>
> - * possible that both are FALSE for a particular CPU. Although it<br>
> - * is unclear what that would imply about the interrupt processing<br>
> - * procedure on that CPU.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE<br>
> -<br>
> -/**<br>
> - * Does the CPU follow the simple vectored interrupt model?<br>
> - *<br>
> - * If TRUE, then RTEMS allocates the vector table it internally manages.<br>
> - * If FALSE, then the BSP is assumed to allocate and manage the vector<br>
> - * table<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE<br>
> -<br>
> -/**<br>
> - * Does this CPU have hardware support for a dedicated interrupt stack?<br>
> - *<br>
> - * If TRUE, then it must be installed during initialization.<br>
> - * If FALSE, then no installation is performed.<br>
> - *<br>
> - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.<br>
> - *<br>
> - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and<br>
> - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is<br>
> - * possible that both are FALSE for a particular CPU. Although it<br>
> - * is unclear what that would imply about the interrupt processing<br>
> - * procedure on that CPU.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE<br>
> -<br>
> -/**<br>
> - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?<br>
> - *<br>
> - * If TRUE, then the memory is allocated during initialization.<br>
> - * If FALSE, then the memory is allocated during initialization.<br>
> - *<br>
> - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE<br>
> -<br>
> -/**<br>
> - * Does the RTEMS invoke the user's ISR with the vector number and<br>
> - * a pointer to the saved interrupt frame (1) or just the vector<br>
> - * number (0)?<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_ISR_PASSES_FRAME_POINTER 0<br>
> -<br>
> -/**<br>
> - * @def CPU_HARDWARE_FP<br>
> - *<br>
> - * Does the CPU have hardware floating point?<br>
> - *<br>
> - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.<br>
> - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.<br>
> - *<br>
> - * If there is a FP coprocessor such as the i387 or mc68881, then<br>
> - * the answer is TRUE.<br>
> - *<br>
> - * The macro name "M32R_HAS_FPU" should be made CPU specific.<br>
> - * It indicates whether or not this CPU model has FP support. For<br>
> - * example, it would be possible to have an i386_nofp CPU model<br>
> - * which set this to false to indicate that you have an i386 without<br>
> - * an i387 and wish to leave floating point support out of RTEMS.<br>
> - */<br>
> -<br>
> -/**<br>
> - * @def CPU_SOFTWARE_FP<br>
> - *<br>
> - * Does the CPU have no hardware floating point and GCC provides a<br>
> - * software floating point implementation which must be context<br>
> - * switched?<br>
> - *<br>
> - * This feature conditional is used to indicate whether or not there<br>
> - * is software implemented floating point that must be context<br>
> - * switched. The determination of whether or not this applies<br>
> - * is very tool specific and the state saved/restored is also<br>
> - * compiler specific.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#if ( M32R_HAS_FPU == 1 )<br>
> -#define CPU_HARDWARE_FP TRUE<br>
> -#else<br>
> -#define CPU_HARDWARE_FP FALSE<br>
> -#endif<br>
> -#define CPU_SOFTWARE_FP FALSE<br>
> -<br>
> -/**<br>
> - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?<br>
> - *<br>
> - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.<br>
> - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.<br>
> - *<br>
> - * So far, the only CPUs in which this option has been used are the<br>
> - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and<br>
> - * gcc both implicitly used the floating point registers to perform<br>
> - * integer multiplies. Similarly, the PowerPC port of gcc has been<br>
> - * seen to allocate floating point local variables and touch the FPU<br>
> - * even when the flow through a subroutine (like vfprintf()) might<br>
> - * not use floating point formats.<br>
> - *<br>
> - * If a function which you would not think utilize the FP unit DOES,<br>
> - * then one can not easily predict which tasks will use the FP hardware.<br>
> - * In this case, this option should be TRUE.<br>
> - *<br>
> - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_ALL_TASKS_ARE_FP TRUE<br>
> -<br>
> -/**<br>
> - * Should the IDLE task have a floating point context?<br>
> - *<br>
> - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task<br>
> - * and it has a floating point context which is switched in and out.<br>
> - * If FALSE, then the IDLE task does not have a floating point context.<br>
> - *<br>
> - * Setting this to TRUE negatively impacts the time required to preempt<br>
> - * the IDLE task from an interrupt because the floating point context<br>
> - * must be saved as part of the preemption.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_IDLE_TASK_IS_FP FALSE<br>
> -<br>
> -/**<br>
> - * Should the saving of the floating point registers be deferred<br>
> - * until a context switch is made to another different floating point<br>
> - * task?<br>
> - *<br>
> - * If TRUE, then the floating point context will not be stored until<br>
> - * necessary. It will remain in the floating point registers and not<br>
> - * disturned until another floating point task is switched to.<br>
> - *<br>
> - * If FALSE, then the floating point context is saved when a floating<br>
> - * point task is switched out and restored when the next floating point<br>
> - * task is restored. The state of the floating point registers between<br>
> - * those two operations is not specified.<br>
> - *<br>
> - * If the floating point context does NOT have to be saved as part of<br>
> - * interrupt dispatching, then it should be safe to set this to TRUE.<br>
> - *<br>
> - * Setting this flag to TRUE results in using a different algorithm<br>
> - * for deciding when to save and restore the floating point context.<br>
> - * The deferred FP switch algorithm minimizes the number of times<br>
> - * the FP context is saved and restored. The FP context is not saved<br>
> - * until a context switch is made to another, different FP task.<br>
> - * Thus in a system with only one FP task, the FP context will never<br>
> - * be saved or restored.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_USE_DEFERRED_FP_SWITCH TRUE<br>
> -<br>
> -/**<br>
> - * Does this port provide a CPU dependent IDLE task implementation?<br>
> - *<br>
> - * If TRUE, then the routine @ref _CPU_Thread_Idle_body<br>
> - * must be provided and is the default IDLE thread body instead of<br>
> - * @ref _CPU_Thread_Idle_body.<br>
> - *<br>
> - * If FALSE, then use the generic IDLE thread body if the BSP does<br>
> - * not provide one.<br>
> - *<br>
> - * This is intended to allow for supporting processors which have<br>
> - * a low power or idle mode. When the IDLE thread is executed, then<br>
> - * the CPU can be powered down.<br>
> - *<br>
> - * The order of precedence for selecting the IDLE thread body is:<br>
> - *<br>
> - * -# BSP provided<br>
> - * -# CPU dependent (if provided)<br>
> - * -# generic (if no BSP and no CPU dependent)<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE<br>
> -<br>
> -/**<br>
> - * Does the stack grow up (toward higher addresses) or down<br>
> - * (toward lower addresses)?<br>
> - *<br>
> - * If TRUE, then the grows upward.<br>
> - * If FALSE, then the grows toward smaller addresses.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_STACK_GROWS_UP TRUE<br>
> -<br>
> -/**<br>
> - * The following is the variable attribute used to force alignment<br>
> - * of critical RTEMS structures. On some processors it may make<br>
> - * sense to have these aligned on tighter boundaries than<br>
> - * the minimum requirements of the compiler in order to have as<br>
> - * much of the critical data area as possible in a cache line.<br>
> - *<br>
> - * The placement of this macro in the declaration of the variables<br>
> - * is based on the syntactically requirements of the GNU C<br>
> - * "__attribute__" extension. For example with GNU C, use<br>
> - * the following to force a structures to a 32 byte boundary.<br>
> - *<br>
> - * __attribute__ ((aligned (32)))<br>
> - *<br>
> - * NOTE: Currently only the Priority Bit Map table uses this feature.<br>
> - * To benefit from using this, the data must be heavily<br>
> - * used so it will stay in the cache and used frequently enough<br>
> - * in the executive to justify turning this on.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_STRUCTURE_ALIGNMENT<br>
> -<br>
> -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE<br>
> -<br>
> -/**<br>
> - * @defgroup CPUEndian Processor Dependent Endianness Support<br>
> - *<br>
> - * This group assists in issues related to processor endianness.<br>
> - *<br>
> - */<br>
> -/**@{**/<br>
> -<br>
> -/**<br>
> - * Define what is required to specify how the network to host conversion<br>
> - * routines are handled.<br>
> - *<br>
> - * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the<br>
> - * same values.<br>
> - *<br>
> - * @see CPU_LITTLE_ENDIAN<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_BIG_ENDIAN TRUE<br>
> -<br>
> -/**<br>
> - * Define what is required to specify how the network to host conversion<br>
> - * routines are handled.<br>
> - *<br>
> - * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the<br>
> - * same values.<br>
> - *<br>
> - * @see CPU_BIG_ENDIAN<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_LITTLE_ENDIAN FALSE<br>
> -<br>
> -/** @} */<br>
> -<br>
> -/**<br>
> - * @ingroup CPUInterrupt<br>
> - * The following defines the number of bits actually used in the<br>
> - * interrupt field of the task mode. How those bits map to the<br>
> - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_MODES_INTERRUPT_MASK 0x00000001<br>
> -<br>
> -#define CPU_PER_CPU_CONTROL_SIZE 0<br>
> -<br>
> -/*<br>
> - * Processor defined structures required for cpukit/score.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -<br>
> -/* may need to put some structures here. */<br>
> -<br>
> -typedef struct {<br>
> - /* There is no CPU specific per-CPU state */<br>
> -} CPU_Per_CPU_control;<br>
> -<br>
> -/**<br>
> - * @defgroup CPUContext Processor Dependent Context Management<br>
> - *<br>
> - * From the highest level viewpoint, there are 2 types of context to save.<br>
> - *<br>
> - * -# Interrupt registers to save<br>
> - * -# Task level registers to save<br>
> - *<br>
> - * Since RTEMS handles integer and floating point contexts separately, this<br>
> - * means we have the following 3 context items:<br>
> - *<br>
> - * -# task level context stuff:: Context_Control<br>
> - * -# floating point task stuff:: Context_Control_fp<br>
> - * -# special interrupt level context :: CPU_Interrupt_frame<br>
> - *<br>
> - * On some processors, it is cost-effective to save only the callee<br>
> - * preserved registers during a task context switch. This means<br>
> - * that the ISR code needs to save those registers which do not<br>
> - * persist across function calls. It is not mandatory to make this<br>
> - * distinctions between the caller/callee saves registers for the<br>
> - * purpose of minimizing context saved during task switch and on interrupts.<br>
> - * If the cost of saving extra registers is minimal, simplicity is the<br>
> - * choice. Save the same context on interrupt entry as for tasks in<br>
> - * this case.<br>
> - *<br>
> - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then<br>
> - * care should be used in designing the context area.<br>
> - *<br>
> - * On some CPUs with hardware floating point support, the Context_Control_fp<br>
> - * structure will not be used or it simply consist of an array of a<br>
> - * fixed number of bytes. This is done when the floating point context<br>
> - * is dumped by a "FP save context" type instruction and the format<br>
> - * is not really defined by the CPU. In this case, there is no need<br>
> - * to figure out the exact format -- only the size. Of course, although<br>
> - * this is enough information for RTEMS, it is probably not enough for<br>
> - * a debugger such as gdb. But that is another problem.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -/**@{**/<br>
> -<br>
> -/**<br>
> - * This defines the minimal set of integer and processor state registers<br>
> - * that must be saved during a voluntary context switch from one thread<br>
> - * to another.<br>
> - */<br>
> -typedef struct {<br>
> - /** r8 -- temporary register */<br>
> - uint32_t r8;<br>
> - /** r9 -- temporary register */<br>
> - uint32_t r9;<br>
> - /** r10 -- temporary register */<br>
> - uint32_t r10;<br>
> - /** r11 -- temporary register */<br>
> - uint32_t r11;<br>
> - /** r12 -- may be global pointer */<br>
> - uint32_t r12;<br>
> - /** r13 -- frame pointer */<br>
> - uint32_t r13_fp;<br>
> - /** r14 -- link register (aka return pointer */<br>
> - uint32_t r14_lr;<br>
> - /** r15 -- stack pointer */<br>
> - uint32_t r15_sp;<br>
> - /** dsp accumulator low order 32-bits */<br>
> - uint32_t acc_low;<br>
> - /** dsp accumulator high order 32-bits */<br>
> - uint32_t acc_high;<br>
> -} Context_Control;<br>
> -<br>
> -/**<br>
> - * This macro returns the stack pointer associated with @a _context.<br>
> - *<br>
> - * @param[in] _context is the thread context area to access<br>
> - *<br>
> - * @return This method returns the stack pointer.<br>
> - */<br>
> -#define _CPU_Context_Get_SP( _context ) \<br>
> - (_context)->r15_sp<br>
> -<br>
> -/**<br>
> - * This defines the complete set of floating point registers that must<br>
> - * be saved during any context switch from one thread to another.<br>
> - */<br>
> -typedef struct {<br>
> - /** FPU registers are listed here */<br>
> - double some_float_register;<br>
> -} Context_Control_fp;<br>
> -<br>
> -/**<br>
> - * This defines the set of integer and processor state registers that must<br>
> - * be saved during an interrupt. This set does not include any which are<br>
> - * in @ref Context_Control.<br>
> - */<br>
> -typedef struct {<br>
> - /** This field is a hint that a port will have a number of integer<br>
> - * registers that need to be saved when an interrupt occurs or<br>
> - * when a context switch occurs at the end of an ISR.<br>
> - */<br>
> - uint32_t special_interrupt_register;<br>
> -} CPU_Interrupt_frame;<br>
> -<br>
> -/**<br>
> - * This variable is optional. It is used on CPUs on which it is difficult<br>
> - * to generate an "uninitialized" FP context. It is filled in by<br>
> - * @ref _CPU_Initialize and copied into the task's FP context area during<br>
> - * @ref _CPU_Context_Initialize.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;<br>
> -<br>
> -/** @} */<br>
> -<br>
> -/**<br>
> - * @defgroup CPUInterrupt Processor Dependent Interrupt Management<br>
> - *<br>
> - * On some CPUs, RTEMS supports a software managed interrupt stack.<br>
> - * This stack is allocated by the Interrupt Manager and the switch<br>
> - * is performed in @ref _ISR_Handler. These variables contain pointers<br>
> - * to the lowest and highest addresses in the chunk of memory allocated<br>
> - * for the interrupt stack. Since it is unknown whether the stack<br>
> - * grows up or down (in general), this give the CPU dependent<br>
> - * code the option of picking the version it wants to use.<br>
> - *<br>
> - * NOTE: These two variables are required if the macro<br>
> - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -/**@{**/<br>
> -<br>
> -/*<br>
> - * Nothing prevents the porter from declaring more CPU specific variables.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -<br>
> -/* XXX: if needed, put more variables here */<br>
> -<br>
> -/**<br>
> - * @ingroup CPUContext<br>
> - * The size of the floating point context area. On some CPUs this<br>
> - * will not be a "sizeof" because the format of the floating point<br>
> - * area is not defined -- only the size is. This is usually on<br>
> - * CPUs with a "floating point save context" instruction.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )<br>
> -<br>
> -/**<br>
> - * Amount of extra stack (above minimum stack size) required by<br>
> - * MPCI receive server thread. Remember that in a multiprocessor<br>
> - * system this thread must exist and be able to process all directives.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0<br>
> -<br>
> -/**<br>
> - * This defines the number of entries in the @ref _ISR_Vector_table managed<br>
> - * by RTEMS.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32<br>
> -<br>
> -/**<br>
> - * This defines the highest interrupt vector number for this port.<br>
> - */<br>
> -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)<br>
> -<br>
> -/**<br>
> - * This is defined if the port has a special way to report the ISR nesting<br>
> - * level. Most ports maintain the variable @a _ISR_Nest_level.<br>
> - */<br>
> -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE<br>
> -<br>
> -/** @} */<br>
> -<br>
> -/**<br>
> - * @ingroup CPUContext<br>
> - * Should be large enough to run all RTEMS tests. This ensures<br>
> - * that a "reasonable" small application should not have any problems.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_STACK_MINIMUM_SIZE (1024)<br>
> -<br>
> -#define CPU_SIZEOF_POINTER 4<br>
> -<br>
> -/**<br>
> - * CPU's worst alignment requirement for data types on a byte boundary. This<br>
> - * alignment does not take into account the requirements for the stack.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_ALIGNMENT 8<br>
> -<br>
> -/**<br>
> - * This number corresponds to the byte alignment requirement for the<br>
> - * heap handler. This alignment requirement may be stricter than that<br>
> - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is<br>
> - * common for the heap to follow the same alignment requirement as<br>
> - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for<br>
> - * the heap, then this should be set to @ref CPU_ALIGNMENT.<br>
> - *<br>
> - * NOTE: This does not have to be a power of 2 although it should be<br>
> - * a multiple of 2 greater than or equal to 2. The requirement<br>
> - * to be a multiple of 2 is because the heap uses the least<br>
> - * significant field of the front and back flags to indicate<br>
> - * that a block is in use or free. So you do not want any odd<br>
> - * length blocks really putting length data in that bit.<br>
> - *<br>
> - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will<br>
> - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that<br>
> - * elements allocated from the heap meet all restrictions.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT<br>
> -<br>
> -/**<br>
> - * This number corresponds to the byte alignment requirement for memory<br>
> - * buffers allocated by the partition manager. This alignment requirement<br>
> - * may be stricter than that for the data types alignment specified by<br>
> - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same<br>
> - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is<br>
> - * strict enough for the partition, then this should be set to<br>
> - * @ref CPU_ALIGNMENT.<br>
> - *<br>
> - * NOTE: This does not have to be a power of 2. It does have to<br>
> - * be greater or equal to than @ref CPU_ALIGNMENT.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT<br>
> -<br>
> -/**<br>
> - * This number corresponds to the byte alignment requirement for the<br>
> - * stack. This alignment requirement may be stricter than that for the<br>
> - * data types alignment specified by @ref CPU_ALIGNMENT. If the<br>
> - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be<br>
> - * set to 0.<br>
> - *<br>
> - * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define CPU_STACK_ALIGNMENT 0<br>
> -<br>
> -/*<br>
> - * ISR handler macros<br>
> - */<br>
> -<br>
> -/**<br>
> - * @addtogroup CPUInterrupt<br>
> - */<br>
> -/**@{**/<br>
> -<br>
> -/**<br>
> - * Support routine to initialize the RTEMS vector table after it is allocated.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define _CPU_Initialize_vectors()<br>
> -<br>
> -/**<br>
> - * Disable all interrupts for an RTEMS critical section. The previous<br>
> - * level is returned in @a _isr_cookie.<br>
> - *<br>
> - * @param[out] _isr_cookie will contain the previous level cookie<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * TODO: As of 8 October 2014, this method is not implemented.<br>
> - */<br>
> -#define _CPU_ISR_Disable( _isr_cookie ) \<br>
> - do { \<br>
> - (_isr_cookie) = 0; \<br>
> - } while (0)<br>
> -<br>
> -/**<br>
> - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).<br>
> - * This indicates the end of an RTEMS critical section. The parameter<br>
> - * @a _isr_cookie is not modified.<br>
> - *<br>
> - * @param[in] _isr_cookie contain the previous level cookie<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * TODO: As of 8 October 2014, this method is not implemented.<br>
> - */<br>
> -#define _CPU_ISR_Enable( _isr_cookie ) \<br>
> - do { \<br>
> - (_isr_cookie) = (_isr_cookie); \<br>
> - } while (0)<br>
> -<br>
> -/**<br>
> - * This temporarily restores the interrupt to @a _isr_cookie before immediately<br>
> - * disabling them again. This is used to divide long RTEMS critical<br>
> - * sections into two or more parts. The parameter @a _isr_cookie is not<br>
> - * modified.<br>
> - *<br>
> - * @param[in] _isr_cookie contain the previous level cookie<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * TODO: As of 8 October 2014, this method is not implemented.<br>
> - */<br>
> -#define _CPU_ISR_Flash( _isr_cookie ) \<br>
> - do { \<br>
> - _CPU_ISR_Enable( _isr_cookie ); \<br>
> - _CPU_ISR_Disable( _isr_cookie ); \<br>
> - } while (0)<br>
> -<br>
> -/**<br>
> - * This routine and @ref _CPU_ISR_Get_level<br>
> - * Map the interrupt level in task mode onto the hardware that the CPU<br>
> - * actually provides. Currently, interrupt levels which do not<br>
> - * map onto the CPU in a generic fashion are undefined. Someday,<br>
> - * it would be nice if these were "mapped" by the application<br>
> - * via a callout. For example, m68k has 8 levels 0 - 7, levels<br>
> - * 8 - 255 would be available for bsp/application specific meaning.<br>
> - * This could be used to manage a programmable interrupt controller<br>
> - * via the rtems_task_mode directive.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * TODO: As of 8 October 2014, this method is not implemented.<br>
> - */<br>
> -static inline void _CPU_ISR_Set_level( unsigned int new_level )<br>
> -{<br>
> -}<br>
> -<br>
> -/**<br>
> - * Return the current interrupt disable level for this task in<br>
> - * the format used by the interrupt level portion of the task mode.<br>
> - *<br>
> - * NOTE: This routine usually must be implemented as a subroutine.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * TODO: As of 8 October 2014, this method is not implemented.<br>
> - */<br>
> -uint32_t _CPU_ISR_Get_level( void );<br>
> -<br>
> -/* end of ISR handler macros */<br>
> -<br>
> -/** @} */<br>
> -<br>
> -/* Context handler macros */<br>
> -<br>
> -/**<br>
> - * @brief Initialize CPU context.<br>
> - *<br>
> - * @ingroup CPUContext<br>
> - * Initialize the context to a state suitable for starting a<br>
> - * task after a context restore operation. Generally, this<br>
> - * involves:<br>
> - *<br>
> - * - setting a starting address<br>
> - * - preparing the stack<br>
> - * - preparing the stack and frame pointers<br>
> - * - setting the proper interrupt level in the context<br>
> - * - initializing the floating point context<br>
> - *<br>
> - * This routine generally does not set any unnecessary register<br>
> - * in the context. The state of the "general data" registers is<br>
> - * undefined at task start time.<br>
> - *<br>
> - * @param[in] _the_context is the context structure to be initialized<br>
> - * @param[in] _stack_base is the lowest physical address of this task's stack<br>
> - * @param[in] _size is the size of this task's stack<br>
> - * @param[in] _isr is the interrupt disable level<br>
> - * @param[in] _entry_point is the thread's entry point. This is<br>
> - * always @a _Thread_Handler<br>
> - * @param[in] _is_fp is TRUE if the thread is to be a floating<br>
> - * point thread. This is typically only used on CPUs where the<br>
> - * FPU may be easily disabled by software such as on the SPARC<br>
> - * where the PSR contains an enable FPU bit.<br>
> - * @param[in] tls_area is the thread-local storage (TLS) area<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_Context_Initialize(<br>
> - Context_Control *the_context,<br>
> - uint32_t *stack_base,<br>
> - size_t size,<br>
> - uint32_t new_level,<br>
> - void *entry_point,<br>
> - bool is_fp,<br>
> - void *tls_area<br>
> -);<br>
> -<br>
> -/**<br>
> - * This routine is responsible for somehow restarting the currently<br>
> - * executing task. If you are lucky, then all that is necessary<br>
> - * is restoring the context. Otherwise, there will need to be<br>
> - * a special assembly routine which does something special in this<br>
> - * case. For many ports, simply adding a label to the restore path<br>
> - * of @ref _CPU_Context_switch will work. On other ports, it may be<br>
> - * possibly to load a few arguments and jump to the restore path. It will<br>
> - * not work if restarting self conflicts with the stack frame<br>
> - * assumptions of restoring a context.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_Context_Restart_self(<br>
> - Context_Control *the_context<br>
> -) RTEMS_NO_RETURN;<br>
> -<br>
> -/**<br>
> - * @ingroup CPUContext<br>
> - * The purpose of this macro is to allow the initial pointer into<br>
> - * a floating point context area (used to save the floating point<br>
> - * context) to be at an arbitrary place in the floating point<br>
> - * context area.<br>
> - *<br>
> - * This is necessary because some FP units are designed to have<br>
> - * their context saved as a stack which grows into lower addresses.<br>
> - * Other FP units can be saved by simply moving registers into offsets<br>
> - * from the base of the context area. Finally some FP units provide<br>
> - * a "dump context" instruction which could fill in from high to low<br>
> - * or low to high based on the whim of the CPU designers.<br>
> - *<br>
> - * @param[in] _base is the lowest physical address of the floating point<br>
> - * context area<br>
> - * @param[in] _offset is the offset into the floating point area<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define _CPU_Context_Fp_start( _base, _offset ) \<br>
> - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )<br>
> -<br>
> -/**<br>
> - * This routine initializes the FP context area passed to it to.<br>
> - * There are a few standard ways in which to initialize the<br>
> - * floating point context. The code included for this macro assumes<br>
> - * that this is a CPU in which a "initial" FP context was saved into<br>
> - * @a _CPU_Null_fp_context and it simply copies it to the destination<br>
> - * context passed to it.<br>
> - *<br>
> - * Other floating point context save/restore models include:<br>
> - * -# not doing anything, and<br>
> - * -# putting a "null FP status word" in the correct place in the FP context.<br>
> - *<br>
> - * @param[in] _destination is the floating point context area<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define _CPU_Context_Initialize_fp( _destination ) \<br>
> - { \<br>
> - *(*(_destination)) = _CPU_Null_fp_context; \<br>
> - }<br>
> -<br>
> -/* end of Context handler macros */<br>
> -<br>
> -/* Fatal Error manager macros */<br>
> -<br>
> -/**<br>
> - * This routine copies _error into a known place -- typically a stack<br>
> - * location or a register, optionally disables interrupts, and<br>
> - * halts/stops the CPU.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#define _CPU_Fatal_halt( _source, _error ) \<br>
> - { \<br>
> - }<br>
> -<br>
> -/* end of Fatal Error manager macros */<br>
> -<br>
> -/* Bitfield handler macros */<br>
> -<br>
> -/**<br>
> - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation<br>
> - *<br>
> - * This set of routines are used to implement fast searches for<br>
> - * the most important ready task.<br>
> - */<br>
> -/**@{**/<br>
> -<br>
> -/**<br>
> - * This definition is set to TRUE if the port uses the generic bitfield<br>
> - * manipulation implementation.<br>
> - */<br>
> -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE<br>
> -<br>
> -/**<br>
> - * This definition is set to TRUE if the port uses the data tables provided<br>
> - * by the generic bitfield manipulation implementation.<br>
> - * This can occur when actually using the generic bitfield manipulation<br>
> - * implementation or when implementing the same algorithm in assembly<br>
> - * language for improved performance. It is unlikely that a port will use<br>
> - * the data if it has a bitfield scan instruction.<br>
> - */<br>
> -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE<br>
> -<br>
> -/**<br>
> - * This routine sets @a _output to the bit number of the first bit<br>
> - * set in @a _value. @a _value is of CPU dependent type<br>
> - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits<br>
> - * wide although only the 16 least significant bits will be used.<br>
> - *<br>
> - * There are a number of variables in using a "find first bit" type<br>
> - * instruction.<br>
> - *<br>
> - * -# What happens when run on a value of zero?<br>
> - * -# Bits may be numbered from MSB to LSB or vice-versa.<br>
> - * -# The numbering may be zero or one based.<br>
> - * -# The "find first bit" instruction may search from MSB or LSB.<br>
> - *<br>
> - * RTEMS guarantees that (1) will never happen so it is not a concern.<br>
> - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and<br>
> - * @ref _CPU_Priority_bits_index. These three form a set of routines<br>
> - * which must logically operate together. Bits in the _value are<br>
> - * set and cleared based on masks built by @ref _CPU_Priority_Mask.<br>
> - * The basic major and minor values calculated by @ref _Priority_Major<br>
> - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index<br>
> - * to properly range between the values returned by the "find first bit"<br>
> - * instruction. This makes it possible for @ref _Priority_Get_highest to<br>
> - * calculate the major and directly index into the minor table.<br>
> - * This mapping is necessary to ensure that 0 (a high priority major/minor)<br>
> - * is the first bit found.<br>
> - *<br>
> - * This entire "find first bit" and mapping process depends heavily<br>
> - * on the manner in which a priority is broken into a major and minor<br>
> - * components with the major being the 4 MSB of a priority and minor<br>
> - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest<br>
> - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next<br>
> - * to the lowest priority.<br>
> - *<br>
> - * If your CPU does not have a "find first bit" instruction, then<br>
> - * there are ways to make do without it. Here are a handful of ways<br>
> - * to implement this in software:<br>
> - *<br>
> -@verbatim<br>
> - - a series of 16 bit test instructions<br>
> - - a "binary search using if's"<br>
> - - _number = 0<br>
> - if _value > 0x00ff<br>
> - _value >>=8<br>
> - _number = 8;<br>
> -<br>
> - if _value > 0x0000f<br>
> - _value >=8<br>
> - _number += 4<br>
> -<br>
> - _number += bit_set_table[ _value ]<br>
> -@endverbatim<br>
> -<br>
> - * where bit_set_table[ 16 ] has values which indicate the first<br>
> - * bit set<br>
> - *<br>
> - * @param[in] _value is the value to be scanned<br>
> - * @param[in] _output is the first bit set<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -<br>
> -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)<br>
> -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \<br>
> - { \<br>
> - (_output) = 0; /* do something to prevent warnings */ \<br>
> - }<br>
> -#endif<br>
> -<br>
> -/* end of Bitfield handler macros */<br>
> -<br>
> -/**<br>
> - * This routine builds the mask which corresponds to the bit fields<br>
> - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion<br>
> - * for that routine.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)<br>
> -<br>
> -#define _CPU_Priority_Mask( _bit_number ) \<br>
> - ( 1 << (_bit_number) )<br>
> -<br>
> -#endif<br>
> -<br>
> -/**<br>
> - * This routine translates the bit numbers returned by<br>
> - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as<br>
> - * a major or minor component of a priority. See the discussion<br>
> - * for that routine.<br>
> - *<br>
> - * @param[in] _priority is the major or minor number to translate<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)<br>
> -<br>
> -#define _CPU_Priority_bits_index( _priority ) \<br>
> - (_priority)<br>
> -<br>
> -#endif<br>
> -<br>
> -/* end of Priority handler macros */<br>
> -<br>
> -/** @} */<br>
> -<br>
> -/* functions */<br>
> -<br>
> -/**<br>
> - * @brief CPU initialization.<br>
> - *<br>
> - * This routine performs CPU dependent initialization.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_Initialize(void);<br>
> -<br>
> -/**<br>
> - * @ingroup CPUInterrupt<br>
> - * This routine installs a "raw" interrupt handler directly into the<br>
> - * processor's vector table.<br>
> - *<br>
> - * @param[in] vector is the vector number<br>
> - * @param[in] new_handler is the raw ISR handler to install<br>
> - * @param[in] old_handler is the previously installed ISR Handler<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_ISR_install_raw_handler(<br>
> - uint32_t vector,<br>
> - proc_ptr new_handler,<br>
> - proc_ptr *old_handler<br>
> -);<br>
> -<br>
> -/**<br>
> - * @ingroup CPUInterrupt<br>
> - * This routine installs an interrupt vector.<br>
> - *<br>
> - * @param[in] vector is the vector number<br>
> - * @param[in] new_handler is the RTEMS ISR handler to install<br>
> - * @param[in] old_handler is the previously installed ISR Handler<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_ISR_install_vector(<br>
> - uint32_t vector,<br>
> - proc_ptr new_handler,<br>
> - proc_ptr *old_handler<br>
> -);<br>
> -<br>
> -/**<br>
> - * @ingroup CPUInterrupt<br>
> - * This routine installs the hardware interrupt stack pointer.<br>
> - *<br>
> - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK<br>
> - * is TRUE.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_Install_interrupt_stack( void );<br>
> -<br>
> -/**<br>
> - * @ingroup CPUContext<br>
> - * This routine switches from the run context to the heir context.<br>
> - *<br>
> - * @param[in] run points to the context of the currently executing task<br>
> - * @param[in] heir points to the context of the heir task<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_Context_switch(<br>
> - Context_Control *run,<br>
> - Context_Control *heir<br>
> -);<br>
> -<br>
> -/**<br>
> - * @addtogroup CPUContext<br>
> - */<br>
> -/**@{**/<br>
> -<br>
> -/**<br>
> - * This routine is generally used only to restart self in an<br>
> - * efficient manner. It may simply be a label in @ref _CPU_Context_switch.<br>
> - *<br>
> - * @param[in] new_context points to the context to be restored.<br>
> - *<br>
> - * NOTE: May be unnecessary to reload some registers.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_Context_restore(<br>
> - Context_Control *new_context<br>
> -) RTEMS_NO_RETURN;<br>
> -<br>
> -/**<br>
> - * This routine saves the floating point context passed to it.<br>
> - *<br>
> - * @param[in] fp_context_ptr is a pointer to a pointer to a floating<br>
> - * point context area<br>
> - *<br>
> - * @return on output @a *fp_context_ptr will contain the address that<br>
> - * should be used with @ref _CPU_Context_restore_fp to restore this context.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_Context_save_fp(<br>
> - Context_Control_fp **fp_context_ptr<br>
> -);<br>
> -<br>
> -/**<br>
> - * This routine restores the floating point context passed to it.<br>
> - *<br>
> - * @param[in] fp_context_ptr is a pointer to a pointer to a floating<br>
> - * point context area to restore<br>
> - *<br>
> - * @return on output @a *fp_context_ptr will contain the address that<br>
> - * should be used with @ref _CPU_Context_save_fp to save this context.<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -void _CPU_Context_restore_fp(<br>
> - Context_Control_fp **fp_context_ptr<br>
> -);<br>
> -<br>
> -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )<br>
> -{<br>
> - /* TODO */<br>
> -}<br>
> -<br>
> -static inline void _CPU_Context_validate( uintptr_t pattern )<br>
> -{<br>
> - while (1) {<br>
> - /* TODO */<br>
> - }<br>
> -}<br>
> -<br>
> -/** @} */<br>
> -<br>
> -/* FIXME */<br>
> -typedef CPU_Interrupt_frame CPU_Exception_frame;<br>
> -<br>
> -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );<br>
> -<br>
> -/**<br>
> - * @ingroup CPUEndian<br>
> - * The following routine swaps the endian format of an unsigned int.<br>
> - * It must be static because it is referenced indirectly.<br>
> - *<br>
> - * This version will work on any processor, but if there is a better<br>
> - * way for your CPU PLEASE use it. The most common way to do this is to:<br>
> - *<br>
> - * swap least significant two bytes with 16-bit rotate<br>
> - * swap upper and lower 16-bits<br>
> - * swap most significant two bytes with 16-bit rotate<br>
> - *<br>
> - * Some CPUs have special instructions which swap a 32-bit quantity in<br>
> - * a single instruction (e.g. i486). It is probably best to avoid<br>
> - * an "endian swapping control bit" in the CPU. One good reason is<br>
> - * that interrupts would probably have to be disabled to ensure that<br>
> - * an interrupt does not try to access the same "chunk" with the wrong<br>
> - * endian. Another good reason is that on some CPUs, the endian bit<br>
> - * endianness for ALL fetches -- both code and data -- so the code<br>
> - * will be fetched incorrectly.<br>
> - *<br>
> - * @param[in] value is the value to be swapped<br>
> - * @return the value after being endian swapped<br>
> - *<br>
> - * Port Specific Information:<br>
> - *<br>
> - * XXX document implementation including references if appropriate<br>
> - */<br>
> -static inline uint32_t CPU_swap_u32(<br>
> - uint32_t value<br>
> -)<br>
> -{<br>
> - uint32_t byte1, byte2, byte3, byte4, swapped;<br>
> -<br>
> - byte4 = (value >> 24) & 0xff;<br>
> - byte3 = (value >> 16) & 0xff;<br>
> - byte2 = (value >> 8) & 0xff;<br>
> - byte1 = value & 0xff;<br>
> -<br>
> - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;<br>
> - return swapped;<br>
> -}<br>
> -<br>
> -/**<br>
> - * @ingroup CPUEndian<br>
> - * This routine swaps a 16 bir quantity.<br>
> - *<br>
> - * @param[in] value is the value to be swapped<br>
> - * @return the value after being endian swapped<br>
> - */<br>
> -#define CPU_swap_u16( value ) \<br>
> - (((value&0xff) << 8) | ((value >> 8)&0xff))<br>
> -<br>
> -typedef uint32_t CPU_Counter_ticks;<br>
> -<br>
> -CPU_Counter_ticks _CPU_Counter_read( void );<br>
> -<br>
> -static inline CPU_Counter_ticks _CPU_Counter_difference(<br>
> - CPU_Counter_ticks second,<br>
> - CPU_Counter_ticks first<br>
> -)<br>
> -{<br>
> - return second - first;<br>
> -}<br>
> -<br>
> -#ifdef __cplusplus<br>
> -}<br>
> -#endif<br>
> -<br>
> -#endif<br>
> diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h<br>
> deleted file mode 100644<br>
> index ac6aac4..0000000<br>
> --- a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h<br>
> +++ /dev/null<br>
> @@ -1,72 +0,0 @@<br>
> -/**<br>
> - * @file<br>
> - *<br>
> - * @brief Intel M32R Assembly File<br>
> - *<br>
> - * Very loose template for an include file for the cpu_asm.? file<br>
> - * if it is implemented as a ".S" file (preprocessed by cpp) instead<br>
> - * of a ".s" file (preprocessed by gm4 or gasp).<br>
> - */<br>
> -<br>
> -/*<br>
> - * COPYRIGHT (c) 1989-1999.<br>
> - * On-Line Applications Research Corporation (OAR).<br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - *<br>
> - */<br>
> -<br>
> -#ifndef _RTEMS_SCORE_CPU_ASM_H<br>
> -#define _RTEMS_SCORE_CPU_ASM_H<br>
> -<br>
> -/* pull in the generated offsets */<br>
> -<br>
> -#include <rtems/score/offsets.h><br>
> -<br>
> -/*<br>
> - * Hardware General Registers<br>
> - */<br>
> -<br>
> -/* put something here */<br>
> -<br>
> -/*<br>
> - * Hardware Floating Point Registers<br>
> - */<br>
> -<br>
> -/* put something here */<br>
> -<br>
> -/*<br>
> - * Hardware Control Registers<br>
> - */<br>
> -<br>
> -/* put something here */<br>
> -<br>
> -/*<br>
> - * Calling Convention<br>
> - */<br>
> -<br>
> -/* put something here */<br>
> -<br>
> -/*<br>
> - * Temporary registers<br>
> - */<br>
> -<br>
> -/* put something here */<br>
> -<br>
> -/*<br>
> - * Floating Point Registers - SW Conventions<br>
> - */<br>
> -<br>
> -/* put something here */<br>
> -<br>
> -/*<br>
> - * Temporary floating point registers<br>
> - */<br>
> -<br>
> -/* put something here */<br>
> -<br>
> -#endif<br>
> -<br>
> -/* end of file */<br>
> diff --git a/cpukit/score/cpu/m32r/rtems/score/cpuatomic.h b/cpukit/score/cpu/m32r/rtems/score/cpuatomic.h<br>
> deleted file mode 100644<br>
> index 598ee76..0000000<br>
> --- a/cpukit/score/cpu/m32r/rtems/score/cpuatomic.h<br>
> +++ /dev/null<br>
> @@ -1,14 +0,0 @@<br>
> -/*<br>
> - * COPYRIGHT (c) 2012-2013 Deng Hengyi.<br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - */<br>
> -<br>
> -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H<br>
> -#define _RTEMS_SCORE_ATOMIC_CPU_H<br>
> -<br>
> -#include <rtems/score/cpustdatomic.h><br>
> -<br>
> -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */<br>
> diff --git a/cpukit/score/cpu/m32r/rtems/score/m32r.h b/cpukit/score/cpu/m32r/rtems/score/m32r.h<br>
> deleted file mode 100644<br>
> index cd91134..0000000<br>
> --- a/cpukit/score/cpu/m32r/rtems/score/m32r.h<br>
> +++ /dev/null<br>
> @@ -1,70 +0,0 @@<br>
> -/**<br>
> - * @file<br>
> - *<br>
> - * @brief Set up Basic CPU Dependency Settings Based on Compiler Settings<br>
> - *<br>
> - * This file sets up basic CPU dependency settings based on<br>
> - * compiler settings. For example, it can determine if<br>
> - * floating point is available. This particular implementation<br>
> - * is specified to the NO CPU port.<br>
> - */<br>
> -<br>
> -/*<br>
> - * COPYRIGHT (c) 1989-1999.<br>
> - * On-Line Applications Research Corporation (OAR).<br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - */<br>
> -<br>
> -#ifndef _RTEMS_SCORE_NO_CPU_H<br>
> -#define _RTEMS_SCORE_NO_CPU_H<br>
> -<br>
> -#ifdef __cplusplus<br>
> -extern "C" {<br>
> -#endif<br>
> -<br>
> -/*<br>
> - * This file contains the information required to build<br>
> - * RTEMS for a particular member of the NO CPU family.<br>
> - * It does this by setting variables to indicate which<br>
> - * implementation dependent features are present in a particular<br>
> - * member of the family.<br>
> - *<br>
> - * This is a good place to list all the known CPU models<br>
> - * that this port supports and which RTEMS CPU model they correspond<br>
> - * to.<br>
> - */<br>
> -<br>
> -#if defined(rtems_multilib)<br>
> -/*<br>
> - * Figure out all CPU Model Feature Flags based upon compiler<br>
> - * predefines.<br>
> - */<br>
> -<br>
> -#define CPU_MODEL_NAME "rtems_multilib"<br>
> -#define NOCPU_HAS_FPU 1<br>
> -<br>
> -#elif defined(__m32r__)<br>
> -<br>
> -#define CPU_MODEL_NAME "m32r"<br>
> -#define NOCPU_HAS_FPU 1<br>
> -<br>
> -#else<br>
> -<br>
> -#error "Unsupported CPU Model"<br>
> -<br>
> -#endif<br>
> -<br>
> -/*<br>
> - * Define the name of the CPU family.<br>
> - */<br>
> -<br>
> -#define CPU_NAME "NO CPU"<br>
> -<br>
> -#ifdef __cplusplus<br>
> -}<br>
> -#endif<br>
> -<br>
> -#endif /* _RTEMS_SCORE_NO_CPU_H */<br>
> diff --git a/cpukit/score/cpu/m32r/rtems/score/types.h b/cpukit/score/cpu/m32r/rtems/score/types.h<br>
> deleted file mode 100644<br>
> index 3ee57f2..0000000<br>
> --- a/cpukit/score/cpu/m32r/rtems/score/types.h<br>
> +++ /dev/null<br>
> @@ -1,52 +0,0 @@<br>
> -/**<br>
> - * @file<br>
> - *<br>
> - * @brief Intel M32R CPU Type Definitions<br>
> - *<br>
> - * This include file contains type definitions pertaining to the Intel<br>
> - * m32r processor family.<br>
> - */<br>
> -<br>
> -/*<br>
> - * COPYRIGHT (c) 1989-2006.<br>
> - * On-Line Applications Research Corporation (OAR).<br>
> - *<br>
> - * The license and distribution terms for this file may be<br>
> - * found in the file LICENSE in this distribution or at<br>
> - * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
> - */<br>
> -<br>
> -#ifndef _RTEMS_SCORE_TYPES_H<br>
> -#define _RTEMS_SCORE_TYPES_H<br>
> -<br>
> -#include <rtems/score/basedefs.h><br>
> -<br>
> -#ifndef ASM<br>
> -<br>
> -#ifdef __cplusplus<br>
> -extern "C" {<br>
> -#endif<br>
> -<br>
> -/*<br>
> - * This section defines the basic types for this processor.<br>
> - */<br>
> -<br>
> -/** Type that can store a 32-bit integer or a pointer. */<br>
> -typedef uintptr_t CPU_Uint32ptr;<br>
> -<br>
> -/** This defines the type for a priority bit map entry. */<br>
> -typedef uint16_t Priority_bit_map_Word;<br>
> -<br>
> -/** This defines the return type for an ISR entry point. */<br>
> -typedef void m32r_isr;<br>
> -<br>
> -/** This defines the prototype for an ISR entry point. */<br>
> -typedef m32r_isr ( *m32r_isr_entry )( void );<br>
> -<br>
> -#ifdef __cplusplus<br>
> -}<br>
> -#endif<br>
> -<br>
> -#endif /* !ASM */<br>
> -<br>
> -#endif<br>
> diff --git a/cpukit/score/src/threadglobalconstruction.c b/cpukit/score/src/threadglobalconstruction.c<br>
> index 05a8613..c7c10d9 100644<br>
> --- a/cpukit/score/src/threadglobalconstruction.c<br>
> +++ b/cpukit/score/src/threadglobalconstruction.c<br>
> @@ -28,9 +28,7 @@<br>
> * initialization this target and compiler version uses.<br>
> */<br>
> #if defined(__USE_INIT_FINI__)<br>
> - #if defined(__M32R__)<br>
> - #define INIT_NAME __init<br>
> - #elif defined(__ARM_EABI__)<br>
> + #if defined(__ARM_EABI__)<br>
> #define INIT_NAME __libc_init_array<br>
> #else<br>
> #define INIT_NAME _init<br>
> diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am<br>
> index 06ebf48..f27cc6a 100644<br>
> --- a/doc/cpu_supplement/Makefile.am<br>
> +++ b/doc/cpu_supplement/Makefile.am<br>
> @@ -1,5 +1,5 @@<br>
> #<br>
> -# COPYRIGHT (c) 1988-2012.<br>
> +# COPYRIGHT (c) 1988-2015.<br>
> # On-Line Applications Research Corporation (OAR).<br>
> # All rights reserved.<br>
><br>
> @@ -20,7 +20,6 @@ GENERATED_FILES += h8300.texi<br>
> GENERATED_FILES += i386.texi<br>
> GENERATED_FILES += lm32.texi<br>
> GENERATED_FILES += m32c.texi<br>
> -GENERATED_FILES += m32r.texi<br>
> GENERATED_FILES += m68k.texi<br>
> GENERATED_FILES += microblaze.texi<br>
> GENERATED_FILES += mips.texi<br>
> @@ -83,11 +82,6 @@ m32c.texi: m32c.t<br>
> -u "Top" \<br>
> -n "" < $< > $@<br>
><br>
> -m32r.texi: m32r.t<br>
> - $(BMENU2) -p "" \<br>
> - -u "Top" \<br>
> - -n "" < $< > $@<br>
> -<br>
> lm32.texi: lm32.t<br>
> $(BMENU2) -p "" \<br>
> -u "Top" \<br>
> diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi<br>
> index 105a54e..2fcdfa0 100644<br>
> --- a/doc/cpu_supplement/cpu_supplement.texi<br>
> +++ b/doc/cpu_supplement/cpu_supplement.texi<br>
> @@ -70,7 +70,6 @@<br>
> * Intel/AMD x86 Specific Information::<br>
> * Lattice Mico32 Specific Information::<br>
> * Renesas M32C Specific Information::<br>
> -* Renesas M32R Specific Information::<br>
> * M68xxx and Coldfire Specific Information::<br>
> * Xilinx MicroBlaze Specific Information::<br>
> * MIPS Specific Information::<br>
> @@ -95,7 +94,6 @@<br>
> @include i386.texi<br>
> @include lm32.texi<br>
> @include m32c.texi<br>
> -@include m32r.texi<br>
> @include m68k.texi<br>
> @include microblaze.texi<br>
> @include mips.texi<br>
> diff --git a/doc/cpu_supplement/m32r.t b/doc/cpu_supplement/m32r.t<br>
> deleted file mode 100644<br>
> index 951bf94..0000000<br>
> --- a/doc/cpu_supplement/m32r.t<br>
> +++ /dev/null<br>
> @@ -1,11 +0,0 @@<br>
> -@c Copyright (c) 2014 embedded brains GmbH. All rights reserved.<br>
> -<br>
> -@chapter Renesas M32R Specific Information<br>
> -<br>
> -@section Symmetric Multiprocessing<br>
> -<br>
> -SMP is not supported.<br>
> -<br>
> -@section Thread-Local Storage<br>
> -<br>
> -Thread-local storage is not implemented.<br>
> diff --git a/doc/user/preface.texi b/doc/user/preface.texi<br>
> index e47f18e..f8c0728 100644<br>
> --- a/doc/user/preface.texi<br>
> +++ b/doc/user/preface.texi<br>
> @@ -1,5 +1,5 @@<br>
> @c<br>
> -@c COPYRIGHT (c) 1989-2011.<br>
> +@c COPYRIGHT (c) 1989-2015.<br>
> @c On-Line Applications Research Corporation (OAR).<br>
> @c All rights reserved.<br>
><br>
> @@ -161,7 +161,6 @@ It has been ported to the following processor families:<br>
> @item Renesas (formerly Hitachi) SuperH<br>
> @item Renesas (formerly Hitachi) H8/300<br>
> @item Renesas M32C<br>
> -@item Renesas M32R<br>
> @item SPARC v7, v8, and V9<br>
> @end itemize<br>
><br>
> diff --git a/testsuites/libtests/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a> b/testsuites/libtests/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
> index a34bbb2..4941c51 100644<br>
> --- a/testsuites/libtests/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
> +++ b/testsuites/libtests/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
> @@ -48,8 +48,7 @@ AM_CONDITIONAL(HAS_POSIX,test x"${rtems_cv_RTEMS_POSIX_API}" = x"yes")<br>
> # Must match the list in cpukit.<br>
> AC_MSG_CHECKING([whether CPU supports libdl])<br>
> case $RTEMS_CPU in<br>
> - arm | i386 | m32r | m68k | mips | \<br>
> - moxie | powerpc | sparc)<br>
> + arm | i386 | m68k | mips | moxie | powerpc | sparc)<br>
> TEST_LIBDL=yes ;;<br>
> # bfin has an issue to resolve with libdl. See ticket #2252<br>
> bfin)<br>
> --<br>
> 1.7.1<br>
><br>
> _______________________________________________<br>
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> <a href="mailto:devel@rtems.org">devel@rtems.org</a><br>
> <a href="http://lists.rtems.org/mailman/listinfo/devel" rel="noreferrer" target="_blank">http://lists.rtems.org/mailman/listinfo/devel</a><br>
</div></div></blockquote></div><br></div></div>