<div dir="ltr">Hi Punit,<div><br></div><div>Great to see PWM driver working....</div><div><br></div><div><div>Besides Martin has suggested, I would like to add few points.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On 21 June 2016 at 21:56, Punit Vara <span dir="ltr"><<a href="mailto:punitvara@gmail.com" target="_blank">punitvara@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"> This patch adds required definitions, registers definitions and testsuit to<br>
test pwm driver for beagle bone black.<br>
---<br>
c/src/lib/libbsp/arm/beagle/Makefile.am | 3 +<br>
c/src/lib/libbsp/arm/beagle/pwm/bbb-pwm.c | 345 ++++++++++++++++++++++++++<br>
c/src/lib/libbsp/shared/include/gpio.h | 11 +<br>
c/src/lib/libcpu/arm/shared/include/am335x.h | 349 ++++++++++++++++++++++++++-<br>
testsuites/samples/Makefile.am | 2 +-<br>
testsuites/samples/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a> | 1 +<br>
testsuites/samples/pwm/Makefile.am | 19 ++<br>
testsuites/samples/pwm/init.c | 70 ++++++<br>
testsuites/samples/pwm/pwm.doc | 9 +<br>
testsuites/samples/pwm/pwm.scn | 3 +<br>
10 files changed, 810 insertions(+), 2 deletions(-)<br>
create mode 100644 c/src/lib/libbsp/arm/beagle/pwm/bbb-pwm.c<br>
create mode 100644 testsuites/samples/pwm/Makefile.am<br>
create mode 100644 testsuites/samples/pwm/init.c<br>
create mode 100644 testsuites/samples/pwm/pwm.doc<br>
create mode 100644 testsuites/samples/pwm/pwm.scn<br>
<br>
diff --git a/c/src/lib/libbsp/arm/beagle/Makefile.am b/c/src/lib/libbsp/arm/beagle/Makefile.am<br>
index 20d3092..68bdbd4 100644<br>
--- a/c/src/lib/libbsp/arm/beagle/Makefile.am<br>
+++ b/c/src/lib/libbsp/arm/beagle/Makefile.am<br>
@@ -117,6 +117,9 @@ libbsp_a_SOURCES += misc/i2c.c<br>
# GPIO<br>
libbsp_a_SOURCES += gpio/bbb-gpio.c<br>
<br>
+#pwm<br>
+libbsp_a_SOURCES += pwm/bbb-pwm.c<br>
+<br>
#RTC<br>
libbsp_a_SOURCES += rtc.c<br>
libbsp_a_SOURCES += ../../shared/tod.c<br>
diff --git a/c/src/lib/libbsp/arm/beagle/pwm/bbb-pwm.c b/c/src/lib/libbsp/arm/beagle/pwm/bbb-pwm.c<br>
new file mode 100644<br>
index 0000000..a2f1107<br>
--- /dev/null<br>
+++ b/c/src/lib/libbsp/arm/beagle/pwm/bbb-pwm.c<br>
@@ -0,0 +1,345 @@<br>
+/* This file is based on following licence<br>
+ * Copyright (c) 2015, Shabaz, VegetableAvenger<br>
+ * Copyright (c) 2016, Punit Vara<br>
+ * Added clock functions and improved pwm_enable function<br>
+ * All rights reserved.<br>
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions are met:<br>
+ *<br>
+ * Redistributions of source code must retain the above copyright notice, this<br>
+ * list of conditions and the following disclaimer.<br>
+<br>
+ * Redistributions in binary form must reproduce the above copyright notice,<br>
+ * this list of conditions and the following disclaimer in the documentation<br>
+ * and/or other materials provided with the distribution.<br>
+ *<br>
+ * Neither the name of BBBIOlib nor the names of its<br>
+ * contributors may be used to endorse or promote products derived from<br>
+ * this software without specific prior written permission.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE<br>
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE<br>
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL<br>
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR<br>
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER<br>
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,<br>
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE<br>
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+#include<libcpu/am335x.h><br>
+#include<stdio.h><br>
+#include<bsp/gpio.h><br>
+#include<bsp/bbb-gpio.h><br>
+#include<bsp.h><br>
+<br>
+#define BASE_CLOCK 100000000<br>
+/**<br>
+ * @brief This function intilize clock and pinmuxing for pwm sub system.<br>
+ *<br>
+ * @param PWMSS_ID It is the instance number of EPWM of pwm sub system.<br>
+ **/<br>
+void pwm_init(unsigned int baseAddr, unsigned int PWMSS_ID)<br>
+{<br>
+ module_clk_config(PWMSS_ID);<br>
+ EPWMPinMuxSetup();<br>
+ EPWM_clock_enable(baseAddr);<br>
+ pwmss_tbclk_enable(PWMSS_ID);<br>
+<br>
+}<br>
+<br>
+<br>
+/**<br>
+ * \brief This function Enables TBCLK(Time Base Clock) for specific<br>
+ * EPWM instance of pwmsubsystem.<br>
+ *<br>
+ * \param instance It is the instance number of EPWM of pwmsubsystem.<br>
+ *<br>
+ **/<br>
+void pwmss_tbclk_enable(unsigned int instance)<br>
+{<br>
+ switch(instance)<br>
+ {<br>
+<br>
+ case 0:<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_PWMSS_CTRL) |=<br>
+ BBBIO_PWMSS_CTRL_PWMSS0_TBCLKEN;<br>
+ break;<br>
+<br>
+ case 1:<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_PWMSS_CTRL) |=<br>
+ BBBIO_PWMSS_CTRL_PWMSS1_TBCLKEN;<br>
+ break;<br>
+<br>
+ case 2:<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_PWMSS_CTRL) |=<br>
+ BBBIO_PWMSS_CTRL_PWMSS2_TBCLKEN;<br>
+ break;<br>
+<br>
+ default:<br>
+ break;<br>
+ }<br>
+}<br>
+<br>
+/**<br>
+ * \brief This function Enables pinmuxing for PWM module.<br>
+ *<br>
+ *<br>
+ * \param instance It is the instance number of EPWM of pwmsubsystem.<br>
+ *<br>
+ **/<br>
+<br>
+<br>
+<br>
+void EPWMPinMuxSetup(void)<br>
+{<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_CONF_GPMC_AD(9)) = BBB_MUXMODE(4);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_CONF_GPMC_AD(8)) = BBB_MUXMODE(4);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_CONF_LCD_DATA(0)) = BBB_MUXMODE(3);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_CONF_LCD_DATA(1)) = BBB_MUXMODE(3);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_CONF_LCD_DATA(11)) = BBB_MUXMODE(2);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_CONF_LCD_DATA(10)) = BBB_MUXMODE(2);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_CONF_GPMC_AD(2)) = BBB_MUXMODE(6);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + CONTROL_CONF_GPMC_AD(3)) = BBB_MUXMODE(6);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_D0) = BBB_MUXMODE(3);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_SCLK) = BBB_MUXMODE(3);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_FSX) = BBB_MUXMODE(1);<br>
+<br>
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_ACLKX) = BBB_MUXMODE(1);<br>
+}<br>
+<br>
+<br>
+<br>
+<br>
+/**<br>
+ * \brief This functions enables clock for EHRPWM module in PWMSS subsystem.<br>
+ *<br>
+ * \param baseAdd It is the Memory address of the PWMSS instance used.<br>
+ *<br>
+ * \return None.<br>
+ *<br>
+ **/<br>
+<br>
+void EPWM_clock_enable(unsigned int baseAdd)<br>
+{<br>
+ REG(baseAdd + PWMSS_CLKCONFIG) |= PWMSS_CLK_EN_ACK;<br>
+}<br>
+<br>
+<br>
+/**<br>
+ * \brief This function configures the L3 and L4_PER system clocks.<br>
+ * It also configures the system clocks for the specified ePWMSS<br>
+ * instance.<br>
+ *<br>
+ * \param instanceNum The instance number of ePWMSS whose system clocks<br>
+ * have to be configured.<br>
+ *<br>
+ * 'instanceNum' can take one of the following values:<br>
+ * (0 <= instanceNum <= 2)<br>
+ *<br>
+ * \return None.<br>
+ *<br>
+ */<br>
+void module_clk_config(unsigned int instanceNum)<br>
+{<br>
+ if(0 == instanceNum)<br>
+ {<br>
+ REG(BBBIO_CM_PER_ADDR + CM_PER_EPWMSS0_CLKCTRL) |=<br>
+ CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE;<br>
+<br>
+<br>
+ }<br>
+ else if(1 == instanceNum)<br>
+ {<br>
+ REG(BBBIO_CM_PER_ADDR + CM_PER_EPWMSS1_CLKCTRL) |=<br>
+ CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE;<br>
+<br>
+ }<br>
+ else if(2 == instanceNum)<br>
+ {<br>
+ REG(BBBIO_CM_PER_ADDR + CM_PER_EPWMSS2_CLKCTRL) |=<br>
+ CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE;<br>
+<br>
+ }<br>
+ else<br>
+ {<br>
+<br>
+ }<br>
+}<br>
+<br>
+<br>
+/**<br>
+ * \brief This API enables the particular PWM module.<br>
+ *<br>
+ * \param baseAddr Base Address of the PWM Module Registers.<br>
+ *<br>
+ * \return None<br>
+ *<br>
+ **/<br>
+void ehrPWM_Enable(unsigned int baseAddr)<br>
+{<br>
+ REG16(baseAddr + EHRPWM_AQCTLA) = 0x2 | (0x3 << 4);<br>
+ REG16(baseAddr + EHRPWM_AQCTLB) = 0x2 | (0x3 << 8);<br>
+ REG16(baseAddr + EHRPWM_TBCNT) = 0;<br>
+ REG16(baseAddr + EHRPWM_TBCTL) |= TBCTL_FREERUN | TBCTL_CTRMODE_UP;<br>
+}<br>
+<br>
+/**<br>
+ * \brief This API disables the HR sub-module.<br>
+ *<br>
+ * \param baseAddr Base Address of the PWM Module Registers.<br>
+ *<br>
+ * \return None<br>
+ *<br>
+ **/<br>
+<br>
+void ehrPWM_Disable(unsigned int baseAddr)<br>
+{<br>
+<br>
+ REG16(baseAddr + EHRPWM_TBCTL) = 0x3;<br>
+ REG16(baseAddr + EHRPWM_AQCTLA) = 0x1 | ( 0x3 << 4 );<br>
+ REG16(baseAddr + EHRPWM_AQCTLB) = 0x1 | ( 0x3 << 8 );<br>
+ REG16(baseAddr + EHRPWM_TBCNT) = 0;<br>
+}<br>
+<br>
+/* PWMSS setting<br>
+ * set pulse argument of epwm module<br>
+ *<br>
+ * @param PWMID : EPWMSS number , 0~2<br>
+ * @param HZ : pulse HZ<br>
+ * @param dutyA : Duty Cycle in ePWM A<br>
+ * @param dutyB : Duty Cycle in ePWM B<br>
+ *<br>
+ * @return : 1 for success , 0 for failed<br>
+ *<br>
+ * @example : PWMSS_Setting(0 , 50.0f , 50.0f , 25.0f); // Generate 50HZ pwm in PWM0 ,<br>
+ * // duty cycle is 50% for ePWM0A , 25% for ePWM0B<br>
+ *<br>
+ * @Note :<br>
+ * find an number nearst 65535 for TBPRD , to improve duty precision,<br>
+ *<br>
+ * Using big TBPRD can increase the range of CMPA and CMPB ,<br>
+ * and it means we can get better precision on duty cycle.<br>
+ *<br>
+ * EX : 20.25% duty cycle<br>
+ * on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500)<br>
+ * on TBPRD = 6250 , CMPA = 1265.625 ( .625 rejection), real duty : 20.24% (1265 6250)<br>
+ * on TBPRD = 500 , CMPA = 101.25 ( .25 rejection) , real duty : 20.2% (101/500)<br>
+ *<br>
+ * Divisor = CLKDIV * HSPCLKDIV<br>
+ * 1 TBPRD : 10 ns (default)<br>
+ * 65535 TBPRD : 655350 ns<br>
+ * 65535 TBPRD : 655350 * Divisor ns = X TBPRD : Cyclens<br>
+ *<br>
+ * accrooding to that , we must find a Divisor value , let X nearest 65535 .<br>
+ * so , Divisor must Nearest Cyclens/655350<br>
+ */<br>
+<br>
+int PWMSS_Setting(unsigned int baseAddr, float HZ, float dutyA, float dutyB)<br>
+{<br>
+ unsigned int z,p,y;<br>
+ int param_error =1;<br>
+ if(HZ < 0)<br>
+ param_error =0;<br>
+ if(dutyA < 0.0f || dutyA > 100.0f || dutyB < 0.0f || dutyB > 100.0f)<br>
+ param_error = 0;<br>
+ if(param_error == 0) {<br>
+ printf("ERROR in parameter \n");<br>
+ }<br>
+ dutyA /= 100.0f;<br>
+ dutyB /= 100.0f;<br>
+<br>
+ /*Compute necessary TBPRD*/<br>
+ float Cyclens = 0.0f;<br>
+ float Divisor =0;<br>
+ int i,j;<br>
+ const float CLKDIV_div[] = {1.0,2.0,4.0,8.0,16.0,32.0,64.0,128.0};<br>
+ const float HSPCLKDIV_div[] = {1.0, 2.0, 4.0, 6.0, 8.0, 10.0,12.0, 14.0};<br>
+ int NearCLKDIV =7;<br>
+ int NearHSPCLKDIV =7;<br>
+ int NearTBPRD =0;<br>
+<br>
+ Cyclens = 1000000000.0f / HZ; /** 10^9 /Hz compute time per cycle (ns)<br>
+ */<br>
+ Divisor = (Cyclens / 655350.0f); /** am335x provide (128* 14) divider,<br>
+ * and per TBPRD means 10ns when divider<br>
+ * and max TBPRD is 65535 so max cycle<br>
+ * is 128 * 8 * 14 * 65535 * 10ns<br>
+ */<br>
+ if(Divisor > (128 * 14)) {<br>
+ printf("Can't generate %f HZ",HZ);<br>
+ return 0;<br>
+ }<br>
+ else {<br>
+ for (i=0;i<8;i++) {<br>
+ for(j=0 ; j<8; j++) {<br>
+ if((CLKDIV_div[i] * HSPCLKDIV_div[j]) < (CLKDIV_div[NearCLKDIV]<br>
+ * HSPCLKDIV_div[NearHSPCLKDIV]) && (CLKDIV_div[i] * HSPCLKDIV_div[j] > Divisor)) {<br>
+ NearCLKDIV = i;<br>
+ NearHSPCLKDIV = j;<br>
+ }<br>
+ }<br>
+ }<br>
+ printf("BBBIO CLKDIV = %d and HSPCLKDIV = %d\n",NearCLKDIV,NearHSPCLKDIV);<br>
+<br>
+ REG16(baseAddr + EHRPWM_TBCTL) &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);<br>
+<br>
+ REG16(baseAddr + EHRPWM_TBCTL) = (REG16(baseAddr + EHRPWM_TBCTL) &<br>
+ (~EHRPWM_TBCTL_CLKDIV)) | ((NearCLKDIV << TBCTL_CLKDIV_SHIFT) & EHRPWM_TBCTL_CLKDIV);<br>
+<br>
+ REG16(baseAddr + EHRPWM_TBCTL) = (REG16(baseAddr + EHRPWM_TBCTL) &<br>
+ (~EHRPWM_TBCTL_HSPCLKDIV)) | ((NearHSPCLKDIV <<<br>
+ TBCTL_HSPCLKDIV_SHIFT) & EHRPWM_TBCTL_HSPCLKDIV);<br>
+<br>
+ NearTBPRD = (Cyclens / (10.0 * CLKDIV_div[NearCLKDIV] * HSPCLKDIV_div[NearHSPCLKDIV]));<br>
+<br>
+ REG16(baseAddr + EHRPWM_TBCTL) = (REG16(baseAddr + EHRPWM_TBCTL) &<br>
+ (~EHRPWM_PRD_LOAD_SHADOW_MASK)) | (((bool)EHRPWM_SHADOW_WRITE_DISABLE <<<br>
+ EHRPWM_TBCTL_PRDLD_SHIFT) & EHRPWM_PRD_LOAD_SHADOW_MASK);<br>
+<br>
+ REG16(baseAddr + EHRPWM_TBCTL) = (REG16(baseAddr + EHRPWM_TBCTL) &<br>
+ (~EHRPWM_COUNTER_MODE_MASK)) | (((unsigned int)EHRPWM_COUNT_UP <<<br>
+ EHRPWM_TBCTL_CTRMODE_SHIFT) & EHRPWM_COUNTER_MODE_MASK);<br>
+<br>
+ printf("writing TBPRD = %x \n",NearTBPRD);<br>
+ /*setting clock divider and freeze time base*/<br>
+ // configure_tbclk(baseAddr, HZ);<br>
+ REG16(baseAddr + EHRPWM_CMPB) = (unsigned short)((float)(NearTBPRD) * dutyB);<br>
+ z = REG16(baseAddr + EHRPWM_CMPB);<br>
+ printk("read CMPB = %x\t",z);<br>
+ REG16(baseAddr + EHRPWM_CMPA) = (unsigned short)((float)(NearTBPRD) * dutyA);<br>
+ p = REG16(baseAddr + EHRPWM_CMPA);<br>
+ printk("read CMPA = %x\n",p);<br>
+ REG16(baseAddr + EHRPWM_TBPRD) = (unsigned short)NearTBPRD;<br>
+ y = REG16(baseAddr + EHRPWM_TBPRD);<br>
+ printk("TBPRD read = %x \n",y);<br>
+ REG16(baseAddr + EHRPWM_TBCNT) = 0;<br>
+ printf("\nfinished setting \n");<br>
+ }<br>
+ return 1;<br>
+}<br>
+<br>
+int PWMSS_TB_clock_check(unsigned int PWMSS_ID)<br>
+{<br>
+ unsigned int reg_value,value;<br>
+<br>
+ /*control module check*/<br>
+ reg_value = REG(BBBIO_CONTROL_MODULE + BBBIO_PWMSS_CTRL);<br>
+<br>
+ value = reg_value & (1 << PWMSS_ID);<br>
+ printf("\n PWMSS_CTRL = %d and reg_value = %d \n",value,reg_value);<br>
+ return (reg_value & (1 << PWMSS_ID));<br>
+}<br>
diff --git a/c/src/lib/libbsp/shared/include/gpio.h b/c/src/lib/libbsp/shared/include/gpio.h<br>
index 7d8f67b..2a89f1d 100644<br>
--- a/c/src/lib/libbsp/shared/include/gpio.h<br>
+++ b/c/src/lib/libbsp/shared/include/gpio.h<br>
@@ -947,6 +947,17 @@ extern rtems_status_code rtems_gpio_bsp_disable_interrupt(<br>
<br>
/** @} */<br>
<br>
+extern void pwmss_tbclk_enable(unsigned int instance);<br>
+extern void EPWM_clock_enable(unsigned int baseAdd);<br>
+extern void module_clk_config(unsigned int instanceNum);<br>
+extern void EPWMPinMuxSetup(void);<br>
+extern int PWMSS_Setting(unsigned int baseAddr, float HZ, float dutyA, float dutyB);<br>
+extern void ehrPWM_Disable(unsigned int baseAddr);<br>
+extern void ehrPWM_Enable(unsigned int baseAddr);<br>
+extern int PWMSS_TB_clock_check(unsigned int PWMSS_ID);<br>
+extern void pwm_init(unsigned int baseAddr, unsigned int PWMSS_ID);<br>
+<br>
+<br>
#ifdef __cplusplus<br>
}<br>
#endif /* __cplusplus */<br>
diff --git a/c/src/lib/libcpu/arm/shared/include/am335x.h b/c/src/lib/libcpu/arm/shared/include/am335x.h<br>
index 2009cef..b89a188 100644<br>
--- a/c/src/lib/libcpu/arm/shared/include/am335x.h<br>
+++ b/c/src/lib/libcpu/arm/shared/include/am335x.h<br>
@@ -467,4 +467,351 @@<br>
#define AM335X_CONF_EXT_WAKEUP 0xA00<br>
#define AM335X_CONF_RTC_KALDO_ENN 0xA04<br>
#define AM335X_CONF_USB0_DRVVBUS 0xA1C<br>
-#define AM335X_CONF_USB1_DRVVBUS 0xA34<br>
\ No newline at end of file<br>
+#define AM335X_CONF_USB1_DRVVBUS 0xA34<br>
+<br>
+/* Added by punit vara<br>
+<br>
+ PWMSS register definitions */<br>
+<br>
+#define PWMSS_CLOCK_CONFIG 0x08<br>
+<br></blockquote><div>Remove these kind of white spaces .... </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">
+#define PWMSS_CLOCK_STATUS 0x0C<br>
+<br></blockquote><div>For processor specific macros you can follow the convention like </div><div><span style="color:rgb(121,93,163);font-family:Consolas,"Liberation Mono",Menlo,Courier,monospace;font-size:12px;line-height:16.8px;white-space:pre-wrap">AM335X_GPIO0_BASE</span></div><div><span style="color:rgb(121,93,163);font-family:Consolas,"Liberation Mono",Menlo,Courier,monospace;font-size:12px;line-height:16.8px;white-space:pre-wrap"><br></span></div><div>This would be more convenient to developer for debugging/developing purpose.</div><div>Kindly follow the same whenever you define macros to processor specific file. </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">
+#define PWMSS_ECAP_CLK_EN_ACK_SHIFT 0x00<br>
+<br>
+#define PWMSS_ECAP_CLK_STOP_ACK_SHIFT 0x01<br>
+<br>
+#define PWMSS_EHRPWM_CLK_EN_ACK_SHIFT 0x08<br>
+<br>
+#define PWMSS_EHRPWM_CLK_STOP_ACK_SHIFT 0x09<br>
+<br>
+#define PWMSS_ECAP_CLK_EN_ACK 0x01<br>
+<br>
+#define PWMSS_ECAP_CLK_STOP_ACK 0x02<br>
+<br>
+#define PWMSS_EHRPWM_CLK_EN_ACK 0x100<br>
+<br>
+#define PWMSS_EHRPWM_CLK_STOP_ACK 0x200<br>
+<br></blockquote><div>Also try to follow standard conventions along with proper indentation. </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">
+/** @brief Base addresses of PWMSS memory mapped registers. */<br>
+<br>
+#define SOC_PWMSS0_REGS (0x48300000)<br>
+#define SOC_PWMSS1_REGS (0x48302000)<br>
+#define SOC_PWMSS2_REGS (0x48304000)<br>
+<br>
+#define SOC_ECAP_REGS (0x00000100)<br>
+#define SOC_EQEP_REGS (0x00000180)<br>
+#define SOC_EPWM_REGS (0x00000200)<br>
+#define SOC_ECAP_0_REGS (SOC_PWMSS0_REGS + SOC_ECAP_REGS)<br>
+#define SOC_ECAP_1_REGS (SOC_PWMSS1_REGS + SOC_ECAP_REGS)<br>
+#define SOC_ECAP_2_REGS (SOC_PWMSS2_REGS + SOC_ECAP_REGS)<br>
+<br>
+#define SOC_EQEP_0_REGS (SOC_PWMSS0_REGS + SOC_EQEP_REGS)<br>
+#define SOC_EQEP_1_REGS (SOC_PWMSS1_REGS + SOC_EQEP_REGS)<br>
+#define SOC_EQEP_2_REGS (SOC_PWMSS2_REGS + SOC_EQEP_REGS)<br>
+<br>
+#define SOC_EPWM_0_REGS (SOC_PWMSS0_REGS + SOC_EPWM_REGS)<br>
+#define SOC_EPWM_1_REGS (SOC_PWMSS1_REGS + SOC_EPWM_REGS)<br>
+#define SOC_EPWM_2_REGS (SOC_PWMSS2_REGS + SOC_EPWM_REGS)<br>
+<br>
+#define CONTROL_PWMSS_CTRL (0x664)<br>
+#define CONTROL_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u)<br>
+#define CONTROL_PWMSS_CTRL_PWMMS1_TBCLKEN (0x00000002u)<br>
+#define CONTROL_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u)<br>
+#define SOC_PRCM_REGS (0x44E00000)<br>
+#define CM_PER_EPWMSS0_CLKCTRL (0xd4)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE (0x2u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC (0x0u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST (0x00030000u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL (0xcc)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE (0x2u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE (0x00000003u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC (0x0u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST (0x00030000u)<br>
+<br>
+/* TBCTL */<br></blockquote><div>This comment could be more descriptive . </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">
+<br>
+#define EHRPWM_TBCTL_FREE_SOFT (0xC000u)<br>
+#define EHRPWM_TBCTL_FREE_SOFT_SHIFT (0x000Eu)<br>
+<br>
+#define EHRPWM_TBCTL_PHSDIR (0x2000u)<br>
+#define EHRPWM_TBCTL_PHSDIR_SHIFT (0x000Du)<br>
+#define EHRPWM_TBCTL_CLKDIV (0x1C00u)<br>
+#define EHRPWM_TBCTL_CLKDIV_SHIFT (0x000Au)<br>
+#define EHRPWM_TBCTL_CLKDIV_DIVBY1 (0x0000u)<br>
+#define EHRPWM_TBCTL_CLKDIV_DIVBY2 (0x0001u)<br>
+#define EHRPWM_TBCTL_CLKDIV_DIVBY4 (0x0002u)<br>
+#define EHRPWM_TBCTL_CLKDIV_DIVBY8 (0x0003u)<br>
+#define EHRPWM_TBCTL_CLKDIV_DIVBY16 (0x0004u)<br>
+#define EHRPWM_TBCTL_CLKDIV_DIVBY32 (0x0005u)<br>
+#define EHRPWM_TBCTL_CLKDIV_DIVBY64 (0x0006u)<br>
+#define EHRPWM_TBCTL_CLKDIV_DIVBY128 (0x0007u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV (0x0380u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_SHIFT (0x0007u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_DIVBY1 (0x0000u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_DIVBY2 (0x0001u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_DIVBY4 (0x0002u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_DIVBY6 (0x0003u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_DIVBY8 (0x0004u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_DIVBY10 (0x0005u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_DIVBY12 (0x0006u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_DIVBY14 (0x0007u)<br>
+#define EHRPWM_TBCTL_SWFSYNC (0x0040u)<br>
+#define EHRPWM_TBCTL_SWFSYNC_SHIFT (0x0006u)<br>
+#define EHRPWM_TBCTL_SYNCOSEL (0x0030u)<br>
+#define EHRPWM_TBCTL_SYNCOSEL_SHIFT (0x0004u)<br>
+#define EHRPWM_TBCTL_SYNCOSEL_EPWMXSYNCI (0x0000u)<br>
+#define EHRPWM_TBCTL_SYNCOSEL_TBCTRZERO (0x0001u)<br>
+#define EHRPWM_TBCTL_SYNCOSEL_TBCTRCMPB (0x0002u)<br>
+#define EHRPWM_TBCTL_SYNCOSEL_DISABLE (0x0003u)<br>
+#define EHRPWM_TBCTL_PRDLD (0x0008u)<br>
+#define EHRPWM_TBCTL_PRDLD_SHIFT (0x0003u)<br>
+#define EHRPWM_TBCTL_PHSEN (0x0004u)<br>
+#define EHRPWM_TBCTL_PHSEN_SHIFT (0x0002u)<br>
+#define EHRPWM_TBCTL_CTRMODE (0x0003u)<br>
+#define EHRPWM_TBCTL_CTRMODE_SHIFT (0x0000u)<br>
+#define EHRPWM_TBCTL_CTRMODE_UP (0x0000u)<br>
+#define EHRPWM_TBCTL_CTRMODE_DOWN (0x0001u)<br>
+#define EHRPWM_TBCTL_CTRMODE_UPDOWN (0x0002u)<br>
+#define EHRPWM_TBCTL_CTRMODE_STOPFREEZE (0x0003u)<br>
+<br>
+/* TBPRD */<br>
+<br>
+#define EHRPWM_TBPRD_TBPRD (0xFFFFu)<br>
+#define EHRPWM_TBPRD_TBPRD_SHIFT (0x0000u)<br>
+<br>
+<br>
+/* CMPA */<br>
+<br>
+#define EHRPWM_CMPA_CMPA (0xFFFFu)<br>
+#define EHRPWM_CMPA_CMPA_SHIFT (0x0000u)<br>
+<br>
+<br>
+/* CMPB */<br></blockquote><div>Try to make all these comments as descriptive as possible. </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">
+<br>
+#define EHRPWM_CMPB_CMPB (0xFFFFu)<br>
+#define EHRPWM_CMPB_CMPB_SHIFT (0x0000u)<br>
+<br>
+/* REVID */ </blockquote><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">
+<br>
+#define EHRPWM_REVID_REV (0xFFFFFFFFu)<br>
+#define EHRPWM_REVID_REV_SHIFT (0x00000000u)<br>
+<br>
+#define EHRPWM_TBCTL (0x0)<br>
+#define EHRPWM_TBSTS (0x2)<br>
+#define EHRPWM_TBPHSHR (0x4)<br>
+#define EHRPWM_TBPHS (0x6)<br>
+#define EHRPWM_TBCTR (0x8)<br>
+#define EHRPWM_TBPRD (0xA)<br>
+#define EHRPWM_CMPCTL (0xE)<br>
+#define EHRPWM_CMPAHR (0x10)<br>
+#define EHRPWM_CMPA (0x12)<br>
+#define EHRPWM_CMPB (0x14)<br>
+#define EHRPWM_AQCTLA (0x16)<br>
+#define EHRPWM_AQCTLB (0x18)<br>
+#define EHRPWM_AQSFRC (0x1A)<br>
+#define EHRPWM_AQCSFRC (0x1C)<br>
+#define EHRPWM_DBCTL (0x1E)<br>
+#define EHRPWM_DBRED (0x20)<br>
+#define EHRPWM_DBFED (0x22)<br>
+#define EHRPWM_TZSEL (0x24)<br>
+#define EHRPWM_TZCTL (0x28)<br>
+#define EHRPWM_TZEINT (0x2A)<br>
+#define EHRPWM_TZFLG (0x2C)<br>
+#define EHRPWM_TZCLR (0x2E)<br>
+#define EHRPWM_TZFRC (0x30)<br>
+#define EHRPWM_ETSEL (0x32)<br>
+#define EHRPWM_ETPS (0x34)<br>
+#define EHRPWM_ETFLG (0x36)<br>
+#define EHRPWM_ETCLR (0x38)<br>
+#define EHRPWM_ETFRC (0x3A)<br>
+#define EHRPWM_PCCTL (0x3C)<br>
+#define EHRPWM_HRCNFG (0x1040)<br>
+<br>
+<br>
+/* TB Period load */<br>
+#define EHRPWM_PRD_LOAD_SHADOW_MASK EHRPWM_TBCTL_PRDLD<br>
+<br>
+/* Counter mode */<br>
+#define EHRPWM_COUNTER_MODE_MASK EHRPWM_TBCTL_CTRMODE<br>
+#define EHRPWM_COUNT_UP (EHRPWM_TBCTL_CTRMODE_UP << \<br>
+ EHRPWM_TBCTL_CTRMODE_SHIFT)<br>
+#define EHRPWM_COUNT_DOWN (EHRPWM_TBCTL_CTRMODE_DOWN << \<br>
+ EHRPWM_TBCTL_CTRMODE_SHIFT)<br>
+#define EHRPWM_COUNT_UP_DOWN (EHRPWM_TBCTL_CTRMODE_UPDOWN << \<br>
+ EHRPWM_TBCTL_CTRMODE_SHIFT)<br>
+#define EHRPWM_COUNT_STOP (EHRPWM_TBCTL_CTRMODE_STOPFREEZE << \<br>
+ EHRPWM_TBCTL_CTRMODE_SHIFT)<br>
+/* Synchronization */<br>
+#define EHRPWM_SYNC_ENABLE EHRPWM_TBCTL_PHSEN<br>
+//#define EHRPWM_SW_FORCED_SYNC 0x1<br>
+<br>
+#define EHRPWM_SYNCOUT_MASK EHRPWM_TBCTL_SYNCOSEL<br>
+#define EHRPWM_SYNCOUT_SYNCIN (EHRPWM_TBCTL_SYNCOSEL_EPWMXSYNCI << \<br>
+ EHRPWM_TBCTL_SYNCOSEL_SHIFT)<br>
+#define EHRPWM_SYNCOUT_COUNTER_EQUAL_ZERO (EHRPWM_TBCTL_SYNCOSEL_TBCTRZERO << \<br>
+ EHRPWM_TBCTL_SYNCOSEL_SHIFT)<br>
+#define EHRPWM_SYNCOUT_COUNTER_EQUAL_COMPAREB (EHRPWM_TBCTL_SYNCOSEL_TBCTRCMPB << \<br>
+ EHRPWM_TBCTL_SYNCOSEL_SHIFT)<br>
+#define EHRPWM_SYNCOUT_DISABLE (EHRPWM_TBCTL_SYNCOSEL_DISABLE << \<br>
+ EHRPWM_TBCTL_SYNCOSEL_SHIFT)<br>
+/* Shadow */<br>
+#define EHRPWM_SHADOW_WRITE_ENABLE 0x0<br>
+#define EHRPWM_SHADOW_WRITE_DISABLE 0x1<br>
+<br>
+/* Time base clock */<br>
+#define EHRPWM_TBCTL_CLKDIV_1 (0x0001u)<br>
+#define EHRPWM_TBCTL_CLKDIV_2 (0x0002u)<br>
+#define EHRPWM_TBCTL_CLKDIV_4 (0x0004u)<br>
+#define EHRPWM_TBCTL_CLKDIV_8 (0x0008u)<br>
+#define EHRPWM_TBCTL_CLKDIV_16 (0x0010u)<br>
+#define EHRPWM_TBCTL_CLKDIV_32 (0x0020u)<br>
+#define EHRPWM_TBCTL_CLKDIV_64 (0x0040u)<br>
+#define EHRPWM_TBCTL_CLKDIV_128 (0x0080u)<br>
+<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_1 (0x0001u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_2 (0x0002u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_4 (0x0004u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_6 (0x0006u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_8 (0x0008u)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_10 (0x000Au)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_12 (0x000Cu)<br>
+#define EHRPWM_TBCTL_HSPCLKDIV_14 (0x000Eu)<br>
+<br>
+/* Count direction after sync */<br>
+#define EHRPWM_COUNT_DOWN_AFTER_SYNC 0x0<br>
+#define EHRPWM_COUNT_UP_AFTER_SYNC 0x1<br>
+/* Counter Compare */<br>
+#define EHRPWM_SHADOW_A_EMPTY (0x0 << EHRPWM_CMPCTL_SHDWAFULL_SHIFT)<br>
+#define EHRPWM_SHADOW_A_FULL (EHRPWM_CMPCTL_SHDWAFULL)<br>
+#define EHRPWM_SHADOW_B_EMPTY (0x0 << EHRPWM_CMPCTL_SHDWBFULL_SHIFT)<br>
+#define EHRPWM_SHADOW_B_FULL (EHRPWM_CMPCTL_SHDWBFULL)<br>
+<br>
+#define EHRPWM_CMPCTL_NOT_OVERWR_SH_FL 0x0<br>
+#define EHRPWM_CMPCTL_OVERWR_SH_FL 0x1<br>
+<br>
+/* Compare register load */<br>
+#define EHRPWM_COMPB_LOAD_MASK EHRPWM_CMPCTL_LOADBMODE<br>
+#define EHRPWM_COMPB_LOAD_COUNT_EQUAL_ZERO (EHRPWM_CMPCTL_LOADBMODE_TBCTRZERO << \<br>
+ EHRPWM_CMPCTL_LOADBMODE_SHIFT)<br>
+#define EHRPWM_COMPB_LOAD_COUNT_EQUAL_PERIOD (EHRPWM_CMPCTL_LOADBMODE_TBCTRPRD << \<br>
+ EHRPWM_CMPCTL_LOADBMODE_SHIFT)<br>
+#define EHRPWM_COMPB_LOAD_COUNT_EQUAL_ZERO_OR_PERIOD \<br>
+ (EHRPWM_CMPCTL_LOADBMODE_ZEROORPRD << \<br>
+ EHRPWM_CMPCTL_LOADBMODE_SHIFT)<br>
+#define EHRPWM_COMPB_NO_LOAD (EHRPWM_CMPCTL_LOADBMODE_FREEZE << \<br>
+ EHRPWM_CMPCTL_LOADBMODE_SHIFT)<br>
+<br>
+<br>
+#define EHRPWM_COMPA_LOAD_MASK EHRPWM_CMPCTL_LOADAMODE<br>
+#define EHRPWM_COMPA_LOAD_COUNT_EQUAL_ZERO (EHRPWM_CMPCTL_LOADAMODE_TBCTRZERO << \<br>
+ EHRPWM_CMPCTL_LOADAMODE_SHIFT)<br>
+#define EHRPWM_COMPA_LOAD_COUNT_EQUAL_PERIOD (EHRPWM_CMPCTL_LOADAMODE_TBCTRPRD << \<br>
+ EHRPWM_CMPCTL_LOADAMODE_SHIFT)<br>
+#define EHRPWM_COMPA_LOAD_COUNT_EQUAL_ZERO_OR_PERIOD \<br>
+ (EHRPWM_CMPCTL_LOADAMODE_ZEROORPRD << \<br>
+ EHRPWM_CMPCTL_LOADAMODE_SHIFT)<br>
+#define EHRPWM_COMPA_NO_LOAD (EHRPWM_CMPCTL_LOADAMODE_FREEZE << \<br>
+ EHRPWM_CMPCTL_LOADAMODE_SHIFT)<br>
+<br>
+#define CM_PER_EPWMSS1_CLKCTRL (0xcc)<br>
+#define CM_PER_EPWMSS0_CLKCTRL (0xd4)<br>
+#define CM_PER_EPWMSS2_CLKCTRL (0xd8)<br>
+<br>
+/* EPWMSS1_CLKCTRL */<br>
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST (0x00030000u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_DISABLE (0x3u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC (0x0u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_IDLE (0x2u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_TRANS (0x1u)<br>
+<br>
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE (0x00000003u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_DISABLED (0x0u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE (0x2u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_RESERVED (0x3u)<br>
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)<br>
+<br>
+/* EPWMSS0_CLKCTRL */<br>
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST (0x00030000u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_DISABLED (0x3u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC (0x0u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_IDLE (0x2u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_TRANS (0x1u)<br>
+<br>
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE (0x00000003u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_DISABLE (0x0u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE (0x2u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_RESERVED (0x3u)<br>
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)<br>
+<br>
+/* EPWMSS2_CLKCTRL */<br>
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST (0x00030000u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_DISABLE (0x3u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC (0x0u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_IDLE (0x2u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_TRANS (0x1u)<br>
+<br>
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE (0x00000003u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_DISABLED (0x0u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE (0x2u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_RESERVED (0x3u)<br>
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)<br>
+<br>
+#define CONTROL_CONF_GPMC_AD(n) (0x800 + (n * 4))<br>
+#define CONTROL_CONF_LCD_DATA(n) (0x8a0 + (n * 4))<br>
+#define EHRPWM_TBCNT 0x8<br>
+<br>
+#define BBBIO_CONTROL_MODULE 0x44e10000<br>
+#define BBBIO_PWMSS_CTRL 0x664<br>
+#define BBBIO_CM_PER_ADDR 0x44e00000<br>
+#define BBBIO_CM_PER_EPWMSS1_CLKCTRL 0xcc<br>
+#define BBBIO_CM_PER_EPWMSS0_CLKCTRL 0xd4<br>
+#define BBBIO_CM_PER_EPWMSS2_CLKCTRL 0xd8<br>
+<br>
+#define PWMSS0_MMAP_ADDR 0x48300000<br>
+#define PWMSS1_MMAP_ADDR 0x48302000<br>
+#define PWMSS2_MMAP_ADDR 0x48304000<br>
+<br>
+#define BBBIO_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u)<br>
+#define BBBIO_PWMSS_CTRL_PWMSS1_TBCLKEN (0x00000002u)<br>
+#define BBBIO_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u)<br>
+<br>
+#define PWMSS_CLKCONFIG 0x8<br>
+#define PWMSS_CLK_EN_ACK 0x100<br>
+<br>
+#define TBCTL_CLKDIV (0x1C00u)<br>
+#define TBCTL_CLKDIV_SHIFT (0x000Au)<br>
+#define TBCTL_CLKDIV_DIVBY1 (0x0000u)<br>
+#define TBCTL_CLKDIV_DIVBY2 (0x0001u)<br>
+#define TBCTL_CLKDIV_DIVBY4 (0x0002u)<br>
+#define TBCTL_CLKDIV_DIVBY8 (0x0003u)<br>
+#define TBCTL_CLKDIV_DIVBY16 (0x0004u)<br>
+#define TBCTL_CLKDIV_DIVBY32 (0x0005u)<br>
+#define TBCTL_CLKDIV_DIVBY64 (0x0006u)<br>
+#define TBCTL_CLKDIV_DIVBY128 (0x0007u)<br>
+#define TBCTL_HSPCLKDIV (0x0380u)<br>
+#define TBCTL_HSPCLKDIV_SHIFT (0x0007u)<br>
+#define TBCTL_HSPCLKDIV_DIVBY1 (0x0000u)<br>
+#define TBCTL_HSPCLKDIV_DIVBY2 (0x0001u)<br>
+#define TBCTL_HSPCLKDIV_DIVBY4 (0x0002u)<br>
+#define TBCTL_HSPCLKDIV_DIVBY6 (0x0003u)<br>
+#define TBCTL_HSPCLKDIV_DIVBY8 (0x0004u)<br>
+#define TBCTL_HSPCLKDIV_DIVBY10 (0x0005u)<br>
+#define TBCTL_HSPCLKDIV_DIVBY12 (0x0006u)<br>
+#define TBCTL_HSPCLKDIV_DIVBY14 (0x0007u)<br>
+<br>
+<br>
+#define TBCTL_CLKDIV(x) ((x) << 10)<br>
+#define TBCTL_CLKDIV_MASK (3 << 10)<br>
+#define TBCTL_HSPCLKDIV(x) ((x) << 7)<br>
+#define TBCTL_HSPCLKDIV_MASK (3 << 7)<br>
+#define TBCTL_FREERUN (2 << 14)<br>
+#define TBCTL_CTRMODE_UP (0 << 0)<br>
diff --git a/testsuites/samples/Makefile.am b/testsuites/samples/Makefile.am<br>
index 374617b..70ebe57 100644<br>
--- a/testsuites/samples/Makefile.am<br>
+++ b/testsuites/samples/Makefile.am<br>
@@ -1,6 +1,6 @@<br>
ACLOCAL_AMFLAGS = -I ../aclocal<br>
<br>
-_SUBDIRS = hello capture ticker base_sp unlimited minimum fileio<br>
+_SUBDIRS = hello capture ticker base_sp unlimited minimum fileio pwm<br>
<br>
if MPTESTS<br>
## base_mp is a sample multiprocessing test<br>
diff --git a/testsuites/samples/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a> b/testsuites/samples/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
index 91a3661..72a64a0 100644<br>
--- a/testsuites/samples/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
+++ b/testsuites/samples/<a href="http://configure.ac" rel="noreferrer" target="_blank">configure.ac</a><br>
@@ -62,6 +62,7 @@ AC_CHECK_SIZEOF([time_t])<br>
AC_CONFIG_FILES([Makefile<br>
base_sp/Makefile<br>
hello/Makefile<br>
+pwm/Makefile<br>
loopback/Makefile<br>
minimum/Makefile<br>
fileio/Makefile<br>
diff --git a/testsuites/samples/pwm/Makefile.am b/testsuites/samples/pwm/Makefile.am<br>
new file mode 100644<br>
index 0000000..85d0fc1<br>
--- /dev/null<br>
+++ b/testsuites/samples/pwm/Makefile.am<br>
@@ -0,0 +1,19 @@<br>
+rtems_tests_PROGRAMS = pwm<br>
+pwm_SOURCES = init.c<br>
+<br>
+dist_rtems_tests_DATA = pwm.scn<br>
+dist_rtems_tests_DATA += pwm.doc<br>
+<br>
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg<br>
+include $(top_srcdir)/../automake/<a href="http://compile.am" rel="noreferrer" target="_blank">compile.am</a><br>
+include $(top_srcdir)/../automake/<a href="http://leaf.am" rel="noreferrer" target="_blank">leaf.am</a><br>
+<br>
+<br>
+LINK_OBJS = $(pwm_OBJECTS)<br>
+LINK_LIBS = $(pwm_LDLIBS)<br>
+<br>
+hello$(EXEEXT): $(pwm_OBJECTS) $(pwm_DEPENDENCIES)<br>
+ @rm -f pwm$(EXEEXT)<br>
+ $(make-exe)<br>
+<br>
+include $(top_srcdir)/../automake/<a href="http://local.am" rel="noreferrer" target="_blank">local.am</a><br>
diff --git a/testsuites/samples/pwm/init.c b/testsuites/samples/pwm/init.c<br>
new file mode 100644<br>
index 0000000..0814720<br>
--- /dev/null<br>
+++ b/testsuites/samples/pwm/init.c<br>
@@ -0,0 +1,70 @@<br>
+#ifdef HAVE_CONFIG_H<br>
+#include "config.h"<br>
+#endif<br>
+<br>
+#include<rtems/test.h><br>
+#include<bsp.h><br>
+#include<bsp/gpio.h><br>
+#include<stdio.h><br>
+#include<stdlib.h><br>
+<br>
+const char rtems_test_name[] = "Punit PWM test GSOC 2016";<br>
+rtems_printer rtems_test_printer;<br>
+<br>
+static void inline delay_sec(int sec)<br>
+{<br>
+ rtems_task_wake_after(sec*rtems_clock_get_ticks_per_second());<br>
+}<br>
+<br>
+rtems_task Init(rtems_task_argument argument);<br>
+<br>
+rtems_task Init(<br>
+ rtems_task_argument ignored<br>
+)<br>
+{<br>
+ rtems_test_begin();<br>
+ printf("Starting PWM Testing");<br>
+<br>
+/* Initialization PWM API*/<br>
+rtems_gpio_initialize();<br>
+pwm_init(PWMSS2_MMAP_ADDR, 2);<br>
+PWMSS_TB_clock_check(2);<br>
+<br>
+<br>
+ float PWM_HZ = 1.0f ;<br>
+ float duty_A = 50.0f ; /* 50% Duty cycle for PWM 2_A output */<br>
+ const float duty_B = 50.0f ; /* 50% Duty cycle for PWM 2_B output*/<br>
+<br>
+<br>
+ for(PWM_HZ=1; PWM_HZ <=100000000; PWM_HZ= PWM_HZ*3)<br>
+ {<br>
+ printf("\n Generating frequency : %f\n",PWM_HZ);<br>
+ PWMSS_Setting(SOC_EPWM_2_REGS, PWM_HZ ,duty_A , duty_B);<br>
+ printf("PWM enable for 10s ....\n");<br>
+ ehrPWM_Enable(SOC_EPWM_2_REGS);<br>
+ delay_sec(10);<br>
+<br>
+ ehrPWM_Disable(SOC_EPWM_2_REGS);<br>
+ }<br>
+ printf("close\n");<br>
+<br>
+}<br>
+<br>
+/* NOTICE: the clock driver is enabled */<br>
+#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER<br>
+#define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER<br>
+<br>
+#define CONFIGURE_MAXIMUM_TASKS 1<br>
+#define CONFIGURE_USE_DEVFS_AS_BASE_FILESYSTEM<br>
+<br>
+#define CONFIGURE_MAXIMUM_SEMAPHORES 1<br>
+<br>
+#define CONFIGURE_RTEMS_INIT_TASKS_TABLE<br>
+<br>
+#define CONFIGURE_EXTRA_TASK_STACKS (2 * RTEMS_MINIMUM_STACK_SIZE)<br>
+<br>
+#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION<br>
+<br>
+#define CONFIGURE_INIT<br>
+#include <rtems/confdefs.h><br>
+<br>
diff --git a/testsuites/samples/pwm/pwm.doc b/testsuites/samples/pwm/pwm.doc<br>
new file mode 100644<br>
index 0000000..9812864<br>
--- /dev/null<br>
+++ b/testsuites/samples/pwm/pwm.doc<br>
@@ -0,0 +1,9 @@<br>
+# COPYRIGHT (c) 1989-1999.<br>
+# On-Line Applications Research Corporation (OAR).<br>
+#<br>
+# The license and distribution terms for this file may be<br>
+# found in the file LICENSE in this distribution or at<br>
+# <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a>.<br>
+#<br>
+<br>
+<br>
diff --git a/testsuites/samples/pwm/pwm.scn b/testsuites/samples/pwm/pwm.scn<br>
new file mode 100644<br>
index 0000000..057ab6e<br>
--- /dev/null<br>
+++ b/testsuites/samples/pwm/pwm.scn<br>
@@ -0,0 +1,3 @@<br>
+*** GPIO TEST ***<br>
+Gpio Testing<br>
+*** END OF GPIO TEST ***<br>
<span><font color="#888888">--<br>
2.7.1<br>
<br>
</font></span></blockquote></div><br></div><div class="gmail_extra">Cheers,</div><div class="gmail_extra">Ketul</div></div>