<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">The Dhrystones are the same: 90k on the RPI 1 and 26k on the RPI 2. <div class=""><br class=""></div><div class="">I recall that when we first got the RPI 2 BSP to run, someone ( Sebastian, I think ) offered a cache configuration fix that made the RPI 2 much faster than the RPI 1, even with a single core.</div><div class=""><br class=""></div><div class="">But getting the RPI 2 to work again with known firmware is a great step. </div><div class=""><br class=""></div><div class="">Alan</div><div class=""><br class=""></div><div class=""><br class=""></div><div class=""><div class=""><div><blockquote type="cite" class=""><div class="">On Jul 4, 2016, at 10:20 PM, Joel Sherrill <<a href="mailto:joel@rtems.org" class="">joel@rtems.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><p dir="ltr" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br class="">On Jul 4, 2016 8:40 PM, "Alan Cudmore" <<a href="mailto:alan.cudmore@gmail.com" class="">alan.cudmore@gmail.com</a>> wrote:<br class="">><br class="">> I figured out my problem with the RPI 2, it was a configuration problem with my build.<br class="">><br class="">> So the latest RTEMS Git builds and runs on Raspberry Pi 2, Raspberry Pi A+, and Raspberry Pi Zero, all with the latest firmware.</p><p dir="ltr" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">How are the drystones?</p><p dir="ltr" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">> Thanks,<br class="">> Alan<br class="">><br class="">><br class="">><br class="">> > On Jul 4, 2016, at 6:29 PM, Alan Cudmore <<a href="mailto:alan.cudmore@gmail.com" class="">alan.cudmore@gmail.com</a>> wrote:<br class="">> ><br class="">> > I updated my RTEMS git and rebuilt the Pi and Pi2 BSPs.<br class="">> > Pi 1 works, but Pi 2 does not boot.<br class="">> ><br class="">> > Pi 1 has a speed up on the dhrystone command:<br class="">> > I get 90000 dhrystones per second.<br class="">> ><br class="">> > When I run your github pi branch, the Pi2 works with both the new and old firmware.<br class="">> > The new firmware Pi 2 dhrystone command is 26315 dhrystones per second<br class="">> > The old firmware Pi 2 dhrystone command is 45454 dhrystones per second.<br class="">> > So something in the firmware and caches is different, I can double check the configuration.<br class="">> ><br class="">> > But first, I will have to try to figure out the differences between the RTEMS git and your github and see why the Pi 2 is not booting for me.<br class="">> ><br class="">> > Thanks,<br class="">> > Alan<br class="">> ><br class="">> ><br class="">> >> On Jul 4, 2016, at 4:17 PM, Pavel Pisa <<a href="mailto:pisa@cmp.felk.cvut.cz" class="">pisa@cmp.felk.cvut.cz</a>> wrote:<br class="">> >><br class="">> >> Hello Alan and Rohini Kulkarni,<br class="">> >><br class="">> >> On Monday 04 of July 2016 18:47:09 Alan Cudmore wrote:<br class="">> >>> Hi Pavel,<br class="">> >>> I can confirm that your rtems-rpi-devel branch from your github account<br class="">> >>> works on the Raspberry Pi A+, Raspberry Pi Zero, and Raspberry Pi 2 with<br class="">> >>> the latest firmware.<br class="">> >>><br class="">> >>> I did notice that the Dhrystone benchmark runs 3 times faster on the Pi 1<br class="">> >>> than the Pi 2, but that could be the cache configuration.<br class="">> >><br class="">> >> Is this problem of the new firmware only?<br class="">> >> If answer is yes, then it can be problem with providing<br class="">> >> permission to control cache from SVC mode. Then some<br class="">> >> register setup before switching from HYP mode could be required.<br class="">> >><br class="">> >> If it is not related to new hardware then I think that<br class="">> >> there is no change in caching attributes introduced<br class="">> >> by all my changes and experience of Rohini Kulkarni working<br class="">> >> on RPi2 SMP project in frame of GSoC 2015 could help.<br class="">> >> Code is on GitHub,<br class="">> >><br class="">> >><span class="Apple-converted-space"> </span><a href="https://github.com/krohini1593/rtems" class="">https://github.com/krohini1593/rtems</a><br class="">> >><br class="">> >> which is not merged to RTEMS mainline yet.<br class="">> >><br class="">> >> There are some changes to change cache configuration.<br class="">> >><br class="">> >> I have tried some changes in bsp_start_hook_1<br class="">> >><br class="">> >> +#include <bsp/arm-cp15-start.h><br class="">> >><br class="">> >><br class="">> >> - bsp_memory_management_initialize();<br class="">> >> + uint32_t ctrl;<br class="">> >><br class="">> >> + /* turn mmu off first in case it's on */<br class="">> >> + ctrl = arm_cp15_start_setup_mmu_and_cache(<br class="">> >> + ARM_CP15_CTRL_M | ARM_CP15_CTRL_A, /* clear - mmu off */<br class="">> >> + ARM_CP15_CTRL_AFE<br class="">> >> + );<br class="">> >> +<br class="">> >> + ctrl |= ARM_CP15_CTRL_Z;<br class="">> >> +<br class="">> >> + arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(<br class="">> >> + ctrl,<br class="">> >> + (uint32_t *) bsp_translation_table_base,<br class="">> >> + ARM_MMU_DEFAULT_CLIENT_DOMAIN,<br class="">> >> + &arm_cp15_start_mmu_config_table[0],<br class="">> >> + arm_cp15_start_mmu_config_table_size<br class="">> >> + );<br class="">> >><br class="">> >> to ensure that ARM_CP15_CTRL_Z is set for branch predictor.<br class="">> >> But I have tried some modifications in BSP and I have observed<br class="">> >> no changes. RPi1 seems to run about 4 times faster in my case.<br class="">> >><br class="">> >> So it is probable that at cache is not enabled. May be only L2???<br class="">> >><br class="">> >> There can be mitchmatch between configured MMU table format/bit use<br class="">> >> and the way bits are filled. I have not time to recheck that<br class="">> >> yet but RPi2 code matches Cyclone Cortex-A9 BSP in CPU setup<br class="">> >> so it should be OK if there is not some Broadcom specific control<br class="">> >> register.<br class="">> >><br class="">> >> Best wishes,<br class="">> >><br class="">> >> Pavel<br class="">> ><br class="">><br class="">> _______________________________________________<br class="">> devel mailing list<br class="">><span class="Apple-converted-space"> </span><a href="mailto:devel@rtems.org" class="">devel@rtems.org</a><br class="">><span class="Apple-converted-space"> </span><a href="http://lists.rtems.org/mailman/listinfo/devel" class="">http://lists.rtems.org/mailman/listinfo/devel</a></p></div></blockquote></div><br class=""></div></div></body></html>