<div dir="ltr"><div dir="ltr" style="font-size:12.8px;text-decoration-style:initial;text-decoration-color:initial">Thanks Christian! This does indeed resolve the warning on psim so it should<div>be ok on all other powerpc BSPs. I will build all powerpc BSPs to double </div><div>check and then push.</div><div><br></div><div>--joel</div></div>
<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Aug 15, 2018 at 5:26 AM, <span dir="ltr"><<a href="mailto:list@c-mauderer.de" target="_blank">list@c-mauderer.de</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Christian Mauderer <<a href="mailto:christian.mauderer@embedded-brains.de">christian.mauderer@embedded-<wbr>brains.de</a>><br>
<br>
The field names for the registers generated a name collision (MSR_RI on<br>
the power pc). This patch adds a SC16IS752_ prefix for all field names.<br>
<br>
Closes #3501.<br>
---<br>
cpukit/dev/serial/sc16is752-<wbr>regs.h | 108 ++++++++++++++---------------<br>
cpukit/dev/serial/sc16is752.c | 85 ++++++++++++-----------<br>
2 files changed, 98 insertions(+), 95 deletions(-)<br>
<br>
diff --git a/cpukit/dev/serial/sc16is752-<wbr>regs.h b/cpukit/dev/serial/sc16is752-<wbr>regs.h<br>
index 21d425a118..b07e489a3e 100644<br>
--- a/cpukit/dev/serial/sc16is752-<wbr>regs.h<br>
+++ b/cpukit/dev/serial/sc16is752-<wbr>regs.h<br>
@@ -52,76 +52,76 @@ extern "C" {<br>
#define SC16IS752_XOFF2 0x7<br>
<br>
/* FCR */<br>
-#define FCR_FIFO_EN 0x01<br>
-#define FCR_RX_FIFO_RST 0x02<br>
-#define FCR_TX_FIFO_RST 0x04<br>
-#define FCR_TX_FIFO_TRG_8 0x00<br>
-#define FCR_TX_FIFO_TRG_16 0x10<br>
-#define FCR_TX_FIFO_TRG_32 0x20<br>
-#define FCR_TX_FIFO_TRG_56 0x30<br>
-#define FCR_RX_FIFO_TRG_8 0x00<br>
-#define FCR_RX_FIFO_TRG_16 0x40<br>
-#define FCR_RX_FIFO_TRG_56 0x80<br>
-#define FCR_RX_FIFO_TRG_60 0xc0<br>
+#define SC16IS752_FCR_FIFO_EN 0x01<br>
+#define SC16IS752_FCR_RX_FIFO_RST 0x02<br>
+#define SC16IS752_FCR_TX_FIFO_RST 0x04<br>
+#define SC16IS752_FCR_TX_FIFO_TRG_8 0x00<br>
+#define SC16IS752_FCR_TX_FIFO_TRG_16 0x10<br>
+#define SC16IS752_FCR_TX_FIFO_TRG_32 0x20<br>
+#define SC16IS752_FCR_TX_FIFO_TRG_56 0x30<br>
+#define SC16IS752_FCR_RX_FIFO_TRG_8 0x00<br>
+#define SC16IS752_FCR_RX_FIFO_TRG_16 0x40<br>
+#define SC16IS752_FCR_RX_FIFO_TRG_56 0x80<br>
+#define SC16IS752_FCR_RX_FIFO_TRG_60 0xc0<br>
<br>
/* EFCR */<br>
-#define EFCR_RS485_ENABLE (1u << 0)<br>
-#define EFCR_RX_DISABLE (1u << 1)<br>
-#define EFCR_TX_DISABLE (1u << 2)<br>
+#define SC16IS752_EFCR_RS485_ENABLE (1u << 0)<br>
+#define SC16IS752_EFCR_RX_DISABLE (1u << 1)<br>
+#define SC16IS752_EFCR_TX_DISABLE (1u << 2)<br>
<br>
/* IER */<br>
-#define IER_RHR (1u << 0)<br>
-#define IER_THR (1u << 1)<br>
-#define IER_RECEIVE_LINE_STATUS (1u << 2)<br>
-#define IER_MODEM_STATUS (1u << 3)<br>
-#define IER_SLEEP_MODE (1u << 4)<br>
-#define IER_XOFF (1u << 5)<br>
-#define IER_RTS (1u << 6)<br>
-#define IER_CTS (1u << 7)<br>
+#define SC16IS752_IER_RHR (1u << 0)<br>
+#define SC16IS752_IER_THR (1u << 1)<br>
+#define SC16IS752_IER_RECEIVE_LINE_<wbr>STATUS (1u << 2)<br>
+#define SC16IS752_IER_MODEM_STATUS (1u << 3)<br>
+#define SC16IS752_IER_SLEEP_MODE (1u << 4)<br>
+#define SC16IS752_IER_XOFF (1u << 5)<br>
+#define SC16IS752_IER_RTS (1u << 6)<br>
+#define SC16IS752_IER_CTS (1u << 7)<br>
<br>
/* IIR */<br>
-#define IIR_TX_INTERRUPT (1u << 1)<br>
-#define IIR_RX_INTERRUPT (1u << 2)<br>
+#define SC16IS752_IIR_TX_INTERRUPT (1u << 1)<br>
+#define SC16IS752_IIR_RX_INTERRUPT (1u << 2)<br>
<br>
/* LCR */<br>
-#define LCR_CHRL_5_BIT (0u << 1) | (0u << 0)<br>
-#define LCR_CHRL_6_BIT (0u << 1) | (1u << 0)<br>
-#define LCR_CHRL_7_BIT (1u << 1) | (0u << 0)<br>
-#define LCR_CHRL_8_BIT (1u << 1) | (1u << 0)<br>
-#define LCR_2_STOP_BIT (1u << 2)<br>
-#define LCR_SET_PARITY (1u << 3)<br>
-#define LCR_EVEN_PARITY (1u << 4)<br>
-#define LCR_ENABLE_DIVISOR (1u << 7)<br>
+#define SC16IS752_LCR_CHRL_5_BIT (0u << 1) | (0u << 0)<br>
+#define SC16IS752_LCR_CHRL_6_BIT (0u << 1) | (1u << 0)<br>
+#define SC16IS752_LCR_CHRL_7_BIT (1u << 1) | (0u << 0)<br>
+#define SC16IS752_LCR_CHRL_8_BIT (1u << 1) | (1u << 0)<br>
+#define SC16IS752_LCR_2_STOP_BIT (1u << 2)<br>
+#define SC16IS752_LCR_SET_PARITY (1u << 3)<br>
+#define SC16IS752_LCR_EVEN_PARITY (1u << 4)<br>
+#define SC16IS752_LCR_ENABLE_DIVISOR (1u << 7)<br>
<br>
/* LSR */<br>
-#define LSR_TXEMPTY (1u << 5)<br>
-#define LSR_RXRDY (1u << 0)<br>
-#define LSR_ERROR_BITS (7u << 2)<br>
+#define SC16IS752_LSR_TXEMPTY (1u << 5)<br>
+#define SC16IS752_LSR_RXRDY (1u << 0)<br>
+#define SC16IS752_LSR_ERROR_BITS (7u << 2)<br>
<br>
/* MCR */<br>
-#define MCR_DTR (1u << 0)<br>
-#define MCR_RTS (1u << 1)<br>
-#define MCR_TCR_TLR (1u << 2)<br>
-#define MCR_LOOPBACK (1u << 4)<br>
-#define MCR_XON_ANY (1u << 5)<br>
-#define MCR_IRDA_ENABLE (1u << 6)<br>
-#define MCR_PRESCALE_NEEDED (1u << 7)<br>
+#define SC16IS752_MCR_DTR (1u << 0)<br>
+#define SC16IS752_MCR_RTS (1u << 1)<br>
+#define SC16IS752_MCR_TCR_TLR (1u << 2)<br>
+#define SC16IS752_MCR_LOOPBACK (1u << 4)<br>
+#define SC16IS752_MCR_XON_ANY (1u << 5)<br>
+#define SC16IS752_MCR_IRDA_ENABLE (1u << 6)<br>
+#define SC16IS752_MCR_PRESCALE_NEEDED (1u << 7)<br>
<br>
/* MSR */<br>
-#define MSR_dCTS (1u << 0)<br>
-#define MSR_dDSR (1u << 1)<br>
-#define MSR_dRI (1u << 2)<br>
-#define MSR_dCD (1u << 3)<br>
-#define MSR_CTS (1u << 4)<br>
-#define MSR_DSR (1u << 5)<br>
-#define MSR_RI (1u << 6)<br>
-#define MSR_CD (1u << 7)<br>
+#define SC16IS752_MSR_dCTS (1u << 0)<br>
+#define SC16IS752_MSR_dDSR (1u << 1)<br>
+#define SC16IS752_MSR_dRI (1u << 2)<br>
+#define SC16IS752_MSR_dCD (1u << 3)<br>
+#define SC16IS752_MSR_CTS (1u << 4)<br>
+#define SC16IS752_MSR_DSR (1u << 5)<br>
+#define SC16IS752_MSR_RI (1u << 6)<br>
+#define SC16IS752_MSR_CD (1u << 7)<br>
<br>
/* EFR */<br>
-#define EFR_ENHANCED_FUNC_ENABLE (1u << 4)<br>
-#define EFR_SPECIAL_CHAR_DETECT (1u << 5)<br>
-#define EFR_RTS_FLOW_CTRL_EN (1u << 6)<br>
-#define EFR_CTS_FLOW_CTRL_EN (1u << 7)<br>
+#define SC16IS752_EFR_ENHANCED_FUNC_<wbr>ENABLE (1u << 4)<br>
+#define SC16IS752_EFR_SPECIAL_CHAR_<wbr>DETECT (1u << 5)<br>
+#define SC16IS752_EFR_RTS_FLOW_CTRL_EN (1u << 6)<br>
+#define SC16IS752_EFR_CTS_FLOW_CTRL_EN (1u << 7)<br>
<br>
/* IOCONTROL: User accessible. Therefore see sc16is752.h for the defines. */<br>
<br>
diff --git a/cpukit/dev/serial/sc16is752.<wbr>c b/cpukit/dev/serial/sc16is752.<wbr>c<br>
index ac88c8389f..0dcf21765a 100644<br>
--- a/cpukit/dev/serial/sc16is752.<wbr>c<br>
+++ b/cpukit/dev/serial/sc16is752.<wbr>c<br>
@@ -57,15 +57,15 @@ static void read_2_reg(<br>
<br>
static bool is_sleep_mode_enabled(<wbr>sc16is752_context *ctx)<br>
{<br>
- return (ctx->ier & IER_SLEEP_MODE) != 0;<br>
+ return (ctx->ier & SC16IS752_IER_SLEEP_MODE) != 0;<br>
}<br>
<br>
static void set_sleep_mode(sc16is752_<wbr>context *ctx, bool enable)<br>
{<br>
if (enable) {<br>
- ctx->ier |= IER_SLEEP_MODE;<br>
+ ctx->ier |= SC16IS752_IER_SLEEP_MODE;<br>
} else {<br>
- ctx->ier &= ~IER_SLEEP_MODE;<br>
+ ctx->ier &= ~SC16IS752_IER_SLEEP_MODE;<br>
}<br>
<br>
write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);<br>
@@ -85,14 +85,14 @@ static void set_mcr_dll_dlh(<br>
set_sleep_mode(ctx, false);<br>
}<br>
<br>
- ctx->lcr |= LCR_ENABLE_DIVISOR;<br>
+ ctx->lcr |= SC16IS752_LCR_ENABLE_DIVISOR;<br>
write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);<br>
<br>
write_reg(ctx, SC16IS752_MCR, &mcr, 1);<br>
write_reg(ctx, SC16IS752_DLH, &dlh, 1);<br>
write_reg(ctx, SC16IS752_DLL, &dll, 1);<br>
<br>
- ctx->lcr &= ~LCR_ENABLE_DIVISOR;<br>
+ ctx->lcr &= ~SC16IS752_LCR_ENABLE_DIVISOR;<br>
write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);<br>
<br>
if (sleep_mode) {<br>
@@ -127,10 +127,10 @@ static bool set_baud(sc16is752_context *ctx, rtems_termios_baud_t baud)<br>
if (divisor > 0xFFFF){<br>
return false;<br>
} else {<br>
- mcr |= MCR_PRESCALE_NEEDED;<br>
+ mcr |= SC16IS752_MCR_PRESCALE_NEEDED;<br>
}<br>
} else {<br>
- mcr &= ~MCR_PRESCALE_NEEDED;<br>
+ mcr &= ~SC16IS752_MCR_PRESCALE_<wbr>NEEDED;<br>
}<br>
<br>
set_mcr_dll_dlh(ctx, mcr, divisor);<br>
@@ -155,42 +155,42 @@ static bool sc16is752_set_attributes(<br>
}<br>
<br>
if ((term->c_cflag & CREAD) == 0){<br>
- ctx->efcr |= EFCR_RX_DISABLE;<br>
+ ctx->efcr |= SC16IS752_EFCR_RX_DISABLE;<br>
} else {<br>
- ctx->efcr &= ~EFCR_RX_DISABLE;<br>
+ ctx->efcr &= ~SC16IS752_EFCR_RX_DISABLE;<br>
}<br>
<br>
write_reg(ctx, SC16IS752_EFCR, &ctx->efcr, 1);<br>
<br>
switch (term->c_cflag & CSIZE) {<br>
case CS5:<br>
- ctx->lcr |= LCR_CHRL_5_BIT;<br>
+ ctx->lcr |= SC16IS752_LCR_CHRL_5_BIT;<br>
break;<br>
case CS6:<br>
- ctx->lcr |= LCR_CHRL_6_BIT;<br>
+ ctx->lcr |= SC16IS752_LCR_CHRL_6_BIT;<br>
break;<br>
case CS7:<br>
- ctx->lcr |= LCR_CHRL_7_BIT;<br>
+ ctx->lcr |= SC16IS752_LCR_CHRL_7_BIT;<br>
break;<br>
case CS8:<br>
- ctx->lcr |= LCR_CHRL_8_BIT;<br>
+ ctx->lcr |= SC16IS752_LCR_CHRL_8_BIT;<br>
break;<br>
}<br>
<br>
if ((term->c_cflag & PARENB) != 0){<br>
if ((term->c_cflag & PARODD) != 0) {<br>
- ctx->lcr &= ~LCR_EVEN_PARITY;<br>
+ ctx->lcr &= ~SC16IS752_LCR_EVEN_PARITY;<br>
} else {<br>
- ctx->lcr |= LCR_EVEN_PARITY;<br>
+ ctx->lcr |= SC16IS752_LCR_EVEN_PARITY;<br>
}<br>
} else {<br>
- ctx->lcr &= ~LCR_SET_PARITY;<br>
+ ctx->lcr &= ~SC16IS752_LCR_SET_PARITY;<br>
}<br>
<br>
if ((term->c_cflag & CSTOPB) != 0) {<br>
- ctx->lcr |= LCR_2_STOP_BIT;<br>
+ ctx->lcr |= SC16IS752_LCR_2_STOP_BIT;<br>
} else {<br>
- ctx->lcr &= ~LCR_2_STOP_BIT;<br>
+ ctx->lcr &= ~SC16IS752_LCR_2_STOP_BIT;<br>
}<br>
<br>
write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);<br>
@@ -218,20 +218,23 @@ static bool sc16is752_first_open(<br>
}<br>
<br>
if (ctx->mode == SC16IS752_MODE_RS485) {<br>
- ctx->efcr = EFCR_RS485_ENABLE;<br>
+ ctx->efcr = SC16IS752_EFCR_RS485_ENABLE;<br>
} else {<br>
ctx->efcr = 0;<br>
}<br>
<br>
write_reg(ctx, SC16IS752_FCR, &ctx->efcr, 1);<br>
<br>
- fcr = FCR_FIFO_EN | FCR_RX_FIFO_RST | FCR_TX_FIFO_RST<br>
- | FCR_RX_FIFO_TRG_16 | FCR_TX_FIFO_TRG_32;<br>
+ fcr = SC16IS752_FCR_FIFO_EN<br>
+ | SC16IS752_FCR_RX_FIFO_RST<br>
+ | SC16IS752_FCR_TX_FIFO_RST<br>
+ | SC16IS752_FCR_RX_FIFO_TRG_16<br>
+ | SC16IS752_FCR_TX_FIFO_TRG_32;<br>
write_reg(ctx, SC16IS752_FCR, &fcr, 1);<br>
<br>
- ctx->ier = IER_RHR;<br>
+ ctx->ier = SC16IS752_IER_RHR;<br>
write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);<br>
- set_efr(ctx, EFR_ENHANCED_FUNC_ENABLE);<br>
+ set_efr(ctx, SC16IS752_EFR_ENHANCED_FUNC_<wbr>ENABLE);<br>
<br>
rtems_termios_set_initial_<wbr>baud(tty, 115200);<br>
ok = sc16is752_set_attributes(base, term);<br>
@@ -265,14 +268,14 @@ static void sc16is752_write(<br>
sc16is752_context *ctx = (sc16is752_context *)base;<br>
<br>
if (len > 0) {<br>
- ctx->ier |= IER_THR;<br>
+ ctx->ier |= SC16IS752_IER_THR;<br>
len = MIN(len, 32);<br>
ctx->tx_in_progress = (uint8_t)len;<br>
write_reg(ctx, SC16IS752_THR, (const uint8_t *)&buf[0], len);<br>
write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);<br>
} else {<br>
ctx->tx_in_progress = 0;<br>
- ctx->ier &= ~IER_THR;<br>
+ ctx->ier &= ~SC16IS752_IER_THR;<br>
write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);<br>
}<br>
}<br>
@@ -286,22 +289,22 @@ static void sc16is752_get_modem_bits(<wbr>sc16is752_context *ctx, int *bits)<br>
read_reg(ctx, SC16IS752_MSR, &msr, 1);<br>
read_reg(ctx, SC16IS752_MCR, &mcr, 1);<br>
<br>
- if (msr & MSR_CTS) {<br>
+ if (msr & SC16IS752_MSR_CTS) {<br>
*bits |= TIOCM_CTS;<br>
}<br>
- if (msr & MSR_DSR) {<br>
+ if (msr & SC16IS752_MSR_DSR) {<br>
*bits |= TIOCM_DSR;<br>
}<br>
- if (msr & MSR_RI) {<br>
+ if (msr & SC16IS752_MSR_RI) {<br>
*bits |= TIOCM_RI;<br>
}<br>
- if (msr & MSR_CD) {<br>
+ if (msr & SC16IS752_MSR_CD) {<br>
*bits |= TIOCM_CD;<br>
}<br>
- if ((mcr & MCR_DTR) == 0) {<br>
+ if ((mcr & SC16IS752_MCR_DTR) == 0) {<br>
*bits |= TIOCM_DTR;<br>
}<br>
- if ((mcr & MCR_RTS) == 0) {<br>
+ if ((mcr & SC16IS752_MCR_RTS) == 0) {<br>
*bits |= TIOCM_RTS;<br>
}<br>
}<br>
@@ -316,29 +319,29 @@ static void sc16is752_set_modem_bits(<br>
<br>
if (bits != NULL) {<br>
if ((*bits & TIOCM_DTR) == 0) {<br>
- mcr |= MCR_DTR;<br>
+ mcr |= SC16IS752_MCR_DTR;<br>
} else {<br>
- mcr &= ~MCR_DTR;<br>
+ mcr &= ~SC16IS752_MCR_DTR;<br>
}<br>
<br>
if ((*bits & TIOCM_RTS) == 0) {<br>
- mcr |= MCR_RTS;<br>
+ mcr |= SC16IS752_MCR_RTS;<br>
} else {<br>
- mcr &= ~MCR_RTS;<br>
+ mcr &= ~SC16IS752_MCR_RTS;<br>
}<br>
}<br>
<br>
if ((set & TIOCM_DTR) != 0) {<br>
- mcr &= ~MCR_DTR;<br>
+ mcr &= ~SC16IS752_MCR_DTR;<br>
}<br>
if ((set & TIOCM_RTS) != 0) {<br>
- mcr &= ~MCR_RTS;<br>
+ mcr &= ~SC16IS752_MCR_RTS;<br>
}<br>
if ((clear & TIOCM_DTR) != 0) {<br>
- mcr |= MCR_DTR;<br>
+ mcr |= SC16IS752_MCR_DTR;<br>
}<br>
if ((clear & TIOCM_RTS) != 0) {<br>
- mcr |= MCR_RTS;<br>
+ mcr |= SC16IS752_MCR_RTS;<br>
}<br>
<br>
write_reg(ctx, SC16IS752_MCR, &mcr, 1);<br>
@@ -416,11 +419,11 @@ void sc16is752_interrupt_handler(<wbr>void *arg)<br>
read_2_reg(ctx, SC16IS752_IIR, SC16IS752_RXLVL, data);<br>
iir = data[0];<br>
<br>
- if ((iir & IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) {<br>
+ if ((iir & SC16IS752_IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) {<br>
rtems_termios_dequeue_<wbr>characters(ctx->tty, ctx->tx_in_progress);<br>
}<br>
<br>
- if ((iir & IIR_RX_INTERRUPT) != 0) {<br>
+ if ((iir & SC16IS752_IIR_RX_INTERRUPT) != 0) {<br>
uint8_t buf[SC16IS752_FIFO_DEPTH];<br>
uint8_t rxlvl = data[1];<br>
<span class="HOEnZb"><font color="#888888"> <br>
-- <br>
2.18.0<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
______________________________<wbr>_________________<br>
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</div></div></blockquote></div><br></div>