<div dir="auto">The order in which threads are assigned to cores has changed since the first smp work. It used to be from 0 up, now from the highest core associated with a scheduler down. If that's the only difference, the screen is out of date. <div dir="auto"><br></div><div dir="auto">Even if the screen is a guide of what to expect in some cases.</div><div dir="auto"><br></div><div dir="auto">How does the smp support in sis switch back and forth between the cores? Per cycle, instruction, etc. Qemu switches per instruction translation block as I recall.</div><div dir="auto"><br></div><div dir="auto">--joel</div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Dec 11, 2018, 9:24 AM Sebastian Huber <<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hello Jiri,<br>
<br>
On 11/12/2018 15:15, Jiri Gaisler wrote:<br>
> What is the status of the smptests of RTEMS 5 ?<br>
><br>
> I have added SMP capability to the sis simulator, and have tested it<br>
> with the smptests from rtems git. I have noticed that the reference<br>
> output (*.scn) are not equivalent to what the simulator or real hardware<br>
> outputs. It seems that the cpus are numbered backwards compared to the<br>
> .scn files.<br>
<br>
the .scn files are not up to date. Also the test output is quite test <br>
dependent and repeated test runs my produce different output.<br>
<br>
The best method to check if a test passed is to check if the<br>
<br>
*** END OF TEST XYZ ***<br>
<br>
<br>
message is printed. Which real target did you use to run the tests? I <br>
will do a test run tomorrow on a N2X.<br>
<br>
-- <br>
Sebastian Huber, embedded brains GmbH<br>
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