<div dir="ltr">Doh! If I am ok with it being merged, I should have pushed it. <div><br></div><div>Sorry. I still am not 100% well and suffering from cold meds.</div><div><br></div><div>--joel</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Feb 12, 2019 at 4:17 PM Joel Sherrill <<a href="mailto:joel.sherrill@gmail.com">joel.sherrill@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div>Just to be clear. I am OK with this being merged.</div><div><br></div><div><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Feb 5, 2019 at 10:45 AM Vijay Kumar Banerjee <<a href="mailto:vijaykumar9597@gmail.com" target="_blank">vijaykumar9597@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">---<br>
tester/covoar/TargetFactory.cc | 2 +<br>
tester/covoar/Target_riscv.cc | 83 +++++++++++++++++<br>
tester/covoar/Target_riscv.h | 95 ++++++++++++++++++++<br>
tester/covoar/wscript | 3 +-<br>
tester/rtems/testing/bsps/griscv-sis-cov.ini | 40 +++++++++<br>
5 files changed, 222 insertions(+), 1 deletion(-)<br>
create mode 100644 tester/covoar/Target_riscv.cc<br>
create mode 100644 tester/covoar/Target_riscv.h<br>
create mode 100644 tester/rtems/testing/bsps/griscv-sis-cov.ini<br>
<br>
diff --git a/tester/covoar/TargetFactory.cc b/tester/covoar/TargetFactory.cc<br>
index fc9c30b..12de94d 100644<br>
--- a/tester/covoar/TargetFactory.cc<br>
+++ b/tester/covoar/TargetFactory.cc<br>
@@ -23,6 +23,7 @@<br>
#include "Target_powerpc.h"<br>
#include "Target_lm32.h"<br>
#include "Target_sparc.h"<br>
+#include "Target_riscv.h"<br>
<br>
namespace Target {<br>
<br>
@@ -56,6 +57,7 @@ namespace Target {<br>
{ "m68k", Target_m68k_Constructor },<br>
{ "powerpc", Target_powerpc_Constructor },<br>
{ "sparc", Target_sparc_Constructor },<br>
+ { "riscv", Target_riscv_Constructor },<br>
{ "TBD", NULL },<br>
};<br>
<br>
diff --git a/tester/covoar/Target_riscv.cc b/tester/covoar/Target_riscv.cc<br>
new file mode 100644<br>
index 0000000..279dc6a<br>
--- /dev/null<br>
+++ b/tester/covoar/Target_riscv.cc<br>
@@ -0,0 +1,83 @@<br>
+/*<br>
+ * RTEMS Tools Project (<a href="http://www.rtems.org/" rel="noreferrer" target="_blank">http://www.rtems.org/</a>)<br>
+ * Copyright 2019 Vijay K. Banerjee <<a href="mailto:vijaykumar9597@gmail.com" target="_blank">vijaykumar9597@gmail.com</a>><br>
+ * All rights reserved.<br>
+ *<br>
+ * This file is part of the RTEMS Tools package in 'rtems-tools'.<br>
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions are met:<br>
+ *<br>
+ * 1. Redistributions of source code must retain the above copyright notice,<br>
+ * this list of conditions and the following disclaimer.<br>
+ *<br>
+ * 2. Redistributions in binary form must reproduce the above copyright notice,<br>
+ * this list of conditions and the following disclaimer in the documentation<br>
+ * and/or other materials provided with the distribution.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE<br>
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+ * POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+/*! @file Target_riscv.cc<br>
+ * @brief Target_riscv Implementation<br>
+ */<br>
+<br>
+#include "Target_riscv.h"<br>
+#include <stdio.h><br>
+#include <stdlib.h><br>
+#include <string.h><br>
+#include <unistd.h><br>
+<br>
+namespace Target {<br>
+<br>
+ Target_riscv::Target_riscv( std::string targetName ):<br>
+ TargetBase( targetName )<br>
+ {<br>
+ branchInstructions.push_back("beqz");<br>
+ branchInstructions.push_back("bnez");<br>
+ branchInstructions.push_back("blez");<br>
+ branchInstructions.push_back("bgez");<br>
+ branchInstructions.push_back("bltz");<br>
+ branchInstructions.push_back("bgt");<br>
+ branchInstructions.push_back("bgtz");<br>
+ branchInstructions.push_back("ble");<br>
+ branchInstructions.push_back("bgtu");<br>
+ branchInstructions.push_back("bleu");<br>
+<br>
+ branchInstructions.sort();<br>
+ }<br>
+<br>
+ Target_riscv::~Target_riscv()<br>
+ {<br>
+ }<br>
+<br>
+ bool Target_riscv::isNopLine(<br>
+ const char* const line,<br>
+ int& size<br>
+ )<br>
+ {<br>
+ if (!strcmp( &line[strlen(line)-3], "nop")){<br>
+ size = 4;<br>
+ return true;<br>
+ }<br>
+<br>
+ return false;<br>
+ }<br>
+<br>
+ TargetBase *Target_riscv_Constructor(<br>
+ std::string targetName<br>
+ )<br>
+ {<br>
+ return new Target_riscv( targetName );<br>
+ }<br>
+}<br>
diff --git a/tester/covoar/Target_riscv.h b/tester/covoar/Target_riscv.h<br>
new file mode 100644<br>
index 0000000..c1cf7ab<br>
--- /dev/null<br>
+++ b/tester/covoar/Target_riscv.h<br>
@@ -0,0 +1,95 @@<br>
+/*<br>
+ * RTEMS Tools Project (<a href="http://www.rtems.org/" rel="noreferrer" target="_blank">http://www.rtems.org/</a>)<br>
+ * Copyright 2019 Vijay K. Banerjee <<a href="mailto:vijaykumar9597@gmail.com" target="_blank">vijaykumar9597@gmail.com</a>><br>
+ * All rights reserved.<br>
+ *<br>
+ * This file is part of the RTEMS Tools package in 'rtems-tools'.<br>
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions are met:<br>
+ *<br>
+ * 1. Redistributions of source code must retain the above copyright notice,<br>
+ * this list of conditions and the following disclaimer.<br>
+ *<br>
+ * 2. Redistributions in binary form must reproduce the above copyright notice,<br>
+ * this list of conditions and the following disclaimer in the documentation<br>
+ * and/or other materials provided with the distribution.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE<br>
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+ * POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+/*! @file Target_riscv.h<br>
+ * @brief Target_riscv Specification<br>
+ *<br>
+ * This file contains the specification of the Target_riscv class.<br>
+ */<br>
+<br>
+#ifndef __TARGET_RISCV_H__<br>
+#define __TARGET_RISCV_H__<br>
+<br>
+#include <list><br>
+#include <string><br>
+#include "TargetBase.h"<br>
+<br>
+namespace Target {<br>
+<br>
+ /*! @class Target_riscv<br>
+ *<br>
+ * This is the class for the riscv target.<br>
+ */<br>
+ class Target_riscv: public TargetBase {<br>
+<br>
+ public:<br>
+<br>
+ /*!<br>
+ * Target_riscv constructor<br>
+ */<br>
+ Target_riscv( std::string targetName );<br>
+<br>
+ virtual ~Target_riscv();<br>
+<br>
+ /*!<br>
+ * This method determines nop instruction.<br>
+ *<br>
+ * @param[in] line contains the object dump line to check<br>
+ * @param[out] size is set to the size in bytes of the nop<br>
+ *<br>
+ * @return Returns True if the instruction is nop, False otherwise.<br>
+ */<br>
+ bool isNopLine(<br>
+ const char* const line,<br>
+ int& size<br>
+ );<br>
+<br>
+ /*!<br>
+ * This method determines if it's a branch instruction<br>
+ *<br>
+ * @param[in] instruction<br>
+ *<br>
+ * @return Returns True if the instruction is a branch instruction, False otherwise.<br>
+ */<br>
+<br>
+ bool isBranch(<br>
+ const char* const instruction<br>
+ );<br>
+<br>
+ private:<br>
+<br>
+ };<br>
+<br>
+ TargetBase *Target_riscv_Constructor(<br>
+ std::string targetName<br>
+ );<br>
+<br>
+}<br>
+#endif<br>
diff --git a/tester/covoar/wscript b/tester/covoar/wscript<br>
index a3730ea..6f722c2 100644<br>
--- a/tester/covoar/wscript<br>
+++ b/tester/covoar/wscript<br>
@@ -105,7 +105,8 @@ def build(bld):<br>
'Target_lm32.cc',<br>
'Target_m68k.cc',<br>
'Target_powerpc.cc',<br>
- 'Target_sparc.cc'],<br>
+ 'Target_sparc.cc',<br>
+ 'Target_riscv.cc'],<br>
cflags = ['-O2', '-g', '-Wall'],<br>
cxxflags = ['-std=c++11', '-O2', '-g', '-Wall'],<br>
includes = ['.'] + rtl_includes)<br>
diff --git a/tester/rtems/testing/bsps/griscv-sis-cov.ini b/tester/rtems/testing/bsps/griscv-sis-cov.ini<br>
new file mode 100644<br>
index 0000000..060bba7<br>
--- /dev/null<br>
+++ b/tester/rtems/testing/bsps/griscv-sis-cov.ini<br>
@@ -0,0 +1,40 @@<br>
+#<br>
+# RTEMS Tools Project (<a href="http://www.rtems.org/" rel="noreferrer" target="_blank">http://www.rtems.org/</a>)<br>
+# Copyright 2019 Vijay K. Banerjee (<a href="mailto:vijaykumar9597@gmail.com" target="_blank">vijaykumar9597@gmail.com</a>)<br>
+# All rights reserved.<br>
+#<br>
+# This file is part of the RTEMS Tools package in 'rtems-tools'.<br>
+#<br>
+# Redistribution and use in source and binary forms, with or without<br>
+# modification, are permitted provided that the following conditions are met:<br>
+#<br>
+# 1. Redistributions of source code must retain the above copyright notice,<br>
+# this list of conditions and the following disclaimer.<br>
+#<br>
+# 2. Redistributions in binary form must reproduce the above copyright notice,<br>
+# this list of conditions and the following disclaimer in the documentation<br>
+# and/or other materials provided with the distribution.<br>
+#<br>
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE<br>
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+# POSSIBILITY OF SUCH DAMAGE.<br>
+#<br>
+<br>
+#<br>
+# The griscv BSP on sis with coverage<br>
+#<br>
+[griscv-sis-cov]<br>
+bsp = griscv-sis<br>
+arch = riscv<br>
+tester = %{_rtscripts}/run.cfg<br>
+target = riscv-rtems5<br>
+bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis<br>
+bsp_run_opts = -nouartrx -r -tlim 300 s -m 4 -cov<br>
-- <br>
2.17.2<br>
<br>
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</blockquote></div></div>
</blockquote></div>