<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, May 20, 2019 at 11:23 PM Sebastian Huber <<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On 20/05/2019 20:23, Joel Sherrill wrote:<br>
> Hi<br>
><br>
> I can't seem to find the number of cores the RISC-V port has been tested<br>
> on. I couldn't even find test results for riscv RTEMS in the archives. <br>
> Info<br>
> appreciated.<br>
<br>
I tested with up to two cores and mostly using a 64-bit target. It <br>
should work on up to 32 cores.<br></blockquote><div><br></div><div>Was this on hardware or qemu? </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
><br>
> I see rtems-tester configurations for spike and sis. Are there any for <br>
> qemu?<br>
> I thought qemu worked for RISC-V even if it had to be a special version.<br>
<br>
The configurations without the _spike use Qemu.<br></blockquote><div><br></div><div>Thanks. Is this one of the RSB qemu configurations? </div><div><br></div><div>I am trying to figure out which BSP variants are expected to work with</div><div>which simulators and in what configurations so I can add them to the</div><div>semi-automated test sweep script I have been trying to run once a week.</div><div><br></div><div>Spike in the RSB doesn't build for me.</div><div><br></div><div>So I haven't found a combination of BSP and simulator to add.</div><div><br></div><div>Suggestions appreciated.</div><div><br></div><div>--joel</div><div><br></div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
-- <br>
Sebastian Huber, embedded brains GmbH<br>
<br>
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<br>
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<br>
</blockquote></div></div>