<div dir="ltr"><div>Hi all,</div><div><br></div>After this patch, you can safely remove all the Motorola M68xxx and Coldfire BSPs<div>from the wiki except probably mvme162lx (It was not mentioned in the </div><div>user/bsps/bsps-m68k.rst , does it also has to be added?)</div><div><br></div><div>Thanks</div><div>-Mritunjay</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Apr 7, 2020 at 2:56 AM Mritunjay <<a href="mailto:mritunjaysharma394@gmail.com">mritunjaysharma394@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">---<br>
user/bsps/bsps-m68k.rst | 829 +++++++++++++++++++++++++++++++++++++++-<br>
1 file changed, 818 insertions(+), 11 deletions(-)<br>
<br>
diff --git a/user/bsps/bsps-m68k.rst b/user/bsps/bsps-m68k.rst<br>
index bdb516b..a035137 100644<br>
--- a/user/bsps/bsps-m68k.rst<br>
+++ b/user/bsps/bsps-m68k.rst<br>
@@ -8,7 +8,22 @@ m68k (Motorola 68000 / ColdFire)<br>
av5282<br>
======<br>
<br>
-TODO.<br>
+Overview<br>
+---------<br>
+<br>
+The Freescale ColdFire? Evaluation Board provides a reference platform for<br>
+engineers to develop a variety of embedded processing applications requiring<br>
+networking connectivity. The board hosts all the necessary hardware and firmware<br>
+needed to implement a networked interface using the Freescale MCF5282 processor.<br>
+By including all the necessary physical layer (PHY) devices, memory and external<br>
+expansion capability the designer can implement any bridging application that<br>
+requires 10/100 Ethernet, UARTs, CAN interface, QSPI, analog inputs and/or<br>
+memory-mapped peripherals. The AvBus expansion connector allows for user defined<br>
+add-on hardware, or can be utilized with over 20 compatible evaluation and<br>
+development boards from Avnet Electronics Marketing. These boards can be mixed<br>
+and matched to provide a variety of additional hardware and firmware capability<br>
+from PCI and PCI-X connectivity, RapidIO, memory and communications and<br>
+video/audio functions.<br>
<br>
csb360<br>
======<br>
@@ -18,27 +33,372 @@ TODO.<br>
gen68340<br>
========<br>
<br>
-TODO.<br>
+Overview<br>
+--------<br>
+<br>
+The MC68340 is a high-performance 32-bit integrated processor with direct memory<br>
+access (DMA), combining an enhanced M68000-compatible processor, 32-bit DMA, and<br>
+other peripheral subsystems on a single integrated circuit. The MC68340 CPU32<br>
+delivers 32-bit CISC processor performance from a lower cost 16-bit memory<br>
+system. The combination of peripherals offered in the MC68340 can be found in a<br>
+diverse range of microprocessor-based systems.Systems requiring very high-speed<br>
+block transfers of data can benefit from the MC68340.<br>
+<br>
+Organization<br>
+-------------<br>
+<br>
+The M68300 family of integrated processors and controllers is built on an M68000<br>
+core processor, an on-chip bus, and a selection of intelligent peripherals<br>
+appropriate for a set of applications. The CPU32 is a powerful central<br>
+processor with nearly the performance of the MC68020. A system integration<br>
+module incorporates the external bus interface and many of the smaller circuits<br>
+that typically surround a microprocessor for address decoding, wait-state<br>
+insertion, interrupt prioritization, clock generation, arbitration, watchdog<br>
+timing, and power-on reset timing. Each member of the M68300 family is<br>
+distinguished by its selection of peripherals. Peripherals are chosen to address<br>
+specific applications but are often useful in a wide variety of applications.<br>
+The peripherals may be highly sophisticated timing or protocol engines that have<br>
+their own processors, or they may be more traditional peripheral functions, such<br>
+as UARTs and timers. Since each major function is designed in a standalone<br>
+module, each module might be found in many different M68300 family parts.<br>
+<br>
+Architecture<br>
+-------------<br>
+<br>
+The CPU32 is upward source- and object-code compatible with the MC68000 and<br>
+MC68010. It is downward source- and object-code compatible with the MC68020.<br>
+Within the M68000 family, architectural differences are limited to the<br>
+supervisory operating state. User state programs can be executed unchanged on<br>
+upward-compatible devices. The major CPU32 features are as follows:<br>
+<br>
+* 32-Bit Internal Data Path and Arithmetic Hardware<br>
+* 32-Bit Address Bus Supported by 32-Bit Calculations<br>
+* Rich Instruction Set<br>
+* Eight 32-Bit General-Purpose Data Registers<br>
+* Seven 32-Bit General-Purpose Address Registers<br>
+* Separate User and Supervisor Stack Pointers<br>
+* Separate User and Supervisor State Address Spaces<br>
+* Separate Program and Data Address Spaces<br>
+* Many Data Types<br>
+* Flexible Addressing Modes<br>
+* Full Interrupt Processing<br>
+* Expansion Capability<br>
+<br>
+The CPU32 is an M68000 family processor specially designed for use as a 32-bit<br>
+core processor and for operation over the intermodule bus (IMB). Designers used<br>
+the MC68020 as a model and included advances of the later M68000 family<br>
+processors, resulting in an instruction execution performance of 4 MIPS<br>
+(VAX-equivalent) at 25.16 MHz. The powerful and flexible M68000 architecture is<br>
+the basis of the CPU32. MC68000 (including the MC68HC000 and the MC68EC000) and<br>
+MC68010 user programs will run unmodified on the CPU32. The programmer can use<br>
+any of the eight 32-bit data registers for fast manipulation of data and any of<br>
+the eight 32-bit address registers for indexing data in memory. The CPU32 can<br>
+operate on data types of single bits, binary-coded decimal (BCD)digits, and 8,<br>
+16, and 32 bits. Peripherals and data in memory can reside anywhere in the<br>
+4-Gbyte linear address space. A supervisor operating mode protects system-level<br>
+resources from the more restricted user mode, allowing a true virtual<br>
+environment to be developed.<br>
+<br>
+Physical<br>
+---------<br>
+<br>
+The MC68340 is available as 0–16.78 MHz and 0–25.16 MHz, 0°C to +70°C and<br>
+-40°C to +85°C, and 5.0 V ±5% and 3.3 V ±0.3 supply voltages (reduced<br>
+frequencies at 3.3 V). Thirty-two power and ground leads minimize ground bounce<br>
+and ensure proper isolation of different sections of the chip, including the<br>
+clock oscillator. A 144 pins are used for signals and power. The MC68340 is<br>
+available in a gull-wing ceramic quad flat pack (CQFP) with 25.6-mil (0.001-in)<br>
+lead spacing or a 15 ´ 15 plastic pin grid array (PPGA) with 0.1-in pin spacing.<br>
+<br>
+System Integration Module<br>
+--------------------------<br>
+<br>
+The MC68340 SIM40 provides the external bus interface for both the CPU32 and the<br>
+DMA. It also eliminates much of the glue logic that typically supports the<br>
+microprocessor and its interface with the peripheral and memory system. The<br>
+SIM40 provides programmable circuits to perform address decoding and chip<br>
+selects, wait-state insertion, interrupt handling, clock generation, bus<br>
+arbitration, watchdog timing, discrete I/O, and power-on reset timing. A<br>
+boundary scan test capability is also provided.<br>
+<br>
+External Bus Interface<br>
+----------------------<br>
+<br>
+The external bus interface (EBI) handles thetransfer of information between the<br>
+internal CPU32 or DMA controller and memory, peripherals, or other processing<br>
+elements in the external address space. Based on the MC68030 bus, the external<br>
+bus provides up to 32 address lines and 16 data lines. Address extensions<br>
+identify each bus cycle as CPU32 or DMA initiated, supervisor or user privilege<br>
+level, and instruction or data access. The data bus allows dynamic sizing for<br>
+8- or 16-bit bus accesses (plus 32 bits for DMA). Synchronous transfers from the<br>
+CPU32 or the DMA can be made in as little as two clock cycles.<br>
+<br>
+Clock Synthesizer<br>
+-----------------<br>
+<br>
+The clock synthesizer generates the clock signals used by all internal<br>
+operations as well as a clock output used by external devices. The clock<br>
+synthesizer can operate with an inexpensive 32768-Hz watch crystal or an<br>
+external oscillator for reference, using an internal phase-locked loop and<br>
+voltage-controlled oscillator. At any time, software can select<br>
+clock frequencies from 131 kHz to 16.78 MHz or 25.16 MHz, favoring either low<br>
+power consumption or high performance. Alternately, an external clock can drive<br>
+the clock signal directly at the operating frequency. With its fully static<br>
+HCMOS design, it is possible to completely stop the system clock without losing<br>
+the contents of the internal registers.<br>
<br>
gen68360<br>
========<br>
<br>
-TODO.<br>
+Overview<br>
+---------<br>
+<br>
+The MC68360 Quad Integrated Communication Controller (QUICC™) is a versatile<br>
+one-chip integrated microprocessor and peripheral combination family that can be<br>
+used in a variety of controller applications.<br>
+<br>
+The MC68360 particularly excels in communications activities. The QUICC can be<br>
+described as a next-generation MC68302, with higher performance in all areas of<br>
+device operation, increased flexibility, and higher integration. The term "quad"<br>
+comes from the fact that there are four serial communications controllers<br>
+(SCCs) on the device. However, there are actually seven serial channels which<br>
+include four SCCs, two serial management controllers (SMCs), and one serial<br>
+peripheral interface (SPI).<br>
+<br>
+Features<br>
+---------<br>
+CPU + Processor (8.3 MIPS at 33MHz)<br>
+<br>
+* 32-bit version of the CPU32 core (fully compatible with CPU32)<br>
+* Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address<br>
+Lines<br>
+<br>
+* Complete static design (0-33 MHz Operation)<br>
+* Slave mode to disable CPU32+ (allows use with external processors)<br>
+ * Multiple QUICCs can share one system bus (one master)<br>
+ * MC68040 companion mode allows QUICC to be an MC68040 companion chip and<br>
+ intelligent peripheral (29 MIPS at 33 MHz)<br>
+<br>
+ * All QUICC features available in slave mode<br>
+* Memory controller (eight banks)<br>
+ * Contains complete Dynamic Random-Access Memory (DRAM) controller<br>
+ * Glueless interface to DRAM Single In-Line Memory Modules (SIMMs), Static<br>
+ Random-Access Memory (SRAM),<br>
+<br>
+ * Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc.<br>
+ * Boot chip select available at Reset (options for 8-, 16-, or 32-bit<br>
+ memory)<br>
+<br>
+ * Special features for MC68040 including Burst Mode<br>
+* Four general-purpose timers<br>
+ * Four 16-bit timers or two 32-bit timers<br>
+* Two Independent DMAs (IDMAs)<br>
+* System Integration Module (SIM60)<br>
+ * Bus monitor<br>
+ * Breakpoint logic provides on-chip H/W breakpoints<br>
+ * Spurious interrupt monitor<br>
+ * External masters may use on-chip features such as chip selects<br>
+* Periodic interrupt timer<br>
+* On-chip bus arbitration with no overhead for internal masters<br>
+* Low power stop mode<br>
+* IEEE 1149.1 Test Access Port<br>
+* RISC Communications Processor Module (CPM)<br>
+* Many new commands (e.g., Graceful Stop Transmit, Close RxBD)<br>
+* Supports continuos mode transmission and reception on all serial channels<br>
+* 2.5 kbytes of dual-port RAM<br>
+* 14 Serial DMA (SDMA) channels<br>
+* Three parallel I/O registers with open-drain capability<br>
+* Each serial channel can have its own Pins (NMSI mode)<br>
+* Four baud rate generators<br>
+* Four SCCs<br>
+* Ethernet/IEEE 802.3 optional on SCCs 1-2@25 MHz, SCCs 1-3@33 MHz<br>
+* HDLC Bus<br>
+* Universal Asynchronous Receiver Transmitter (UART)<br>
+* Synchronous UART<br>
+* Asynchronous HDLC (RAM microcode option) to support PPP (Point to Point<br>
+Protocol)<br>
+<br>
+* Two SMCs<br>
+* UART<br>
+* Transparent<br>
+* General Circuit Interface (GCI) controller<br>
+* One SPI<br>
+* Time-Slot assignor<br>
+* Supports two TDM channels<br>
+* Parallel Interface Port (supports fast connection between QUICCs)<br>
+<br>
+Host controlled Board Setup<br>
+---------------------------<br>
+<br>
+Required equipment:<br>
+<br>
+* +5 V 5 A power supply<br>
+* +12 V 1 A power supply (optional)<br>
+* Host Computer, one of the following:<br>
+* Sun - 4 (SBus interface)<br>
+* IBM-PC/XT/AT<br>
+* ADI board - compatible with the host computer<br>
+* 37 line flat cable with female 37 pin D-type connectors on each end<br>
+<br>
+Stand alone Board Setup<br>
+------------------------<br>
+<br>
+Required equipment:<br>
+<br>
+* +5 V 5 A power supply<br>
+* +12 V 1 A power supply (optional)<br>
+* VT100 compatible terminal<br>
+* RS-232 cable with male 9 pin D-type connector on the QUADS side.<br>
+<br>
+Debugging BDM controller<br>
+------------------------<br>
+<br>
+The slave QUICC enables the M68360QUADS to become BDM controller to control<br>
+other QUICC devices on the user application. The BDM feature enables the user to<br>
+download code and provides hardware and software debugging capability of the<br>
+user application. The 8 pin BDM connector P9 utilizes five pins of the slave<br>
+QUICC port B. These pins are configured as general purpose I/O pins.<br>
+<br>
+Debugging Ethernet controller<br>
+-----------------------------<br>
+<br>
+The slave QUICC provides Ethernet port for the M68360QUADS by connecting SCC1 to<br>
+Motorola MC68160 EEST device (U35 in sheet 10). The MC68160 provides two<br>
+Ethernet interfaces, twisted-pair on P8 and AUI on P7. The LEDs LD3-LD8 are<br>
+controlled by the EEST, and they provide indications about the status of the<br>
+Ethernet ports activity. The signals between the slave QUICC and the MC68160<br>
+appear on connector P10 for debugging purposes. P10 is a set of wire holes.<br>
+The socket U24 is installed for internal factory testing only. For proper<br>
+operation of the EEST, this socket must be empty.<br>
+<br>
+References<br>
+----------<br>
+<br>
+* `User Manual <<a href="https://www.nxp.com/docs/en/reference-manual/MC68360UM.pdf" rel="noreferrer" target="_blank">https://www.nxp.com/docs/en/reference-manual/MC68360UM.pdf</a>>`_<br>
<br>
genmcf548x<br>
==========<br>
<br>
-TODO.<br>
+Overview<br>
+---------<br>
+<br>
+The MCF548x family is based on the ColdFire V4e core, a complex which comprises<br>
+the ColdFire V4 central processor unit (CPU), an enhanced multiply-accumulate<br>
+unit (EMAC), a memory management unit (MMU), a double-precision floating point<br>
+unit (FPU) conforming to standard IEEE-754, and controllers for caches and local<br>
+data memories. The MCF548x family is capable of performing at an operating<br>
+frequency of up to 200 MHz or 308 MIPS.<br>
+<br>
+To maximize throughput, the MCF548x family incorporates three independent<br>
+external bus interfaces:<br>
+<br>
+* The general-purpose local bus (FlexBus) is used for system boot memories and<br>
+simple peripherals and has up to six chip selects.<br>
+<br>
+* Program code and data can be stored in SDRAM connected to a dedicated 32-bit<br>
+double data rate (DDR) bus that can run at up to one-half of the CPU core<br>
+frequency. The glueless DDR SDRAM controller handles all address multiplexing,<br>
+input and output strobe timing, and memory bus clock generation.<br>
+<br>
+* A 32-bit PCI bus compliant with the version 2.2 specification and running at<br>
+a typical frequency of 25 MHz or 50 MHz supports peripherals that require high<br>
+bandwidth, the ability to arbitrate for bus mastership, and access to internal<br>
+MCF548x memory resources.<br>
+<br>
+References<br>
+----------<br>
+<br>
+ * `User Manual <<a href="https://www.nxp.com/docs/en/reference-manual/MCF5485RM.pdf" rel="noreferrer" target="_blank">https://www.nxp.com/docs/en/reference-manual/MCF5485RM.pdf</a>>`_<br>
<br>
mcf5206elite<br>
============<br>
<br>
-TODO.<br>
+Overview<br>
+---------<br>
+<br>
+The MCF5206e integrated microprocessor combines a Version 2 (V2) ColdFire®<br>
+processor core with several peripheral functions such as a DRAM controller,<br>
+timers, general-purpose I/O and serial interfaces, debug module, and system<br>
+integration. Designed for embedded control applications, the V2 ColdFire core<br>
+delivers enhanced performance while maintaining<br>
+low system costs. To speed program execution, the largeon-chip instruction cache<br>
+and SRAM provide one-cycle access to critical code and data. The MCF5206e<br>
+greatly reduces the time required for system design and implementation by<br>
+packaging common system functions on chip and providing glueless interfaces to 8<br>
+bit, 16 bit, and 32 bit DRAM, SRAM, ROM, and I/O devices.<br>
+<br>
+The MCF5206e is an enhanced version of the MCF5206 processor, with the same<br>
+peripheral set, DMA, MAC, Hardware Divide, larger cache, and larger SRAM. It is<br>
+pin compatible with the MCF5206, with the DMA pins muxed with Timer 0 pins.<br>
+<br>
+References<br>
+----------<br>
+<br>
+ * `User Manual <<a href="https://www.nxp.com/docs/en/reference-manual/MCF5485RM.pdf" rel="noreferrer" target="_blank">https://www.nxp.com/docs/en/reference-manual/MCF5485RM.pdf</a>>`_<br>
+<br>
<br>
mcf52235<br>
========<br>
<br>
-TODO.<br>
+Overview<br>
+---------<br>
+<br>
+The MCF52235 represents a family of highly-integrated 32-bit microcontrollers<br>
+based on the V2 ColdFire microarchitecture. Featuring up to 32 Kbytes of<br>
+internal SRAM and 256 Kbytes of flash memory, four 32-bit timers with DMA<br>
+request capability, a 4-channel DMA controller, fast Ethernet controller,<br>
+a CAN module, an I2C™ module, 3 UARTs and a queued SPI, the MC52235 family has<br>
+been designed for general-purpose industrial control applications.<br>
+<br>
+This 32-bit device is based on the Version 2 ColdFire? core operating at a<br>
+frequency up to 60 MHz, offering high performance and low power consumption.<br>
+On-chip memories connected tightly to the processor core include up to 256<br>
+Kbytes of Flash and 32 Kbytes of static random access memory (SRAM).<br>
+<br>
+This BSP was heavily based on the MCF5235 BSP.<br>
+<br>
+Key features<br>
+------------<br>
+<br>
+* Version 2 ColdFire variable-length RISC processor core<br>
+* System debug support<br>
+* On-chip memories<br>
+* Power management<br>
+* Fast Ethernet Controller (FEC)<br>
+* On-chip Ethernet Transceiver (EPHY)<br>
+* FlexCAN 2.0B module<br>
+* Three universal asynchronous/synchronous receiver transmitters (UARTs)<br>
+* I2C module<br>
+* Queued serial peripheral interface (QSPI)<br>
+* Fast analog-to-digital converter (ADC)<br>
+* Four 32-bit DMA timers<br>
+* Four-channel general purpose timers<br>
+* Pulse-width modulation timer<br>
+* Real-Time Clock (RTC)<br>
+* Two periodic interrupt timers (PITs)<br>
+* Software watchdog timer<br>
+* Clock Generation Features<br>
+* Dual Interrupt Controllers (INTC0/INTC1)<br>
+* DMA controller<br>
+* Reset<br>
+* Chip integration module (CIM)<br>
+* General purpose I/O interface<br>
+* JTAG support for system level board testing<br>
+<br>
+Board Setup<br>
+------------<br>
+<br>
+To setup, we will display the firmware settings using the boot monitor's "state"<br>
+ command:<br>
+<br>
+.. code-block:: none<br>
+<br>
+ INET> state<br>
+ iface 0- IP addr:192.168.1.99 subnet:255.255.255.0 gateway:192.168.1.1<br>
+ current tick count 4204<br>
+ Task wakeups:netmain: 27<br>
+ nettick: 2102<br>
+ keyboard: 2099<br>
<br>
mcf5225x<br>
========<br>
@@ -48,7 +408,35 @@ TODO.<br>
mcf5235<br>
=======<br>
<br>
-TODO.<br>
+Overview<br>
+--------<br>
+<br>
+The MCF5235EVB is a Motorola evaluation board that is based on the Coldfire<br>
+MCF5235 32-bit processor. The board includes 32 Mbytes of SDRAM, 2Mbytes of<br>
+flash, the MCF5235 processor with a max core frequency of 150MHz, Ethernet<br>
+support, and CAN bus support. This BSP has also been tested to work with the<br>
+Coldfire MCF5270 processor with a max core frequency of 100MHz.<br>
+This BSP has also been tested to work with the newer Freescale M5235BCC<br>
+evaluation board and with the Axiom Manufacturing CMM-5235 Board.<br>
+The BSP provides support to run applications from both RAM when debugging and<br>
+from Flash when the application is complete.<br>
+<br>
+Board Setup<br>
+------------<br>
+<br>
+Here is the setup for the Axiom M5235BCC in the RTEMS Lab:<br>
+<br>
+.. code-block:: none<br>
+ dBUG> show<br>
+ base: 16 baud: 19200<br>
+ server: 192.168.1.92 client: 192.168.1.241<br>
+ gateway: 192.168.1.14 netmask: 255.255.255.0<br>
+ filename: /mcf5235.exe filetype: ELF<br>
+ ethaddr: 00:20:DD:00:00:11<br>
+<br>
+Downloading and Executing<br>
+--------------------------<br>
+<br>
<br>
mcf5329<br>
=======<br>
@@ -75,12 +463,133 @@ TODO.<br>
mvme147<br>
=======<br>
<br>
-TODO.<br>
+Overview<br>
+--------<br>
+<br>
+The MVME147 is a double-high VMEmodule based on the MC68030 microprocessor. It<br>
+is best utilized in a 32-bit VMEbus system with both P1 and P2 backplanes. The<br>
+module has high functionality with large onboard shared RAM, serial ports, and<br>
+Centronics printer port. The module provides a SCSI bus controller with DMA,<br>
+floating-point coprocessor, tick timer, watchdog timer, and time-of-day<br>
+clock/calendar with battery backup, 4KB of static RAM with battery backup, four<br>
+ROM sockets, and A32/D32 VMEbus interface with system controller functions.<br>
+<br>
+Key Features<br>
+------------<br>
+<br>
+* 16, 25, or 33.33 MHz MC68030 enhanced 32-bit microprocessor<br>
+* 16, 25, or 33.33 MHz MC68882 floating-point coprocessor<br>
+* 4, 8, 16, or 32MB of shared DRAM, with programmable parity<br>
+* 4K x 8 SRAM and time-of-day clock with battery backup<br>
+* Four 28/32-pin ROM/PROM/EPROM/EEPROM sockets, 16 bits wide<br>
+* A32/D32 VMEbus master/slave interface with system controller function<br>
+* Four EIA-232-D serial communications ports<br>
+* Centronics compatible printer port<br>
+* Two 16-bit timers and watchdog timer<br>
+* SCSI bus interface with DMA<br>
+* Ethernet transceiver interface<br>
+* 4-level requester, 7-level interrupter, and 7-level interrupt handler for<br>
+VMEbus<br>
+<br>
+* On-board debugger and diagnostic firmware<br>
+<br>
+Board Setup<br>
+-----------<br>
+<br>
+Set jumpers on your MVME147 module. Ensure that ROM devices are properly<br>
+installed in the sockets. Install your MVME147 module in the chassis. Set<br>
+jumpers on the transition board; connect and install the transition board, P2<br>
+adapter module, and optional SCSI device cables. Connect a console terminal to<br>
+the MVME712. Connect any other optional devices or equipment you will be using.<br>
+Power up the system. Note that the debugger prompt appears. Initialize the<br>
+clock. Examine and/or change environmental parameters. Program the PCCchip and<br>
+VMEchip.<br>
+<br>
+See `manual <<a href="http://ppd.fnal.gov/experiments/e907/TPC/DAQ/147aih.pdf" rel="noreferrer" target="_blank">ppd.fnal.gov/experiments/e907/TPC/DAQ/147aih.pdf</a>>`_ for further<br>
+information.<br>
+<br>
+Downloading and Executing<br>
+--------------------------<br>
+<br>
+There are various ways to enter a user program into system memory for execution.<br>
+One way is to create the program using the Memory Modify (MM) command with the<br>
+assembler/disassembler option. You enter the program one source line at a time.<br>
+After each source line is entered, it is assembled and the object code loads<br>
+into memory. Refer to the MVME147 BUG 147Bug Debugging Package User's Manual for<br>
+complete details of the 147Bug Assembler/Disassembler?. Another way to enter a<br>
+program is to download an object file from a host system. The program must be in<br>
+S-record format (described in the MVME147BUG 147Bug Debugging Package User's<br>
+Manual) and may have been assembled or compiled on the host system. Alternately,<br>
+the program may have been previously created using the 147Bug MM command as<br>
+outlined above and stored to the host using the Dump (DU) command. A<br>
+communication link must exist between the host system and the MVME147. The file<br>
+is downloaded from the host to MVME147 memory by the Load (LO) command.<br>
+<br>
+References<br>
+----------<br>
+<br>
+ * `User Manual <<a href="http://ppd.fnal.gov/experiments/e907/TPC/DAQ/147aih.pdf" rel="noreferrer" target="_blank">ppd.fnal.gov/experiments/e907/TPC/DAQ/147aih.pdf</a>>`_<br>
<br>
mvme147s<br>
========<br>
<br>
-TODO.<br>
+Overview<br>
+---------<br>
+<br>
+The MVME 147s is extremely similar to the Mvme147. The main difference between<br>
+them is that the 147s also has only 2KB of static RAM while the 147 has 4KB.<br>
+<br>
+Another small difference between them is the time-of-day clock. The MVME147s has<br>
+ a Mostek MK48T02 while the MVME147 has an M48T18.<br>
+<br>
+The MVME147S is a double-high VMEmodule and is best utilized in a 32-bit VMEbus<br>
+system with both P1 and P2 backplanes. The module has high functionality with<br>
+large onboard shared RAM, serial ports, and Centronics printer port. The module<br>
+provides a SCSI bus controller with DMA, floating-point coprocessor, tick timer,<br>
+watchdog timer, and time-of-day clock/calendar with battery backup, 2KB of<br>
+static RAM with battery backup, four ROM sockets, and A32/D32 VMEbus interface<br>
+with system controller functions are also provided. The MVME147S can be operated<br>
+as part of a VMEbus system with other VMEmodules such as RAM modules, CPU<br>
+modules, graphics modules, and analog I/O modules.<br>
+<br>
+Board Setup<br>
+------------<br>
+<br>
+To select the desired configuration and ensure proper operation of the MVME147S<br>
+module, certain changes may be made before installation. These changes are made<br>
+through jumper arrangements on the headers. The module has been factory tested<br>
+and is shipped with factory-installed jumper configurations. The module is<br>
+operational with the factory-installed jumpers. The module is configured to<br>
+provide the system functions required for a VMEbus system. It is necessary to<br>
+make changes in the jumper arrangements for the following conditions:<br>
+<br>
+System controller select (J3) Factory use only (J5, J6) ROM configuration select<br>
+ (J1, J2) Serial port 4 clock configuration select (J8, J9)<br>
+<br>
+See `manual <<a href="http://www.ing.iac.es/~docs/external/vme/147s_d3.pdf" rel="noreferrer" target="_blank">www.ing.iac.es/~docs/external/vme/147s_d3.pdf</a>>`_ for further<br>
+information.<br>
+<br>
+Downloading and Executing<br>
+--------------------------<br>
+<br>
+There are various ways to enter a user program into system memory for execution.<br>
+One way is to create the program using the Memory Modify (MM) command with the<br>
+assembler/disassembler option. You enter the program one source line at a time.<br>
+After each source line is entered, it is assembled and the object code loads<br>
+into memory. Refer to the MVME147 BUG 147Bug Debugging Package User's Manual for<br>
+complete details of the 147Bug Assembler/Disassembler?. Another way to enter a<br>
+program is to download an object file from a host system. The program must be in<br>
+S-record format (described in the MVME147BUG 147Bug Debugging Package User's<br>
+Manual) and may have been assembled or compiled on the host system.<br>
+Alternately, the program may have been previously created using the 147Bug MM<br>
+command as outlined above and stored to the host using the Dump (DU) command.<br>
+A communication link must exist between the host system and the MVME147. The<br>
+file is downloaded from the host to MVME147 memory by the Load (LO) command.<br>
+<br>
+References<br>
+----------<br>
+<br>
+* `User Manual <<a href="http://www.ing.iac.es/~docs/external/vme/147s_d3.pdf" rel="noreferrer" target="_blank">www.ing.iac.es/~docs/external/vme/147s_d3.pdf</a>>`_<br>
<br>
mvme162<br>
=======<br>
@@ -264,9 +773,307 @@ The program will automatically run when download is complete.<br>
mvme167<br>
=======<br>
<br>
-TODO.<br>
+Overview<br>
+---------<br>
+<br>
+The MVME167 is a double-high VMEmodule based on the MC68040 microprocessor.The<br>
+MVME167 has 4/8/16/32/64 MB of parity-protected DRAM or4/8/16/32/64/128/256 MB<br>
+of ECC-protected DRAM, 8KB of static RAM and time of day clock (with<br>
+battery backup), Ethernet transceiver interface, four serial ports with<br>
+EIA-232-D interface, four tick timers, watchdog timer, four ROM sockets, SCSI<br>
+bus interface with DMA, Centronics printer port, A16/A24/A32/D8/D16/D32/D64<br>
+VMEbus master/slave interface, 128KB of static RAM (with optional battery<br>
+backup),and VMEbus system controller.<br>
+<br>
+Firmware Setup<br>
+---------------<br>
+<br>
+The mvme167 BSP by default (i.e., unless you tamper with the linkcmds) is linked<br>
+at 0x00800000 and the firmware has to be properly configured so that loading and<br>
+executing at that address is possible: # The board's RAM must be mapped<br>
+starting at address 0x00800000 (and not zero as may seem more natural and which<br>
+IIRC is 167Bug's default). ## Use 167Bug's 'env' command to set the 'Base<br>
+Address of Local Memory' to 00800000. ## Use 167Bug's 'niot' command to set the<br>
+download and execution address to 00800000. # By default, the 167Bug firmware<br>
+uses the lowest 64k block of RAM it finds for internal data and this conflicts<br>
+with RTEMS' needs. 167Bug won't allow you to download the RTEMS image to<br>
+0x00800000 unless you instruct 167Bug to use another area (e.g., static RAM) for<br>
+it's internal data. ## Use 167Bug's 'env' command to set both, the 'Memory<br>
+Search Starting Address' and 'Memory Search Ending Address' to zero.<br>
+The 'search' area is the address-range that is scanned by 167Bug when it tries<br>
+to find an area for it's internal data. If it finds no RAM (since start==end)<br>
+then it uses static RAM and 00800000 and up can be used by RTEMS.<br>
+<br>
+These are the 'env' settings:<br>
+<br>
+.. code-block:: none<br>
+<br>
+ MPU Clock Speed =25Mhz<br>
+<br>
+ 167-Bug>env<br>
+ Bug or System environment [B/S] = B?<br>
+ Field Service Menu Enable [Y/N] = N?<br>
+ Remote Start Method Switch [G/M/B/N] = B?<br>
+ Probe System for Supported I/O Controllers [Y/N] = Y?<br>
+ Negate VMEbus SYSFAIL* Always [Y/N] = N?<br>
+ Local SCSI Bus Reset on Debugger Startup [Y/N] = N?<br>
+ Local SCSI Bus Negotiations Type [A/S/N] = A?<br>
+ Ignore CFGA Block on a Hard Disk Boot [Y/N] = Y?<br>
+ Auto Boot Enable [Y/N] = N?<br>
+ Auto Boot at power-up only [Y/N] = Y?<br>
+ Auto Boot Controller LUN = 00?<br>
+ Auto Boot Device LUN = 00?<br>
+ Auto Boot Abort Delay = 15?<br>
+ Auto Boot Default String [NULL for a empty string] = ?<br>
+ ROM Boot Enable [Y/N] = N?<br>
+ ROM Boot at power-up only [Y/N] = Y?<br>
+ ROM Boot Enable search of VMEbus [Y/N] = N?<br>
+ ROM Boot Abort Delay = 0?<br>
+ ROM Boot Direct Starting Address = FF800000?<br>
+ ROM Boot Direct Ending Address = FFBFFFFC?<br>
+ Network Auto Boot Enable [Y/N] = N?<br>
+ Network Auto Boot at power-up only [Y/N] = Y?<br>
+ Network Auto Boot Controller LUN = 00?<br>
+ Network Auto Boot Device LUN = 00?<br>
+ Network Auto Boot Abort Delay = 5?<br>
+ Network Auto Boot Configuration Parameters Pointer (NVRAM) = FFFC0000?<br>
+ Memory Search Starting Address = 00000000?<br>
+ Memory Search Ending Address = 00000000?<br>
+ Memory Search Increment Size = 00010000?<br>
+ Memory Search Delay Enable [Y/N] = N?<br>
+ Memory Search Delay Address = FFFFCE0F?<br>
+ Memory Size Enable [Y/N] = Y?<br>
+ Memory Size Starting Address = 00000000?<br>
+ Memory Size Ending Address = 01000000?<br>
+ Base Address of Local Memory = 00800000?<br>
+ Size of Local Memory Board #0 = 00800000?<br>
+ Size of Local Memory Board #1 = 00000000?<br>
+ Slave Enable #1 [Y/N] = Y?<br>
+ Slave Starting Address #1 = 00000000?<br>
+ Slave Ending Address #1 = 007FFFFF?<br>
+ Slave Address Translation Address #1 = 00000000?<br>
+ Slave Address Translation Select #1 = FF800000?<br>
+ Slave Control #1 = 00FF?<br>
+ Slave Enable #2 [Y/N] = N?<br>
+ Slave Starting Address #2 = FFE00000?<br>
+ Slave Ending Address #2 = FFE1FFFF?<br>
+ Slave Address Translation Address #2 = 00000000?<br>
+ Slave Address Translation Select #2 = 00000000?<br>
+ Slave Control #2 = 01EF?<br>
+ Master Enable #1 [Y/N] = Y?<br>
+ Master Starting Address #1 = 01000000?<br>
+ Master Ending Address #1 = EFFFFFFF?<br>
+ Master Control #1 = 0D?<br>
+ Master Enable #2 [Y/N] = N?<br>
+ Master Starting Address #2 = 00000000?<br>
+ Master Ending Address #2 = 00000000?<br>
+ Master Control #2 = 00?<br>
+ Master Enable #3 [Y/N] = N?<br>
+ Master Starting Address #3 = 00800000?<br>
+ Master Ending Address #3 = 00FFFFFF?<br>
+ Master Control #3 = 3D?<br>
+ Master Enable #4 [Y/N] = N?<br>
+ Master Starting Address #4 = 00000000?<br>
+ Master Ending Address #4 = 00000000?<br>
+ Master Address Translation Address #4 = 00000000?<br>
+ Master Address Translation Select #4 = 00000000?<br>
+ Master Control #4 = 00?<br>
+ Short I/O (VMEbus A16) Enable [Y/N] = Y?<br>
+ Short I/O (VMEbus A16) Control = 01?<br>
+ F-Page (VMEbus A24) Enable [Y/N] = Y?<br>
+ F-Page (VMEbus A24) Control = 02?<br>
+ ROM Speed Bank A Code = 05?<br>
+ ROM Speed Bank B Code = 05?<br>
+ Static RAM Speed Code = 01?<br>
+ PCC2 Vector Base = 05?<br>
+ VMEC2 Vector Base #1 = 06?<br>
+ VMEC2 Vector Base #2 = 07?<br>
+ VMEC2 GCSR Group Base Address = CC?<br>
+ VMEC2 GCSR Board Base Address = 00?<br>
+ VMEbus Global Time Out Code = 01?<br>
+ Local Bus Time Out Code = 00?<br>
+ VMEbus Access Time Out Code = 02?<br>
+ 167-Bug><br>
+<br>
+NIOT (Network I/O Teach) is a 167-Bug's debugger command commonly<br>
+used to setup the Server/Client IP Addresses for the TFTP Transfer.<br>
+<br>
+The NIOT command goes something like this:<br>
+<br>
+<br>
+.. code-block:: none<br>
+<br>
+ 167-Bug>niot<br>
+ Controller LUN =00?<br>
+ Device LUN =00?<br>
+ Node Control Memory Address =FFE10000?<br>
+ Client IP Address =0.0.0.0?<br>
+ Server IP Address =0.0.0.0?<br>
+ Subnet IP Address Mask =0.0.0.0?<br>
+ Broadcast IP Address =0.0.0.0?<br>
+ Gateway IP Address =0.0.0.0?<br>
+ Boot File Name ("NULL" for None) =?<br>
+ Argument File Name ("NULL" for None) =?<br>
+ Boot File Load Address =00800000?<br>
+ Boot File Execution Address =00800000?<br>
+ Boot File Execution Delay =00000000?<br>
+ Boot File Length =00000000?<br>
+ Boot File Byte Offset =00000000?<br>
+ BOOTP/RARP Request Retry =00?<br>
+ TFTP/ARP Request Retry =00?<br>
+ Trace Character Buffer Address =00000000?<br>
+ BOOTP/RARP Request Control: Always/When-Needed (A/W)=A?<br>
+ BOOTP/RARP Reply Update Control: Yes/No (Y/N) =Y?<br>
+ 167-Bug><br>
+<br>
+RTEMS Lab Board Setup<br>
+----------------------<br>
+<br>
+The firmware setup instructions above are true for the RTEMS Lab board except<br>
+for the memory search addresses. Set these as follows:<br>
+<br>
+.. code-block:: none<br>
+<br>
+ Memory Search Starting Address = FFE00000?<br>
+ Memory Search Ending Address = FFE10000?<br>
+<br>
+These are the RTEMS Lab board settings:<br>
+<br>
+.. code-block:: none<br>
+<br>
+ MPU Clock Speed =25Mhz<br>
+<br>
+ 167-Bug>env<br>
+ Bug or System environment [B/S] = B?<br>
+ Field Service Menu Enable [Y/N] = N?<br>
+ Remote Start Method Switch [G/M/B/N] = B?<br>
+ Probe System for Supported I/O Controllers [Y/N] = Y?<br>
+ Negate VMEbus SYSFAIL* Always [Y/N] = N?<br>
+ Local SCSI Bus Reset on Debugger Startup [Y/N] = N?<br>
+ Ignore CFGA Block on a Hard Disk Boot [Y/N] = Y?<br>
+ Auto Boot Enable [Y/N] = N?<br>
+ Auto Boot at power-up only [Y/N] = Y?<br>
+ Auto Boot Controller LUN = 00?<br>
+ Auto Boot Device LUN = 00?<br>
+ Auto Boot Abort Delay = 15?<br>
+ Auto Boot Default String [Y(NULL String)/(String)] = ?<br>
+ ROM Boot Enable [Y/N] = N?<br>
+ ROM Boot at power-up only [Y/N] = Y?<br>
+ ROM Boot Enable search of VMEbus [Y/N] = N?<br>
+ ROM Boot Abort Delay = 0?<br>
+ ROM Boot Direct Starting Address = FF800000?<br>
+ ROM Boot Direct Ending Address = FFBFFFFC?<br>
+ Network Auto Boot Enable [Y/N] = N?<br>
+ Network Auto Boot at power-up only [Y/N] = N?<br>
+ Network Auto Boot Controller LUN = 00?<br>
+ Network Auto Boot Device LUN = 00?<br>
+ Network Auto Boot Abort Delay = 5?<br>
+ Network Auto Boot Configuration Parameters Pointer (NVRAM) = FFFC0000?<br>
+ Memory Search Starting Address = FFE00000?<br>
+ Memory Search Ending Address = FFE10000?<br>
+ Memory Search Increment Size = 00010000?<br>
+ Memory Search Delay Enable [Y/N] = N?<br>
+ Memory Search Delay Address = FFFFCE0F?<br>
+ Memory Size Enable [Y/N] = Y?<br>
+ Memory Size Starting Address = 00000000?<br>
+ Memory Size Ending Address = 01000000?<br>
+ Base Address of Local Memory = 00800000?<br>
+ Size of Local Memory Board #0 = 01000000?<br>
+ Size of Local Memory Board #1 = 00000000?<br>
+ Slave Enable #1 [Y/N] = Y?<br>
+ Slave Starting Address #1 = 00000000?<br>
+ Slave Ending Address #1 = 007FFFFF?<br>
+ Slave Address Translation Address #1 = 00000000?<br>
+ Slave Address Translation Select #1 = FF800000?<br>
+ Slave Control #1 = 00FF?<br>
+ Slave Enable #2 [Y/N] = N?<br>
+ Slave Starting Address #2 = FFE00000?<br>
+ Slave Ending Address #2 = FFE10000?<br>
+ Slave Address Translation Address #2 = 00000000?<br>
+ Slave Address Translation Select #2 = 00000000?<br>
+ Slave Control #2 = 01EF?<br>
+ Master Enable #1 [Y/N] = Y?<br>
+ Master Starting Address #1 = 01000000?<br>
+ Master Ending Address #1 = EFFFFFFF?<br>
+ Master Control #1 = 0D?<br>
+ Master Enable #2 [Y/N] = N?<br>
+ Master Starting Address #2 = 00000000?<br>
+ Master Ending Address #2 = 00000000?<br>
+ Master Control #2 = 00?<br>
+ Master Enable #3 [Y/N] = N?<br>
+ Master Starting Address #3 = 00800000?<br>
+ Master Ending Address #3 = 00FFFFFF?<br>
+ Master Control #3 = 30?<br>
+ Master Enable #4 [Y/N] = N?<br>
+ Master Starting Address #4 = 00000000?<br>
+ Master Ending Address #4 = 00000000?<br>
+ Master Address Translation Address #4 = 00000000?<br>
+ Master Address Translation Select #4 = 00000000?<br>
+ Master Control #4 = 00?<br>
+ Short I/O (VMEbus A16) Enable [Y/N] = Y?<br>
+ Short I/O (VMEbus A16) Control = 01?<br>
+ F-Page (VMEbus A24) Enable [Y/N] = Y?<br>
+ F-Page (VMEbus A24) Control = 02?<br>
+ ROM Speed Bank A Code = 05?<br>
+ ROM Speed Bank B Code = 05?<br>
+ Static RAM Speed Code = 01?<br>
+ PCC2 Vector Base = 05?<br>
+ VMEC2 Vector Base #1 = 06?<br>
+ VMEC2 Vector Base #2 = 07?<br>
+ VMEC2 GCSR Group Base Address = CC?<br>
+ VMEC2 GCSR Board Base Address = 00?<br>
+ VMEbus Global Time Out Code = 01?<br>
+ Local Bus Time Out Code = 00?<br>
+ VMEbus Access Time Out Code = 02?<br>
+<br>
+The NIOT command goes something like this:<br>
+<br>
+.. code-block:: none<br>
+<br>
+ 167-Bug>niot<br>
+ Controller LUN =00?<br>
+ Device LUN =00?<br>
+ Node Control Memory Address =FFE10000?<br>
+ Client IP Address =0.0.0.0?<br>
+ Server IP Address =0.0.0.0?<br>
+ Subnet IP Address Mask =255.255.255.0?<br>
+ Broadcast IP Address =255.255.255.255?<br>
+ Gateway IP Address =0.0.0.0?<br>
+ Boot File Name ("NULL" for None) =?<br>
+ Argument File Name ("NULL" for None) =?<br>
+ Boot File Load Address =00800000?<br>
+ Boot File Execution Address =00800000?<br>
+ Boot File Execution Delay =00000000?<br>
+ Boot File Length =00000000?<br>
+ Boot File Byte Offset =00000000?<br>
+ BOOTP/RARP Request Retry =00?<br>
+ TFTP/ARP Request Retry =00?<br>
+ Trace Character Buffer Address =00000000?<br>
+ BOOTP/RARP Request Control: Always/When-Needed (A/W)=A?<br>
+ BOOTP/RARP Reply Update Control: Yes/No (Y/N) =N?<br>
+<br>
+References<br>
+-----------<br>
+<br>
+* `User Manual <<a href="https://prep.fnal.gov/catalog/hardware_info/motorola/mvme167_d3.pdf" rel="noreferrer" target="_blank">https://prep.fnal.gov/catalog/hardware_info/motorola/mvme167_d3.pdf</a>>`_<br>
<br>
uC5282<br>
======<br>
<br>
-TODO.<br>
+Overview<br>
+--------<br>
+<br>
+The uC5282 is a compact, embedded microprocessor module ideal for networked<br>
+control and communication applications. The device is available in a standard<br>
+144pin soDIMM edge connector format to allow fast integration into products.<br>
+The module is based on the Freescale® ColdFire® MCF5282 microprocessor and<br>
+includes all required system memory and physical terminations to enable most<br>
+applications without the need for external circuitry. The uC5282 features<br>
+Ethernet, CAN and serial communications systems as well as standard peripheral<br>
+device connectivity using I2C, QSPI or data/address logic.<br>
+<br>
+References<br>
+-----------<br>
+<br>
+* `User Manual <<a href="https://prep.fnal.gov/catalog/hardware_info/motorola/mvme167_d3.pdf" rel="noreferrer" target="_blank">https://prep.fnal.gov/catalog/hardware_info/motorola/mvme167_d3.pdf</a>>`_<br>
+<br>
--<br>
2.17.1<br>
<br>
</blockquote></div>