<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Aug 13, 2020 at 9:49 PM 朱忠杰 <<a href="mailto:zhongjiezhu1@gmail.com">zhongjiezhu1@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Hi, everyone<br>
<br>
Is there any consideration why the FAST_IDLE is separated from normal<br>
path，can I change the FAST_IDLE like the following?<br></blockquote><div><br></div><div>The looks reasonably clean. It evolved over time so a clean up may just have</div><div>been overdue.</div><div><br></div><div>Just to be clear, this is a special mode only to be used on simulators when</div><div>you know the only source of interrupts is the clock tick. At this point, I would</div><div>tend to say it is not needed by the sparc BSPs because sis and tsim </div><div>are very fast themselves and also recognize when nothing is happening so</div><div>can quickly advance the state of the processor to the next event.</div><div><br></div><div>But qemu and gdb based simulators tend to need this enabled to speed</div><div>up runs of the test application. sp01 (same as ticker) is a good judge.</div><div>It runs for 30 seconds of target time. I have seen it take over 5 minutes on</div><div>simulators without fast idle. Also this was added in the days when </div><div>development computers were much slower.</div><div><br></div><div>If you are looking at fast idle, which BSPs have it as an option would be</div><div>good to check also.</div><div><br></div><div>--joel</div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
#if defined(BSP_FEATURE_IRQ_EXTENSION) || \<br>
(CPU_SIMPLE_VECTORED_INTERRUPTS != TRUE)<br>
void Clock_isr(void *arg);<br>
void Clock_isr(void *arg)<br>
{<br>
#else<br>
rtems_isr Clock_isr(rtems_vector_number vector);<br>
rtems_isr Clock_isr(<br>
rtems_vector_number vector<br>
)<br>
{<br>
#endif<br>
/*<br>
* Accurate count of ISRs<br>
*/<br>
Clock_driver_ticks += 1;<br>
<br>
#if CLOCK_DRIVER_ISRS_PER_TICK<br>
/*<br>
* The driver is multiple ISRs per clock tick.<br>
*/<br>
if ( !Clock_driver_isrs ) {<br>
Clock_driver_timecounter_tick();<br>
<br>
Clock_driver_isrs = CLOCK_DRIVER_ISRS_PER_TICK_VALUE;<br>
}<br>
Clock_driver_isrs--;<br>
#else<br>
/*<br>
* The driver is one ISR per clock tick.<br>
*/<br>
Clock_driver_timecounter_tick();<br>
<br>
#if CLOCK_DRIVER_USE_FAST_IDLE<br>
if (_SMP_Get_processor_maximum() == 1) {<br>
struct timecounter *tc;<br>
uint64_t us_per_tick;<br>
uint32_t interval;<br>
Per_CPU_Control *cpu_self;<br>
<br>
cpu_self = _Per_CPU_Get();<br>
tc = _Timecounter;<br>
us_per_tick = rtems_configuration_get_microseconds_per_tick();<br>
interval = (uint32_t) ((tc->tc_frequency * us_per_tick) / 1000000);<br>
<br>
while (<br>
cpu_self->thread_dispatch_disable_level == cpu_self->isr_nest_level<br>
&& cpu_self->heir == cpu_self->executing<br>
&& cpu_self->executing->is_idle<br>
) {<br>
ISR_lock_Context lock_context;<br>
<br>
_Timecounter_Acquire(&lock_context);<br>
_Timecounter_Tick_simple(<br>
interval,<br>
(*tc->tc_get_timecount)(tc),<br>
&lock_context<br>
);<br>
}<br>
}<br>
#endif<br>
#endif<br>
/*<br>
* Do the hardware specific per-tick action.<br>
*<br>
* The counter/timer may or may not be set to automatically reload.<br>
*/<br>
Clock_driver_support_at_tick();<br>
}<br>
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