<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Jun 7, 2021 at 1:57 PM <<a href="mailto:Jan.Sommer@dlr.de">Jan.Sommer@dlr.de</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
<br>
> -----Original Message-----<br>
> From: Gedare Bloom <<a href="mailto:gedare@rtems.org" target="_blank">gedare@rtems.org</a>><br>
> Sent: Monday, June 7, 2021 7:00 PM<br>
> To: Sommer, Jan <<a href="mailto:Jan.Sommer@dlr.de" target="_blank">Jan.Sommer@dlr.de</a>><br>
> Cc: <a href="mailto:devel@rtems.org" target="_blank">devel@rtems.org</a><br>
> Subject: Re: [PATCH v1] bsps/riscv: Give enough time for clock driver<br>
> initialization<br>
> <br>
> On Mon, Jun 7, 2021 at 9:47 AM Jan Sommer <<a href="mailto:jan.sommer@dlr.de" target="_blank">jan.sommer@dlr.de</a>> wrote:<br>
> ><br>
> > - Clock driver initialization for secondary cores had to take less<br>
> > than one tick<br>
> > - If tick time is small (i.e. <= 1ms) setting up all cores could take<br>
> > too long and a fatal error is thrown.<br>
> > - Give at least 10 ms time for clock initialization to avoid this<br>
> > error<br>
> <br>
> Is there a reason to pick 10?<br>
><br>
<br>
In qemu I (coarsely) measured 1.5ms for 8 cores.<br>
So I thought this should add enough buffer to prevent a fatal error.<br>
I probably could also reduce it to 5 ms.<br>
<br>
> I assume this blocks/idles the system until the interval elapses, so it would be<br>
> good to minimize waste (subject to Joel's noted rant about premature<br>
> optimization).<br>
></blockquote><div><br></div><div>No. I'm more worried about boot time. :)</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> <br>
<br>
If you take a look at the clock initialization of the secondary cores (<a href="https://git.rtems.org/rtems/tree/bsps/riscv/riscv/clock/clockdrv.c#n178" rel="noreferrer" target="_blank">https://git.rtems.org/rtems/tree/bsps/riscv/riscv/clock/clockdrv.c#n178</a>):<br>
<br>
_SMP_Othercast_action(riscv_clock_secondary_action, &cmpval);<br>
<br>
if (cmpval - riscv_clock_read_mtime(&clint->mtime) >= interval) {<br>
bsp_fatal(RISCV_FATAL_CLOCK_SMP_INIT);<br>
}<br>
<br>
It will put the first clock tick 10ms into the future (instead of just one tick), but it won't block the system initialization.<br>
It only prevents entering the if condition by having a large enough value for interval, but the runtime of the clock initialization is the same.<br>
<br></blockquote><div><br></div><div>How does this impact the timeline for boot to first application thread?</div><div><br></div><div>Is there a period where the system is up but only one core?</div><div><br></div><div>Any other oddities I might be missing?</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
> > ---<br>
> > bsps/riscv/riscv/clock/clockdrv.c | 8 +++++++-<br>
> > 1 file changed, 7 insertions(+), 1 deletion(-)<br>
> ><br>
> > diff --git a/bsps/riscv/riscv/clock/clockdrv.c<br>
> > b/bsps/riscv/riscv/clock/clockdrv.c<br>
> > index 3afe86576f..102137aeab 100644<br>
> > --- a/bsps/riscv/riscv/clock/clockdrv.c<br>
> > +++ b/bsps/riscv/riscv/clock/clockdrv.c<br>
> > @@ -211,7 +211,13 @@ static void riscv_clock_initialize(void)<br>
> > tc->interval = interval;<br>
> ><br>
> > cmpval = riscv_clock_read_mtime(&clint->mtime);<br>
> > - cmpval += interval;<br>
> > + /*<br>
> > + * For very short intervals the time of 1 tick is not enough to<br>
> > + * set up the timer on all cores in SMP systems.<br>
> > + * Give the CPU at least 10 ms.<br>
> > + */<br>
> > + interval = (10000 / us_per_tick) * interval; cmpval += interval;<br>
> ><br>
> > riscv_clock_clint_init(clint, cmpval, 0);<br>
> > riscv_clock_secondary_initialization(clint, cmpval, interval);<br>
> > --<br>
> > 2.17.1<br>
> ><br>
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</blockquote></div></div>