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<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US">Thanks, I prepared tickets for master and 5.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US">I will make sure that the link in the commit message fits the right ticket of the corresponding branch.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US">My plan is to push that on Monday, when I am back in the office<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US">Best regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US"> Jan<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b>From:</b> Joel Sherrill <joel@rtems.org> <br>
<b>Sent:</b> Wednesday, June 16, 2021 8:06 PM<br>
<b>To:</b> Gedare Bloom <gedare@rtems.org><br>
<b>Cc:</b> Sommer, Jan <Jan.Sommer@dlr.de>; devel@rtems.org<br>
<b>Subject:</b> Re: [PATCH v2 1/1] bsps/i386: Update calibration of TSC to be more accurate<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Me too. Just needs separate tickets for 5 and 6 so the release notes are generated correctly.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Wed, Jun 16, 2021 at 12:51 PM Gedare Bloom <<a href="mailto:gedare@rtems.org">gedare@rtems.org</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">I'm good with it for master and 5.<br>
<br>
On Wed, Jun 16, 2021 at 4:18 AM Jan Sommer <<a href="mailto:jan.sommer@dlr.de" target="_blank">jan.sommer@dlr.de</a>> wrote:<br>
><br>
> Closes #4455<br>
> ---<br>
> bsps/i386/pc386/clock/ckinit.c | 71 ++++++++++++++++++----------------<br>
> 1 file changed, 38 insertions(+), 33 deletions(-)<br>
><br>
> diff --git a/bsps/i386/pc386/clock/ckinit.c b/bsps/i386/pc386/clock/ckinit.c<br>
> index 09afe73cde..2df1818dd3 100644<br>
> --- a/bsps/i386/pc386/clock/ckinit.c<br>
> +++ b/bsps/i386/pc386/clock/ckinit.c<br>
> @@ -104,48 +104,60 @@ static uint32_t pc386_get_timecount_i8254(struct timecounter *tc)<br>
><br>
> /*<br>
> * Calibrate CPU cycles per tick. Interrupts should be disabled.<br>
> + * Will also set the PIT, so call this before registering the<br>
> + * periodic timer for rtems tick generation<br>
> */<br>
> static void calibrate_tsc(void)<br>
> {<br>
> uint64_t begin_time;<br>
> - uint8_t then_lsb, then_msb, now_lsb, now_msb;<br>
> - uint32_t i;<br>
> -<br>
> - /*<br>
> - * We just reset the timer, so we know we're at the beginning of a tick.<br>
> - */<br>
> -<br>
> - /*<br>
> - * Count cycles. Watching the timer introduces a several microsecond<br>
> - * uncertaintity, so let it cook for a while and divide by the number of<br>
> - * ticks actually executed.<br>
> - */<br>
> + uint8_t lsb, msb;<br>
> + uint32_t max_timer_value;<br>
> + uint32_t last_tick, cur_tick;<br>
> + int32_t diff, remaining;<br>
> +<br>
> + /* Set the timer to free running mode */<br>
> + outport_byte(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_INTTC);<br>
> + /* Reset the 16 timer reload value, first LSB, then MSB */<br>
> + outport_byte(TIMER_CNTR0, 0);<br>
> + outport_byte(TIMER_CNTR0, 0);<br>
> + /* We use the full 16 bit */<br>
> + max_timer_value = 0xffff;<br>
> + /* Calibrate for 1s, i.e. TIMER_TICK PIT ticks */<br>
> + remaining = TIMER_TICK;<br>
><br>
> begin_time = rdtsc();<br>
> -<br>
> - for (i = rtems_clock_get_ticks_per_second() * pc386_isrs_per_tick;<br>
> - i != 0; --i ) {<br>
> - /* We know we've just completed a tick when timer goes from low to high */<br>
> - then_lsb = then_msb = 0xff;<br>
> - do {<br>
> - READ_8254(now_lsb, now_msb);<br>
> - if ((then_msb < now_msb) ||<br>
> - ((then_msb == now_msb) && (then_lsb < now_lsb)))<br>
> - break;<br>
> - then_lsb = now_lsb;<br>
> - then_msb = now_msb;<br>
> - } while (1);<br>
> + READ_8254(lsb, msb);<br>
> + last_tick = (msb << 8) | lsb;<br>
> + while(remaining > 0) {<br>
> + READ_8254(lsb, msb);<br>
> + cur_tick = (msb << 8) | lsb;<br>
> + /* PIT counts down, so subtract cur from last */<br>
> + diff = last_tick - cur_tick;<br>
> + last_tick = cur_tick;<br>
> + if (diff < 0) {<br>
> + diff += max_timer_value;<br>
> + }<br>
> + remaining -= diff;<br>
> }<br>
><br>
> pc586_tsc_frequency = rdtsc() - begin_time;<br>
><br>
> #if 0<br>
> - printk( "CPU clock at %u MHz\n", (uint32_t)(pc586_tsc_frequency / 1000000));<br>
> + printk( "CPU clock at %u Hz\n", (uint32_t)(pc586_tsc_frequency ));<br>
> #endif<br>
> }<br>
><br>
> static void clockOn(void)<br>
> {<br>
> +<br>
> + /*<br>
> + * First calibrate the TSC. Do this every time we<br>
> + * turn the clock on in case the CPU clock speed has changed.<br>
> + */<br>
> + if ( x86_has_tsc() ) {<br>
> + calibrate_tsc();<br>
> + }<br>
> +<br>
> rtems_interrupt_lock_context lock_context;<br>
> pc386_isrs_per_tick = 1;<br>
> pc386_microseconds_per_isr = rtems_configuration_get_microseconds_per_tick();<br>
> @@ -171,13 +183,6 @@ static void clockOn(void)<br>
> rtems_interrupt_lock_release(&rtems_i386_i8254_access_lock, &lock_context);<br>
><br>
> bsp_interrupt_vector_enable( BSP_PERIODIC_TIMER );<br>
> -<br>
> - /*<br>
> - * Now calibrate cycles per tick. Do this every time we<br>
> - * turn the clock on in case the CPU clock speed has changed.<br>
> - */<br>
> - if ( x86_has_tsc() )<br>
> - calibrate_tsc();<br>
> }<br>
><br>
> bool Clock_isr_enabled = false;<br>
> --<br>
> 2.17.1<br>
><br>
> _______________________________________________<br>
> devel mailing list<br>
> <a href="mailto:devel@rtems.org" target="_blank">devel@rtems.org</a><br>
> <a href="http://lists.rtems.org/mailman/listinfo/devel" target="_blank">http://lists.rtems.org/mailman/listinfo/devel</a><br>
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