<div dir="auto">This looks generally ok but is all this visible to any application that includes bsp.h? <div dir="auto"><br></div><div dir="auto">It might all need to be moved into a separate header to avoid contaminating everyone's namespace.</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Jul 21, 2022, 10:56 AM Noor Aman <<a href="mailto:nooraman5718@gmail.com">nooraman5718@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div>A brief gist of what i found compatible with the older code</div><div>---COMPATIBLE HEADER---</div><div>- BCM2835 timer</div><div>- GPIO</div><div>- AUX</div><div>- GPU timer</div><div>---DIDNT CHECK---</div><div>- SPI</div><div>- I2C</div><div>---MINOR CHNAGE---</div><div>- IRQ</div><div>- FIQ</div><div>---NOT SURE ABOUT---</div><div>- Watchdog</div><div>- Power management</div><div>- Mailbox register<br></div><div><br></div><div>I didnt get any info about power management or watchdog or mailboxes. (It isnt in the BCM2835 Documention too I think??)</div><div><br></div><div>And to answer your question Alan about if the Aarch64 would require a DTB or not which you asked me quite earlier. I can say now, you dont, because every address is defined here already so no need for the DTB.<br></div><div><br></div><div><br></div><div><br></div><div>diff --git a/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h</div>index eeb48c42f1..a4ed2a01d1 100644<br>--- a/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h<br>+++ b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h<br>@@ -52,15 +52,23 @@<br> * @{<br> */<br> <br>-#if (BSP_IS_RPI2 == 1)<br>- #define RPI_PERIPHERAL_BASE 0x3F000000<br>+#if (RPI_BSP == RPI2)<br>+ #define RPI_PERIPHERAL_BASE 0X3F000000<br> #define BASE_OFFSET 0X3F000000<br>+<br>+#elif (RPI_BSP == RPI4)<br>+ #define RPI_PERIPHERAL_BASE 0xFE000000<br>+ #define BASE_OFFSET 0xFE000000<br>+ #define RPI_PERIPHERAL_SIZE 0x01800000<br>+<br> #else<br> #define RPI_PERIPHERAL_BASE 0x20000000<br> #define BASE_OFFSET 0X5E000000<br>+ <br> #endif<br> <br>-#define RPI_PERIPHERAL_SIZE 0x01000000<br>+#ifndef RPI_PERIPHERAL_SIZE<br>+#define RPI_PERIPHERAL_SIZE 0x01000000<br> <br> /**<br> * @name Bus to Physical address translation<br>@@ -543,6 +551,188 @@<br> #define BCM2836_IRQ_SOURCE_PMU 0x00000200<br> #define BCM2836_IRQ_SOURCE_LOCAL_TIMER 0x00000800<br> <br>+<br>+<br>+/**<br>+ * @name Raspberry Pi 4 ARM_LOCAL registers<br>+ *<br>+ * @{<br>+ */<br>+<br>+#define BCM2711_LOCAL_REGS_BASE 0x4C0000000<br>+<br>+#define BCM2711_LOCAL_ARM_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x00)<br>+#define BCM2711_LOCAL_CORE_IRQ_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x0c)<br>+#define BCM2711_LOCAL_PMU_CONTROL_SET (BCM2711_LOCAL_REGS_BASE + 0x10)<br>+#define BCM2711_LOCAL_PMU_CONTROL_CLR (BCM2711_LOCAL_REGS_BASE + 0x14)<br>+#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 (BCM2711_LOCAL_REGS_BASE + 0x24)<br>+#define BCM2711_LOCAL_AXI_QUIET_TIME (BCM2711_LOCAL_REGS_BASE + 0x30)<br>+#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x34)<br>+#define BCM2711_LOCAL_LOCAL_TIMER_IRQ (BCM2711_LOCAL_REGS_BASE + 0x38)<br>+<br>+#define BCM2711_LOCAL_TIMER_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x40)<br>+#define BCM2711_LOCAL_TIMER_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x44)<br>+#define BCM2711_LOCAL_TIMER_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x48)<br>+#define BCM2711_LOCAL_TIMER_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x4c)<br>+<br>+#define BCM2711_LOCAL_MAILBOX_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x50)<br>+#define BCM2711_LOCAL_MAILBOX_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x54)<br>+#define BCM2711_LOCAL_MAILBOX_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x58)<br>+#define BCM2711_LOCAL_MAILBOX_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x5c)<br>+<br>+#define BCM2711_LOCAL_IRQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x60)<br>+#define BCM2711_LOCAL_IRQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x64)<br>+#define BCM2711_LOCAL_IRQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x68)<br>+#define BCM2711_LOCAL_IRQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x6c)<br>+<br>+#define BCM2711_LOCAL_FIQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x70)<br>+#define BCM2711_LOCAL_FIQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x74)<br>+#define BCM2711_LOCAL_FIQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x78)<br>+#define BCM2711_LOCAL_FIQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x7c)<br>+<br>+<br>+/**<br>+ * @name Raspberry Pi 4 ARM_C FIQ and IRQ registers<br>+ *<br>+ * @{<br>+ */<br>+<br>+#define BCM2711_ARMC_REGS_BASE (RPI_PERIPHERAL_BASE + 0xB200)<br>+<br>+#define BCM2711_ARMC_IRQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x00) <br>+#define BCM2711_ARMC_IRQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x04) <br>+#define BCM2711_ARMC_IRQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x08) <br>+#define BCM2711_ARMC_IRQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x10) <br>+#define BCM2711_ARMC_IRQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x14) <br>+#define BCM2711_ARMC_IRQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x18) <br>+#define BCM2711_ARMC_IRQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x20) <br>+#define BCM2711_ARMC_IRQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x24) <br>+#define BCM2711_ARMC_IRQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x28) <br>+<br>+#define BCM2711_ARMC_IRQ_STATUS0 (BCM2711_ARMC_REGS_BASE + 0x30) <br>+#define BCM2711_ARMC_IRQ_STATUS1 (BCM2711_ARMC_REGS_BASE + 0x34) <br>+#define BCM2711_ARMC_IRQ_STATUS2 (BCM2711_ARMC_REGS_BASE + 0x38)<br>+<br>+#define BCM2711_ARMC_IRQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x40) <br>+#define BCM2711_ARMC_IRQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x44) <br>+#define BCM2711_ARMC_IRQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x48) <br>+#define BCM2711_ARMC_IRQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x50) <br>+#define BCM2711_ARMC_IRQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x54) <br>+#define BCM2711_ARMC_IRQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x58) <br>+#define BCM2711_ARMC_IRQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x60) <br>+#define BCM2711_ARMC_IRQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x64) <br>+#define BCM2711_ARMC_IRQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x68) <br>+<br>+#define BCM2711_ARMC_IRQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x80) <br>+#define BCM2711_ARMC_IRQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x84) <br>+#define BCM2711_ARMC_IRQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x88) <br>+#define BCM2711_ARMC_IRQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x90) <br>+#define BCM2711_ARMC_IRQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x94) <br>+#define BCM2711_ARMC_IRQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x98) <br>+#define BCM2711_ARMC_IRQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xA0) <br>+#define BCM2711_ARMC_IRQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xA4) <br>+#define BCM2711_ARMC_IRQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xA8) <br>+<br>+#define BCM2711_ARMC_IRQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0xC0) <br>+#define BCM2711_ARMC_IRQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0xC4) <br>+#define BCM2711_ARMC_IRQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0xC8) <br>+#define BCM2711_ARMC_IRQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0xD0) <br>+#define BCM2711_ARMC_IRQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0xD4) <br>+#define BCM2711_ARMC_IRQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0xD8) <br>+#define BCM2711_ARMC_IRQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xE0) <br>+#define BCM2711_ARMC_IRQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xE4) <br>+#define BCM2711_ARMC_IRQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xE8)<br>+<br>+<br>+<br>+#define BCM2711_ARMC_FIQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x100) <br>+#define BCM2711_ARMC_FIQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x104) <br>+#define BCM2711_ARMC_FIQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x108) <br>+#define BCM2711_ARMC_FIQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x110) <br>+#define BCM2711_ARMC_FIQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x114) <br>+#define BCM2711_ARMC_FIQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x118) <br>+#define BCM2711_ARMC_FIQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x120) <br>+#define BCM2711_ARMC_FIQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x124) <br>+#define BCM2711_ARMC_FIQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x128)<br>+<br>+#define BCM2711_ARMC_FIQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x140) <br>+#define BCM2711_ARMC_FIQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x144) <br>+#define BCM2711_ARMC_FIQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x148) <br>+#define BCM2711_ARMC_FIQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x150) <br>+#define BCM2711_ARMC_FIQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x154) <br>+#define BCM2711_ARMC_FIQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x158) <br>+#define BCM2711_ARMC_FIQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x160) <br>+#define BCM2711_ARMC_FIQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x164) <br>+#define BCM2711_ARMC_FIQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x168)<br>+<br>+#define BCM2711_ARMC_FIQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x180) <br>+#define BCM2711_ARMC_FIQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x184) <br>+#define BCM2711_ARMC_FIQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x188) <br>+#define BCM2711_ARMC_FIQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x190) <br>+#define BCM2711_ARMC_FIQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x194) <br>+#define BCM2711_ARMC_FIQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x198) <br>+#define BCM2711_ARMC_FIQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1A0) <br>+#define BCM2711_ARMC_FIQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1A4) <br>+#define BCM2711_ARMC_FIQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1A8)<br>+<br>+#define BCM2711_ARMC_FIQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x1C0) <br>+#define BCM2711_ARMC_FIQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x1C4) <br>+#define BCM2711_ARMC_FIQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x1C8) <br>+#define BCM2711_ARMC_FIQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1D0) <br>+#define BCM2711_ARMC_FIQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1D4) <br>+#define BCM2711_ARMC_FIQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1D8) <br>+#define BCM2711_ARMC_FIQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1E0) <br>+#define BCM2711_ARMC_FIQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1E4) <br>+#define BCM2711_ARMC_FIQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1E8)<br>+<br>+#define BCM2711_ARMC_SWIRQ_SET (BCM2711_ARMC_REGS_BASE + 0x1F0) <br>+#define BCM2711_ARMC_SWIRQ_CLEAR (BCM2711_ARMC_REGS_BASE + 0x1F4) <br>+ <br>+<br>+/**<br>+ * @name Raspberry Pi 4 Mailbox registers<br>+ *<br>+ * @{<br>+ */<br>+<br>+<br>+<br>+#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080<br>+#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084<br>+#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088<br>+#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C<br>+#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090<br>+#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094<br>+#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098<br>+#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C<br>+#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0<br>+#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4<br>+#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8<br>+#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC<br>+#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0<br>+#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4<br>+#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8<br>+#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC<br>+<br>+#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0<br>+#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4<br>+#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8<br>+#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC<br>+#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0<br>+#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4<br>+#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8<br>+#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC<br>+#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0<br>+#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4<br>+#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8<br>+#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC<br>+#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0<br>+#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4<br>+#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8<br>+#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC<br>+<br>+<br>+<br> /** @} */<br> <br> #endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */<br></div>
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