<div dir="ltr"><div dir="ltr">Hi Padmarao,<div>The patches apply cleanly and build for me. What is the recommended config.ini file for this BSP?</div><div>I used:</div><div>[riscv/mpfs64imafdc]<br>BUILD_TESTS=True<br>RTEMS_POSIX_API=True<br>RTEMS_SMP=True<br>BSP_START_COPY_FDT_FROM_U_BOOT=False<br>BSP_DTB_IS_SUPPORTED=True<br>BSP_DTB_HEADER_PATH=bsp/mpfs-dtb.h<br></div><div><br></div><div>I don't have a Polarfire SoC board, but is there a QEMU platform to run this on?</div><div><br></div><div>When this is in, I will rebase my k210 variant and eventually get it submitted!</div><div>Thanks,</div></div>Alan<div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Sep 19, 2022 at 9:00 AM Padmarao Begari <<a href="mailto:padmarao.begari@microchip.com">padmarao.begari@microchip.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">This patch set adds the Microchip PolarFire SoC BSP Variant<br>
support to RISC-V RTEMS.<br>
<br>
The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and<br>
a 64-bit RISC-V E51 monitor core SoC from Microchip, more<br>
info available here:<br>
<a href="https://www.microchip.com/en-us/products/fpgas-and-plds/" rel="noreferrer" target="_blank">https://www.microchip.com/en-us/products/fpgas-and-plds/</a><br>
system-on-chip-fpgas/polarfire-soc-fpgas#Overview<br>
<br>
This new BSP variant is added for the 4x U54 cores not for E51<br>
because the E51 monitor core is resreved for first stage<br>
bootloader (Hart Software Services).<br>
<br>
The boot HARTID configurable is implemented for the riscv BSP<br>
to work with individual hart(cpu core) or SMP.<br>
<br>
This BSP support components: 4 CPU Cores (U54), Interrupt<br>
controller (PLIC), Timer (CLINT), UART (16550-compatible)<br>
work fine on actual Microchip PolarFire SoC Icicle Kit.<br>
<br>
v2:<br>
- Add a license and copyright information in dtb header file<br>
- Use RISCV_BOOT_HARDID instead of RTEMS_BOOT_HARDID<br>
- Add '_RISCV_Map_hardid_to_cpu_index()' and<br>
'_RISCV_Map_cpu_index_to_hardid()' functions<br>
- Change bsp_fdt_get() instead of bsp_fdt_copy() function for dtb<br>
- Move dtb and dtb header configurable build option to the bsps<br>
<br>
Padmarao Begari (4):<br>
bsps/riscv: Add device tree blob<br>
spec/build/bsps: Add dtb support<br>
bsps/riscv: Add Microchip PolarFire SoC BSP variant<br>
bsps/shared/: Use device tree blob<br>
<br>
bsps/riscv/riscv/clock/clockdrv.c | 6 +-<br>
bsps/riscv/riscv/config/mpfs64imafdc.cfg | 9 +<br>
bsps/riscv/riscv/dts/mpfs.dts | 365 +++++++++++<br>
bsps/riscv/riscv/include/bsp/mpfs-dtb.h | 602 ++++++++++++++++++<br>
bsps/riscv/riscv/include/bsp/riscv.h | 14 +<br>
bsps/riscv/riscv/irq/irq.c | 81 +++<br>
bsps/riscv/riscv/start/bsp_fatal_halt.c | 3 +<br>
bsps/riscv/riscv/start/bspsmp.c | 2 +-<br>
bsps/riscv/riscv/start/bspstart.c | 19 +-<br>
bsps/riscv/shared/start/start.S | 2 +<br>
bsps/shared/start/bsp-fdt.c | 8 +<br>
.../score/cpu/riscv/include/rtems/score/cpu.h | 2 +-<br>
.../cpu/riscv/include/rtems/score/cpuimpl.h | 2 +-<br>
spec/build/bsps/optdtb.yml | 19 +<br>
spec/build/bsps/optdtbheaderpath.yml | 20 +<br>
spec/build/bsps/riscv/optextirqmax.yml | 5 +-<br>
spec/build/bsps/riscv/optrambegin.yml | 5 +-<br>
spec/build/bsps/riscv/optramsize.yml | 5 +-<br>
spec/build/bsps/riscv/riscv/abi.yml | 6 +<br>
.../bsps/riscv/riscv/bspmpfs64imafdc.yml | 19 +<br>
spec/build/bsps/riscv/riscv/grp.yml | 6 +<br>
spec/build/bsps/riscv/riscv/optmpfs.yml | 18 +<br>
spec/build/bsps/riscv/riscv/optns16550max.yml | 3 +<br>
spec/build/cpukit/cpuopts.yml | 2 +<br>
spec/build/cpukit/optarchbits.yml | 1 +<br>
spec/build/cpukit/optboothartid.yml | 19 +<br>
spec/build/cpukit/optsmp.yml | 1 +<br>
27 files changed, 1235 insertions(+), 9 deletions(-)<br>
create mode 100644 bsps/riscv/riscv/config/mpfs64imafdc.cfg<br>
create mode 100644 bsps/riscv/riscv/dts/mpfs.dts<br>
create mode 100644 bsps/riscv/riscv/include/bsp/mpfs-dtb.h<br>
create mode 100644 spec/build/bsps/optdtb.yml<br>
create mode 100644 spec/build/bsps/optdtbheaderpath.yml<br>
create mode 100644 spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml<br>
create mode 100644 spec/build/bsps/riscv/riscv/optmpfs.yml<br>
create mode 100644 spec/build/cpukit/optboothartid.yml<br>
<br>
-- <br>
2.25.1<br>
<br>
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</blockquote></div></div></div>