<div dir="auto"><div>Chris did you add it to the bsp-builder configuration?<br><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Sep 20, 2022, 11:51 PM <<a href="mailto:Padmarao.Begari@microchip.com">Padmarao.Begari@microchip.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Joel,<br>
<br>
> On Tue, 2022-09-20 at 12:03 -0500, Joel Sherrill wrote:<br>
> EXTERNAL EMAIL: Do not click links or open attachments unless you<br>
> know the content is safe<br>
> I have pushed this patch set. Please check that the merge is OK and<br>
> follow up with an update to the Users Guide for those looking for<br>
> this BSP.<br>
> <br>
<br>
Thank You.<br>
<br>
I have checked the merge is OK. Sure, will update the User Guide for<br>
this BSP.<br>
<br>
Thanks & Regards<br>
Padmarao<br>
<br>
> Thanks.<br>
> <br>
> On Tue, Sep 20, 2022 at 8:56 AM Joel Sherrill <<br>
> <a href="mailto:joel.sherrill@gmail.com" target="_blank" rel="noreferrer">joel.sherrill@gmail.com</a>> wrote:<br>
> > This procedure should be added to the Users Guide under the BSPs<br>
> > section.<br>
> > <br>
> > Otherwise, it looks like I should coordinate with Padmarao to make<br>
> > sure it's ok after I merged it<br>
> > <br>
> > On Tue, Sep 20, 2022, 1:50 AM <<a href="mailto:Padmarao.Begari@microchip.com" target="_blank" rel="noreferrer">Padmarao.Begari@microchip.com</a>><br>
> > wrote:<br>
> > > RTEMS SMP on the Microchip PolarFire Icicle Kit<br>
> > > <br>
> > > Test Procedure:<br>
> > > <br>
> > > 1. Create the "config.ini" file with below content at rtems root <br>
> > > <br>
> > > [riscv/mpfs64imafdc]<br>
> > > BUILD_TESTS = True<br>
> > > RTEMS_POSIX_API=True<br>
> > > RTEMS_SMP = True<br>
> > > BSP_START_COPY_FDT_FROM_U_BOOT=False<br>
> > > BSP_VERBOSE_FATAL_EXTENSION = False<br>
> > > <br>
> > > 2. Build RTEMS<br>
> > > $ ./waf configure --prefix=$HOME/rtems-start/rtems/6<br>
> > > $ ./waf<br>
> > > <br>
> > > 3. Convert .exe to .elf file<br>
> > > <br>
> > > $ riscv-rtems6-objcopy <br>
> > > build/riscv/mpfs64imafdc/testsuites/smptests/sm<br>
> > > p01.exe<br>
> > > build/riscv/mpfs64imafdc/testsuites/smptests/smp01.elf<br>
> > > <br>
> > > 4. Generate the payload for the smp01.elf using the hss-payload-<br>
> > > generator with hart-entry-points/exec-addr: 0x1000000000<br>
> > > <br>
> > > <a href="https://github.com/polarfire-soc/hart-software-services/tree/master/tools/hss-payload-generator" rel="noreferrer noreferrer" target="_blank">https://github.com/polarfire-soc/hart-software-services/tree/master/tools/hss-payload-generator</a><br>
> > > <br>
> > > 5. Programming the'payload.bin' for the eMMC/SD<br>
> > > <br>
> > > 5.1) Board setting and FPGA Programing<br>
> > > <br>
> > > <a href="https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md" rel="noreferrer noreferrer" target="_blank">https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md</a><br>
> > > <br>
> > > <br>
> > > 5.2). Power Cycle the Microchip PolarFire Icicle Kit and stop at<br>
> > > the <br>
> > > HSS.<br>
> > > <br>
> > > 5.3) type "mmc" and then "usbdmsc" on the HSS terminal(UART0).<br>
> > > <br>
> > > 5.4) Load payload from the Host PC.<br>
> > > $ sudo dd if=payload.bin of=/dev/sdb bs=512<br>
> > > <br>
> > > 5.5) Quit USB and Reset the Icicle Kit<br>
> > > <br>
> > > 5.6) Serial terminal UART1 displays the SMP example messages <br>
> > > <br>
> > > *** BEGIN OF TEST SMP 1 ***<br>
> > > *** TEST VERSION: 6.0.0.ef33f861e16de9bf4190a36e4d18062c7300986c<br>
> > > *** TEST STATE: EXPECTED_PASS<br>
> > > *** TEST BUILD: RTEMS_POSIX_API RTEMS_SMP<br>
> > > *** TEST TOOLS: 12.1.1 20220622 (RTEMS 6, RSB<br>
> > > 3cb78b0b815ba05d17f5c6<br>
> > > 5865d246a8333aa087, Newlib ea99f21)<br>
> > > <br>
> > > CPU 3 start task TA0<br>
> > > CPU 2 running Task TA0 <br>
> > > CPU 3 start task TA1<br>
> > > CPU 1 running Task TA1 <br>
> > > CPU 3 start task TA2<br>
> > > CPU 0 running Task TA2 <br>
> > > <br>
> > > *** END OF TEST SMP 1 ***<br>
> > > <br>
> > > Regards<br>
> > > Padmarao<br>
> > > On Mon, 2022-09-19 at 18:30 +0530, Padmarao Begari wrote:<br>
> > > > This patch set adds the Microchip PolarFire SoC BSP Variant<br>
> > > > support to RISC-V RTEMS.<br>
> > > > <br>
> > > > The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and<br>
> > > > a 64-bit RISC-V E51 monitor core SoC from Microchip, more<br>
> > > > info available here:<br>
> > > > <a href="https://www.microchip.com/en-us/products/fpgas-and-plds/" rel="noreferrer noreferrer" target="_blank">https://www.microchip.com/en-us/products/fpgas-and-plds/</a><br>
> > > > system-on-chip-fpgas/polarfire-soc-fpgas#Overview<br>
> > > > <br>
> > > > This new BSP variant is added for the 4x U54 cores not for E51<br>
> > > > because the E51 monitor core is resreved for first stage<br>
> > > > bootloader (Hart Software Services).<br>
> > > > <br>
> > > > The boot HARTID configurable is implemented for the riscv BSP<br>
> > > > to work with individual hart(cpu core) or SMP.<br>
> > > > <br>
> > > > This BSP support components: 4 CPU Cores (U54), Interrupt<br>
> > > > controller (PLIC), Timer (CLINT), UART (16550-compatible)<br>
> > > > work fine on actual Microchip PolarFire SoC Icicle Kit.<br>
> > > > <br>
> > > > v2:<br>
> > > > - Add a license and copyright information in dtb header file<br>
> > > > - Use RISCV_BOOT_HARDID instead of RTEMS_BOOT_HARDID<br>
> > > > - Add '_RISCV_Map_hardid_to_cpu_index()' and<br>
> > > > '_RISCV_Map_cpu_index_to_hardid()' functions<br>
> > > > - Change bsp_fdt_get() instead of bsp_fdt_copy() function for<br>
> > > dtb<br>
> > > > - Move dtb and dtb header configurable build option to the bsps<br>
> > > > <br>
> > > > Padmarao Begari (4):<br>
> > > > bsps/riscv: Add device tree blob<br>
> > > > spec/build/bsps: Add dtb support<br>
> > > > bsps/riscv: Add Microchip PolarFire SoC BSP variant<br>
> > > > bsps/shared/: Use device tree blob<br>
> > > > <br>
> > > > bsps/riscv/riscv/clock/clockdrv.c | 6 +-<br>
> > > > bsps/riscv/riscv/config/mpfs64imafdc.cfg | 9 +<br>
> > > > bsps/riscv/riscv/dts/mpfs.dts | 365<br>
> > > +++++++++++<br>
> > > > bsps/riscv/riscv/include/bsp/mpfs-dtb.h | 602<br>
> > > > ++++++++++++++++++<br>
> > > > bsps/riscv/riscv/include/bsp/riscv.h | 14 +<br>
> > > > bsps/riscv/riscv/irq/irq.c | 81 +++<br>
> > > > bsps/riscv/riscv/start/bsp_fatal_halt.c | 3 +<br>
> > > > bsps/riscv/riscv/start/bspsmp.c | 2 +-<br>
> > > > bsps/riscv/riscv/start/bspstart.c | 19 +-<br>
> > > > bsps/riscv/shared/start/start.S | 2 +<br>
> > > > bsps/shared/start/bsp-fdt.c | 8 +<br>
> > > > .../score/cpu/riscv/include/rtems/score/cpu.h | 2 +-<br>
> > > > .../cpu/riscv/include/rtems/score/cpuimpl.h | 2 +-<br>
> > > > spec/build/bsps/optdtb.yml | 19 +<br>
> > > > spec/build/bsps/optdtbheaderpath.yml | 20 +<br>
> > > > spec/build/bsps/riscv/optextirqmax.yml | 5 +-<br>
> > > > spec/build/bsps/riscv/optrambegin.yml | 5 +-<br>
> > > > spec/build/bsps/riscv/optramsize.yml | 5 +-<br>
> > > > spec/build/bsps/riscv/riscv/abi.yml | 6 +<br>
> > > > .../bsps/riscv/riscv/bspmpfs64imafdc.yml | 19 +<br>
> > > > spec/build/bsps/riscv/riscv/grp.yml | 6 +<br>
> > > > spec/build/bsps/riscv/riscv/optmpfs.yml | 18 +<br>
> > > > spec/build/bsps/riscv/riscv/optns16550max.yml | 3 +<br>
> > > > spec/build/cpukit/cpuopts.yml | 2 +<br>
> > > > spec/build/cpukit/optarchbits.yml | 1 +<br>
> > > > spec/build/cpukit/optboothartid.yml | 19 +<br>
> > > > spec/build/cpukit/optsmp.yml | 1 +<br>
> > > > 27 files changed, 1235 insertions(+), 9 deletions(-)<br>
> > > > create mode 100644 bsps/riscv/riscv/config/mpfs64imafdc.cfg<br>
> > > > create mode 100644 bsps/riscv/riscv/dts/mpfs.dts<br>
> > > > create mode 100644 bsps/riscv/riscv/include/bsp/mpfs-dtb.h<br>
> > > > create mode 100644 spec/build/bsps/optdtb.yml<br>
> > > > create mode 100644 spec/build/bsps/optdtbheaderpath.yml<br>
> > > > create mode 100644<br>
> > > spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml<br>
> > > > create mode 100644 spec/build/bsps/riscv/riscv/optmpfs.yml<br>
> > > > create mode 100644 spec/build/cpukit/optboothartid.yml<br>
> > > > <br>
> > > _______________________________________________<br>
> > > devel mailing list<br>
> > > <a href="mailto:devel@rtems.org" target="_blank" rel="noreferrer">devel@rtems.org</a><br>
> > > <a href="http://lists.rtems.org/mailman/listinfo/devel" rel="noreferrer noreferrer" target="_blank">http://lists.rtems.org/mailman/listinfo/devel</a><br>
> > > <br>
</blockquote></div></div></div>