<div dir="auto"><div><br><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sun, Sep 25, 2022, 7:43 PM Chris Johns <<a href="mailto:chrisj@rtems.org">chrisj@rtems.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi,<br>
<br>
Thanks for this. It is exciting to see this board being supported. Well done<br>
getting to a point we can review the changess. My comments are mostly about the<br>
commit message :)<br>
<br>
Is the BSP called `aarch64/raspberrypi4b`? I just want to make sure I am reading<br>
the spec files correctly.<br>
<br>
On 25/9/2022 2:44 am, Mohd Noor Aman wrote:<br>
> This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently only IPL64 ABI is supported. <br>
<br>
Please format this comment block to be less that 80 characters. I have updated<br>
our commit message documentation to be more specific.<br>
<br>
Should the first line be `bsp/raspberrypi: ...`?<br>
<br>
> IPL32 Supported will be added in the near future.<br>
<br>
Please say ...<br>
<br>
"IPL32 is not supported"<br></blockquote></div></div><div dir="auto"><br></div><div dir="auto">ILP32 and ILP64?</div><div dir="auto"><br></div><div dir="auto"><br></div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
... as that is correct and "near future" may turn into never. On the Versal<br>
IPL32 is not going to be supported because some resources need 64bit pointers.<br>
Let put in the history only what we have and know.<br></blockquote></div></div><div dir="auto"><br></div><div dir="auto">I was going to say I doubt anyone will ever want ilp32 on Pi4.</div><div dir="auto"><br></div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
> RAM starts from 0x80000 in the arm64 bit mode for Raspberry pi 4B, RAM extends to 1GB and MMU starts from 0x0.<br>
<br>
There are 1GB, 2GB, 4GB and 8G models. Which is supported?<br>
<br>
> All the IRQs are similiar to the older Raspberry pi 2 ARM BSP. Although newer GIC-400 related IRQs would be required in the near future.<br>
<br>
Please limit the comment to what is supported.<br>
<br>
> Only PL011 serial is supported as of now and that's too only for UART0. <br>
<br>
I do not understand the last part of this sentence<br>
<br>
> You'll need to disable default miniuart in order for that to work.<br>
<br>
Do we want this to work? I am not sure if this is a must requirement or not from<br>
this statement?<br>
<br>
Again thanks and well done<br>
<br>
Chris<br>
<br>
> The raspberrypi.h includes many of the address required for the future development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.<br>
<br>
> ---<br>
> bsps/aarch64/raspberrypi/console/console.c | 69 +++<br>
> bsps/aarch64/raspberrypi/include/bsp.h | 73 +++<br>
> bsps/aarch64/raspberrypi/include/bsp/irq.h | 109 ++++<br>
> .../raspberrypi/include/bsp/raspberrypi.h | 471 ++++++++++++++++++<br>
> bsps/aarch64/raspberrypi/include/tm27.h | 46 ++<br>
> bsps/aarch64/raspberrypi/start/bspstart.c | 49 ++<br>
> .../aarch64/raspberrypi/start/bspstarthooks.c | 53 ++<br>
> bsps/aarch64/raspberrypi/start/bspstartmmu.c | 84 ++++<br>
> spec/build/bsps/aarch64/raspberrypi/abi.yml | 21 +<br>
> .../aarch64/raspberrypi/bspraspberrypi4.yml | 81 +++<br>
> .../bsps/aarch64/raspberrypi/linkercmds.yml | 76 +++<br>
> 11 files changed, 1132 insertions(+)<br>
> create mode 100644 bsps/aarch64/raspberrypi/console/console.c<br>
> create mode 100644 bsps/aarch64/raspberrypi/include/bsp.h<br>
> create mode 100644 bsps/aarch64/raspberrypi/include/bsp/irq.h<br>
> create mode 100644 bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h<br>
> create mode 100644 bsps/aarch64/raspberrypi/include/tm27.h<br>
> create mode 100644 bsps/aarch64/raspberrypi/start/bspstart.c<br>
> create mode 100644 bsps/aarch64/raspberrypi/start/bspstarthooks.c<br>
> create mode 100644 bsps/aarch64/raspberrypi/start/bspstartmmu.c<br>
> create mode 100644 spec/build/bsps/aarch64/raspberrypi/abi.yml<br>
> create mode 100644 spec/build/bsps/aarch64/raspberrypi/bspraspberrypi4.yml<br>
> create mode 100644 spec/build/bsps/aarch64/raspberrypi/linkercmds.yml<br>
> <br>
> diff --git a/bsps/aarch64/raspberrypi/console/console.c b/bsps/aarch64/raspberrypi/console/console.c<br>
> new file mode 100644<br>
> index 0000000000..73bb0036ff<br>
> --- /dev/null<br>
> +++ b/bsps/aarch64/raspberrypi/console/console.c<br>
> @@ -0,0 +1,69 @@<br>
> +/* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> +/**<br>
> + * @file<br>
> + *<br>
> + * @ingroup RTEMSBSPsAArch64Raspberrypi4<br>
> + *<br>
> + * @brief Console Configuration<br>
> + */<br>
> +<br>
> +/*<br>
> + * Copyright (C) 2022 Mohd Noor Aman<br>
> + *<br>
> + *<br>
> + * Redistribution and use in source and binary forms, with or without<br>
> + * modification, are permitted provided that the following conditions<br>
> + * are met:<br>
> + * 1. Redistributions of source code must retain the above copyright<br>
> + * notice, this list of conditions and the following disclaimer.<br>
> + * 2. Redistributions in binary form must reproduce the above copyright<br>
> + * notice, this list of conditions and the following disclaimer in the<br>
> + * documentation and/or other materials provided with the distribution.<br>
> + *<br>
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
> + * POSSIBILITY OF SUCH DAMAGE.<br>
> + */<br>
> +<br>
> +#include <rtems/bspIo.h><br>
> +<br>
> +#include <bsp.h><br>
> +#include <dev/serial/arm-pl011.h><br>
> +#include <bsp/console-termios.h><br>
> +<br>
> +#include <bspopts.h><br>
> +<br>
> +arm_pl011_context raspberrypi_4_context = {<br>
> + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),<br>
> + .regs = (volatile pl011 *) BSP_RPI4_PL011_BASE,<br>
> + .initial_baud = 115200<br>
> +};<br>
> +<br>
> +const console_device console_device_table[] = {<br>
> + {<br>
> + .device_file = "/dev/ttyS0",<br>
> + .probe = console_device_probe_default,<br>
> + .handler = &arm_pl011_fns,<br>
> + .context = &raspberrypi_4_context.base<br>
> + }<br>
> +};<br>
> +<br>
> +const size_t console_device_count = RTEMS_ARRAY_SIZE(console_device_table);<br>
> +<br>
> +static void output_char( char c )<br>
> +{<br>
> + arm_pl011_write_polled(&raspberrypi_4_context.base, c);<br>
> +}<br>
> +<br>
> +BSP_output_char_function_type BSP_output_char = output_char;<br>
> +<br>
> +BSP_polling_getchar_function_type BSP_poll_char = NULL;<br>
> diff --git a/bsps/aarch64/raspberrypi/include/bsp.h b/bsps/aarch64/raspberrypi/include/bsp.h<br>
> new file mode 100644<br>
> index 0000000000..d94a0432d5<br>
> --- /dev/null<br>
> +++ b/bsps/aarch64/raspberrypi/include/bsp.h<br>
> @@ -0,0 +1,73 @@<br>
> +/* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> +/**<br>
> + * @file<br>
> + *<br>
> + * @ingroup RTEMSBSPsAArch64Raspberrypi4<br>
> + *<br>
> + * @brief Core BSP definitions<br>
> + */<br>
> +<br>
> +/*<br>
> + * Copyright (C) 2022 Mohd Noor Aman<br>
> + *<br>
> + *<br>
> + * Redistribution and use in source and binary forms, with or without<br>
> + * modification, are permitted provided that the following conditions<br>
> + * are met:<br>
> + * 1. Redistributions of source code must retain the above copyright<br>
> + * notice, this list of conditions and the following disclaimer.<br>
> + * 2. Redistributions in binary form must reproduce the above copyright<br>
> + * notice, this list of conditions and the following disclaimer in the<br>
> + * documentation and/or other materials provided with the distribution.<br>
> + *<br>
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
> + * POSSIBILITY OF SUCH DAMAGE.<br>
> + */<br>
> +<br>
> +#ifndef LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H<br>
> +#define LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H<br>
> +<br>
> +/**<br>
> + * @addtogroup RTEMSBSPsAArch64<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +#include <bspopts.h><br>
> +<br>
> +#ifndef ASM<br>
> +<br>
> +#include <bsp/default-initial-extension.h><br>
> +#include <bsp/start.h><br>
> +<br>
> +#include <rtems.h><br>
> +<br>
> +#ifdef __cplusplus<br>
> +extern "C" {<br>
> +#endif /* __cplusplus */<br>
> +<br>
> +#define BSP_ARM_GIC_CPUIF_BASE 0xFF842000<br>
> +#define BSP_ARM_GIC_DIST_BASE 0xFF841000<br>
> +<br>
> +#define BSP_RPI4_PL011_BASE 0xFE201000<br>
> +#define BSP_RPI4_PL011_LENGTH 0x200<br>
> +<br>
> +#ifdef __cplusplus<br>
> +}<br>
> +#endif /* __cplusplus */<br>
> +<br>
> +#endif /* ASM */<br>
> +<br>
> +/** @} */<br>
> +<br>
> +#endif /* LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H */<br>
> diff --git a/bsps/aarch64/raspberrypi/include/bsp/irq.h b/bsps/aarch64/raspberrypi/include/bsp/irq.h<br>
> new file mode 100644<br>
> index 0000000000..effec1b040<br>
> --- /dev/null<br>
> +++ b/bsps/aarch64/raspberrypi/include/bsp/irq.h<br>
> @@ -0,0 +1,109 @@<br>
> +/**<br>
> + * @file<br>
> + *<br>
> + * @ingroup raspberrypi_interrupt<br>
> + *<br>
> + * @brief Interrupt definitions.<br>
> + */<br>
> +<br>
> +/**<br>
> + * Copyright (c) 2013 Alan Cudmore<br>
> + * Copyright (c) 2022 Mohd Noor Aman<br>
> + *<br>
> + * The license and distribution terms for this file may be<br>
> + * found in the file LICENSE in this distribution or at<br>
> + *<br>
> + * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a><br>
> + *<br>
> + */<br>
> +<br>
> +#ifndef LIBBSP_ARM_RASPBERRYPI_IRQ_H<br>
> +#define LIBBSP_ARM_RASPBERRYPI_IRQ_H<br>
> +<br>
> +#ifndef ASM<br>
> +<br>
> +#include <rtems.h><br>
> +#include <rtems/irq.h><br>
> +#include <rtems/irq-extension.h><br>
> +#include <dev/irq/arm-gic-irq.h><br>
> +<br>
> +#if defined(RTEMS_SMP)<br>
> +#include <rtems/score/processormask.h><br>
> +#endif<br>
> +<br>
> +/**<br>
> + * @defgroup raspberrypi_interrupt Interrrupt Support<br>
> + *<br>
> + * @ingroup RTEMSBSPsARMRaspberryPi<br>
> + *<br>
> + * @brief Interrupt support.<br>
> + */<br>
> +<br>
> +#define BCM2835_INTC_TOTAL_IRQ (64 + 8)<br>
> +<br>
> +#define BCM2835_IRQ_SET1_MIN 0<br>
> +#define BCM2835_IRQ_SET2_MIN 32<br>
> +<br>
> +#define BCM2835_IRQ_ID_GPU_TIMER_M0 0<br>
> +#define BCM2835_IRQ_ID_GPU_TIMER_M1 1<br>
> +#define BCM2835_IRQ_ID_GPU_TIMER_M2 2<br>
> +#define BCM2835_IRQ_ID_GPU_TIMER_M3 3<br>
> +<br>
> +#define BCM2835_IRQ_ID_USB 9<br>
> +#define BCM2835_IRQ_ID_AUX 29<br>
> +#define BCM2835_IRQ_ID_SPI_SLAVE 43<br>
> +#define BCM2835_IRQ_ID_PWA0 45<br>
> +#define BCM2835_IRQ_ID_PWA1 46<br>
> +#define BCM2835_IRQ_ID_SMI 48<br>
> +#define BCM2835_IRQ_ID_GPIO_0 49<br>
> +#define BCM2835_IRQ_ID_GPIO_1 50<br>
> +#define BCM2835_IRQ_ID_GPIO_2 51<br>
> +#define BCM2835_IRQ_ID_GPIO_3 52<br>
> +#define BCM2835_IRQ_ID_I2C 53<br>
> +#define BCM2835_IRQ_ID_SPI 54<br>
> +#define BCM2835_IRQ_ID_PCM 55<br>
> +#define BCM2835_IRQ_ID_UART 57<br>
> +#define BCM2835_IRQ_ID_SD 62<br>
> +<br>
> +#define BCM2835_IRQ_ID_BASIC_BASE_ID 64<br>
> +#define BCM2835_IRQ_ID_TIMER_0 64<br>
> +#define BCM2835_IRQ_ID_MAILBOX_0 65<br>
> +#define BCM2835_IRQ_ID_DOORBELL_0 66<br>
> +#define BCM2835_IRQ_ID_DOORBELL_1 67<br>
> +#define BCM2835_IRQ_ID_GPU0_HALTED 68<br>
> +#define BCM2835_IRQ_ID_GPU1_HALTED 69<br>
> +#define BCM2835_IRQ_ID_ILL_ACCESS_1 70<br>
> +#define BCM2835_IRQ_ID_ILL_ACCESS_0 71<br>
> +#define BSP_TIMER_VIRT_PPI 27<br>
> +#define BSP_TIMER_PHYS_NS_PPI 30<br>
> +#define BSP_VPL011_SPI 32<br>
> +<br>
> +#define BSP_INTERRUPT_VECTOR_COUNT BCM2835_INTC_TOTAL_IRQ<br>
> +#define BSP_INTERRUPT_VECTOR_INVALID (UINT32_MAX)<br>
> +<br>
> +#define BSP_IRQ_COUNT (BCM2835_INTC_TOTAL_IRQ)<br>
> +<br>
> +#if defined(RTEMS_SMP)<br>
> +static inline rtems_status_code bsp_interrupt_set_affinity(<br>
> + rtems_vector_number vector,<br>
> + const Processor_mask *affinity<br>
> +)<br>
> +{<br>
> + (void) vector;<br>
> + (void) affinity;<br>
> + return RTEMS_UNSATISFIED;<br>
> +}<br>
> +<br>
> +static inline rtems_status_code bsp_interrupt_get_affinity(<br>
> + rtems_vector_number vector,<br>
> + Processor_mask *affinity<br>
> +)<br>
> +{<br>
> + (void) vector;<br>
> + _Processor_mask_From_index( affinity, 0 );<br>
> + return RTEMS_UNSATISFIED;<br>
> +}<br>
> +#endif<br>
> +<br>
> +#endif /* ASM */<br>
> +#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */<br>
> diff --git a/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h<br>
> new file mode 100644<br>
> index 0000000000..2cd851b5a2<br>
> --- /dev/null<br>
> +++ b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h<br>
> @@ -0,0 +1,471 @@<br>
> +/**<br>
> + * @file<br>
> + *<br>
> + * @ingroup raspberrypi_4_regs<br>
> + *<br>
> + * @brief Register definitions.<br>
> + */<br>
> +<br>
> +/*<br>
> + * Copyright (c) 2022 Mohd Noor Aman<br>
> + *<br>
> + * The license and distribution terms for this file may be<br>
> + * found in the file LICENSE in this distribution or at<br>
> + *<br>
> + * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a><br>
> + *<br>
> + */<br>
> +<br>
> +<br>
> +#ifndef LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H<br>
> +#define LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H<br>
> +<br>
> +<br>
> +#include <bspopts.h><br>
> +#include <stdint.h><br>
> +#include <bsp/utility.h><br>
> +<br>
> +<br>
> +/**<br>
> + * @defgroup raspberrypi_reg Register Definitions<br>
> + *<br>
> + * @ingroup RTEMSBSPsARMRaspberryPi<br>
> + *<br>
> + * @brief Register Definitions<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +/**<br>
> + * @name Register Macros<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +#define BCM2711_REG(x) (*(volatile uint64_t *)(x))<br>
> +#define BCM2711_BIT(n) (1 << (n))<br>
> +<br>
> +/** @} */<br>
> +<br>
> +/**<br>
> + * @name Peripheral Base Register Address<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +#define RPI_PERIPHERAL_BASE 0xFE000000<br>
> +#define BASE_OFFSET 0xFE000000<br>
> +#define RPI_PERIPHERAL_SIZE 0x01800000<br>
> +<br>
> +/**<br>
> + * @name Bus to Physical address translation<br>
> + * Macro.<br>
> + * @{<br>
> + */<br>
> +#define BUS_TO_PHY(x) ((x) - BASE_OFFSET)<br>
> +<br>
> +/** @} */<br>
> +<br>
> +/**<br>
> + * @name Internal ARM Timer Registers<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +#define BCM2711_CLOCK_FREQ 250000000<br>
> +<br>
> +#define BCM2711_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400)<br>
> +<br>
> +#define BCM2711_TIMER_LOD (BCM2711_TIMER_BASE + 0x00)<br>
> +#define BCM2711_TIMER_VAL (BCM2711_TIMER_BASE + 0x04)<br>
> +#define BCM2711_TIMER_CTL (BCM2711_TIMER_BASE + 0x08)<br>
> +#define BCM2711_TIMER_CLI (BCM2711_TIMER_BASE + 0x0C)<br>
> +#define BCM2711_TIMER_RIS (BCM2711_TIMER_BASE + 0x10)<br>
> +#define BCM2711_TIMER_MIS (BCM2711_TIMER_BASE + 0x14)<br>
> +#define BCM2711_TIMER_RLD (BCM2711_TIMER_BASE + 0x18)<br>
> +#define BCM2711_TIMER_DIV (BCM2711_TIMER_BASE + 0x1C)<br>
> +#define BCM2711_TIMER_CNT (BCM2711_TIMER_BASE + 0x20)<br>
> +<br>
> +#define BCM2711_TIMER_PRESCALE 0xF9<br>
> +<br>
> +/** @} */<br>
> +<br>
> +/**<br>
> + * @name Power Management and Watchdog Registers<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +#define BCM2711_PM_PASSWD_MAGIC 0x5a000000<br>
> +<br>
> +#define BCM2711_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000)<br>
> +<br>
> +#define BCM2711_PM_GNRIC (BCM2711_PM_BASE + 0x00)<br>
> +#define BCM2711_PM_GNRIC_POWUP 0x00000001<br>
> +#define BCM2711_PM_GNRIC_POWOK 0x00000002<br>
> +#define BCM2711_PM_GNRIC_ISPOW 0x00000004<br>
> +#define BCM2711_PM_GNRIC_MEMREP 0x00000008<br>
> +#define BCM2711_PM_GNRIC_MRDONE 0x00000010<br>
> +#define BCM2711_PM_GNRIC_ISFUNC 0x00000020<br>
> +#define BCM2711_PM_GNRIC_RSTN 0x00000fc0<br>
> +#define BCM2711_PM_GNRIC_ENAB 0x00001000<br>
> +#define BCM2711_PM_GNRIC_CFG 0x007f0000<br>
> +<br>
> +#define BCM2711_PM_AUDIO (BCM2711_PM_BASE + 0x04)<br>
> +#define BCM2711_PM_AUDIO_APSM 0x000fffff<br>
> +#define BCM2711_PM_AUDIO_CTRLEN 0x00100000<br>
> +#define BCM2711_PM_AUDIO_RSTN 0x00200000<br>
> +<br>
> +#define BCM2711_PM_STATUS (BCM2711_PM_BASE + 0x18)<br>
> +<br>
> +#define BCM2711_PM_RSTC (BCM2711_PM_BASE + 0x1c)<br>
> +#define BCM2711_PM_RSTC_DRCFG 0x00000003<br>
> +#define BCM2711_PM_RSTC_WRCFG 0x00000030<br>
> +#define BCM2711_PM_RSTC_WRCFG_FULL 0x00000020<br>
> +#define BCM2711_PM_RSTC_SRCFG 0x00000300<br>
> +#define BCM2711_PM_RSTC_QRCFG 0x00003000<br>
> +#define BCM2711_PM_RSTC_FRCFG 0x00030000<br>
> +#define BCM2711_PM_RSTC_HRCFG 0x00300000<br>
> +<br>
> +#define BCM2711_PM_RSTS (BCM2711_PM_BASE + 0x20)<br>
> +#define BCM2711_PM_RSTS_HADDRQ 0x00000001<br>
> +#define BCM2711_PM_RSTS_HADDRF 0x00000002<br>
> +#define BCM2711_PM_RSTS_HADDRH 0x00000004<br>
> +#define BCM2711_PM_RSTS_HADWRQ 0x00000010<br>
> +#define BCM2711_PM_RSTS_HADWRF 0x0000002<br>
> +#define BCM2711_PM_RSTS_HADWRH 0x00000040<br>
> +#define BCM2711_PM_RSTS_HADSRQ 0x00000100<br>
> +#define BCM2711_PM_RSTS_HADSRF 0x00000200<br>
> +#define BCM2711_PM_RSTS_HADSRH 0x00000400<br>
> +#define BCM2711_PM_RSTS_HADPOR 0x00001000<br>
> +<br>
> +#define BCM2711_PM_WDOG (BCM2711_PM_BASE + 0x24)<br>
> +<br>
> +/** @} */<br>
> +<br>
> +<br>
> +/** @} */<br>
> +<br>
> +/**<br>
> + * @name AUX Registers<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +#define BCM2711_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000)<br>
> +<br>
> +#define AUX_ENABLES (BCM2711_AUX_BASE + 0x04)<br>
> +#define AUX_MU_IO_REG (BCM2711_AUX_BASE + 0x40)<br>
> +#define AUX_MU_IER_REG (BCM2711_AUX_BASE + 0x44)<br>
> +#define AUX_MU_IIR_REG (BCM2711_AUX_BASE + 0x48)<br>
> +#define AUX_MU_LCR_REG (BCM2711_AUX_BASE + 0x4C)<br>
> +#define AUX_MU_MCR_REG (BCM2711_AUX_BASE + 0x50)<br>
> +#define AUX_MU_LSR_REG (BCM2711_AUX_BASE + 0x54)<br>
> +#define AUX_MU_MSR_REG (BCM2711_AUX_BASE + 0x58)<br>
> +#define AUX_MU_SCRATCH (BCM2711_AUX_BASE + 0x5C)<br>
> +#define AUX_MU_CNTL_REG (BCM2711_AUX_BASE + 0x60)<br>
> +#define AUX_MU_STAT_REG (BCM2711_AUX_BASE + 0x64)<br>
> +#define AUX_MU_BAUD_REG (BCM2711_AUX_BASE + 0x68)<br>
> +<br>
> +/** @} */<br>
> +<br>
> +<br>
> +<br>
> +/** @} */<br>
> +<br>
> +/**<br>
> + * @name GPU Timer Registers<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +/**<br>
> + * NOTE: The GPU uses Compare registers 0 and 2 for<br>
> + * it's own RTOS. 1 and 3 are available for use in<br>
> + * RTEMS.<br>
> + */<br>
> +#define BCM2711_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000)<br>
> +<br>
> +#define BCM2711_GPU_TIMER_CS (BCM2711_GPU_TIMER_BASE + 0x00)<br>
> +#define BCM2711_GPU_TIMER_CS_M0 0x00000001<br>
> +#define BCM2711_GPU_TIMER_CS_M1 0x00000002<br>
> +#define BCM2711_GPU_TIMER_CS_M2 0x00000004<br>
> +#define BCM2711_GPU_TIMER_CS_M3 0x00000008<br>
> +#define BCM2711_GPU_TIMER_CLO (BCM2711_GPU_TIMER_BASE + 0x04)<br>
> +#define BCM2711_GPU_TIMER_CHI (BCM2711_GPU_TIMER_BASE + 0x08)<br>
> +#define BCM2711_GPU_TIMER_C0 (BCM2711_GPU_TIMER_BASE + 0x0C)<br>
> +#define BCM2711_GPU_TIMER_C1 (BCM2711_GPU_TIMER_BASE + 0x10)<br>
> +#define BCM2711_GPU_TIMER_C2 (BCM2711_GPU_TIMER_BASE + 0x14)<br>
> +#define BCM2711_GPU_TIMER_C3 (BCM2711_GPU_TIMER_BASE + 0x18)<br>
> +<br>
> +/** @} */<br>
> +<br>
> +/**<br>
> + * @name EMMC Registers<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +/**<br>
> + * NOTE: Since the SD controller follows the SDHCI standard,<br>
> + * the rtems-libbsd tree already provides the remaining registers.<br>
> + */<br>
> +<br>
> +#define BCM2711_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000)<br>
> +<br>
> +/** @} */<br>
> +<br>
> +/**<br>
> +* @name Mailbox Registers<br>
> +*<br>
> +* @{<br>
> +*/<br>
> +<br>
> +#define BCM2711_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880)<br>
> +<br>
> +#define BCM2711_MBOX_READ (BCM2711_MBOX_BASE+0x00)<br>
> +#define BCM2711_MBOX_PEEK (BCM2711_MBOX_BASE+0x10)<br>
> +#define BCM2711_MBOX_SENDER (BCM2711_MBOX_BASE+0x14)<br>
> +#define BCM2711_MBOX_STATUS (BCM2711_MBOX_BASE+0x18)<br>
> +#define BCM2711_MBOX_WRITE (BCM2711_MBOX_BASE+0x20)<br>
> +#define BCM2711_MBOX_CONFIG (BCM2711_MBOX_BASE+0x1C)<br>
> +<br>
> +#define BCM2711_MBOX_RESPONSE 0x80000000<br>
> +#define BCM2711_MBOX_FULL 0x80000000<br>
> +#define BCM2711_MBOX_EMPTY 0x40000000<br>
> +<br>
> +/** @} */<br>
> +<br>
> +/**<br>
> +* @name Mailbox Channels<br>
> +*<br>
> +* @{<br>
> +*/<br>
> +<br>
> +/* Power Manager channel */<br>
> +#define BCM2711_MBOX_CHANNEL_PM 0<br>
> +/* Framebuffer channel */<br>
> +#define BCM2711_MBOX_CHANNEL_FB 1<br>
> + /* Virtual UART channel */<br>
> +#define BCM2711_MBOX_CHANNEL_VUART 2<br>
> + /* VCHIQ channel */<br>
> +#define BCM2711_MBOX_CHANNEL_VCHIQ 3<br>
> + /* LEDs channel */<br>
> +#define BCM2711_MBOX_CHANNEL_LED 4<br>
> + /* Button channel */<br>
> +#define BCM2711_MBOX_CHANNEL_BUTTON 5<br>
> + /* Touch screen channel */<br>
> +#define BCM2711_MBOX_CHANNEL_TOUCHS 6<br>
> +<br>
> +#define BCM2711_MBOX_CHANNEL_COUNT 7<br>
> +/* Property tags (ARM <-> VC) channel */<br>
> +#define BCM2711_MBOX_CHANNEL_PROP_AVC 8<br>
> + /* Property tags (VC <-> ARM) channel */<br>
> +#define BCM2711_MBOX_CHANNEL_PROP_VCA 9<br>
> +<br>
> +/** @} */<br>
> +<br>
> +<br>
> +<br>
> +/**<br>
> + * @name Raspberry Pi 2 Interrupt Register Defines<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +/* Timers interrupt control registers */<br>
> +#define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE 0xFF800040<br>
> +#define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE 0xFF800044<br>
> +#define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE 0xFF800048<br>
> +#define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE 0xFF80004C<br>
> +<br>
> +#define BCM2711_CORE_TIMER_IRQ_CTRL(cpuidx) \<br>
> + (BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))<br>
> +<br>
> +<br>
> +/**<br>
> + * @name Raspberry Pi 4 ARM_LOCAL registers<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +#define BCM2711_LOCAL_REGS_BASE 0x4C0000000<br>
> +#define BCM2711_LOCAL_REGS_SIZE 0x100<br>
> +<br>
> +#define BCM2711_LOCAL_ARM_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x00)<br>
> +#define BCM2711_LOCAL_CORE_IRQ_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x0c)<br>
> +#define BCM2711_LOCAL_PMU_CONTROL_SET (BCM2711_LOCAL_REGS_BASE + 0x10)<br>
> +#define BCM2711_LOCAL_PMU_CONTROL_CLR (BCM2711_LOCAL_REGS_BASE + 0x14)<br>
> +#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 (BCM2711_LOCAL_REGS_BASE + 0x24)<br>
> +#define BCM2711_LOCAL_AXI_QUIET_TIME (BCM2711_LOCAL_REGS_BASE + 0x30)<br>
> +#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x34)<br>
> +#define BCM2711_LOCAL_LOCAL_TIMER_IRQ (BCM2711_LOCAL_REGS_BASE + 0x38)<br>
> +<br>
> +#define BCM2711_LOCAL_TIMER_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x40)<br>
> +#define BCM2711_LOCAL_TIMER_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x44)<br>
> +#define BCM2711_LOCAL_TIMER_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x48)<br>
> +#define BCM2711_LOCAL_TIMER_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x4c)<br>
> +<br>
> +#define BCM2711_LOCAL_MAILBOX_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x50)<br>
> +#define BCM2711_LOCAL_MAILBOX_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x54)<br>
> +#define BCM2711_LOCAL_MAILBOX_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x58)<br>
> +#define BCM2711_LOCAL_MAILBOX_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x5c)<br>
> +<br>
> +#define BCM2711_LOCAL_IRQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x60)<br>
> +#define BCM2711_LOCAL_IRQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x64)<br>
> +#define BCM2711_LOCAL_IRQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x68)<br>
> +#define BCM2711_LOCAL_IRQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x6c)<br>
> +<br>
> +#define BCM2711_LOCAL_FIQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x70)<br>
> +#define BCM2711_LOCAL_FIQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x74)<br>
> +#define BCM2711_LOCAL_FIQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x78)<br>
> +#define BCM2711_LOCAL_FIQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x7c)<br>
> +<br>
> +/**<br>
> + * @name Raspberry Pi 4 Mailbox registers<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +<br>
> +<br>
> +#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080<br>
> +#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084<br>
> +#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088<br>
> +#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C<br>
> +#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090<br>
> +#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094<br>
> +#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098<br>
> +#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C<br>
> +#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0<br>
> +#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4<br>
> +#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8<br>
> +#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC<br>
> +#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0<br>
> +#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4<br>
> +#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8<br>
> +#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC<br>
> +<br>
> +#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0<br>
> +#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4<br>
> +#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8<br>
> +#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC<br>
> +#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0<br>
> +#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4<br>
> +#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8<br>
> +#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC<br>
> +#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0<br>
> +#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4<br>
> +#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8<br>
> +#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC<br>
> +#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0<br>
> +#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4<br>
> +#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8<br>
> +#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC<br>
> +<br>
> +<br>
> +/**<br>
> + * @name Raspberry Pi 4 ARM_C FIQ and IRQ registers<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +#define BCM2711_ARMC_REGS_BASE (RPI_PERIPHERAL_BASE + 0xB200)<br>
> +#define BCM2711_ARMC_REGS_SIZE 0x200<br>
> +<br>
> +#define BCM2711_ARMC_IRQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x00) <br>
> +#define BCM2711_ARMC_IRQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x04) <br>
> +#define BCM2711_ARMC_IRQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x08) <br>
> +#define BCM2711_ARMC_IRQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x10) <br>
> +#define BCM2711_ARMC_IRQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x14) <br>
> +#define BCM2711_ARMC_IRQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x18) <br>
> +#define BCM2711_ARMC_IRQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x20) <br>
> +#define BCM2711_ARMC_IRQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x24) <br>
> +#define BCM2711_ARMC_IRQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x28) <br>
> +<br>
> +#define BCM2711_ARMC_IRQ_STATUS0 (BCM2711_ARMC_REGS_BASE + 0x30) <br>
> +#define BCM2711_ARMC_IRQ_STATUS1 (BCM2711_ARMC_REGS_BASE + 0x34) <br>
> +#define BCM2711_ARMC_IRQ_STATUS2 (BCM2711_ARMC_REGS_BASE + 0x38)<br>
> +<br>
> +#define BCM2711_ARMC_IRQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x40) <br>
> +#define BCM2711_ARMC_IRQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x44) <br>
> +#define BCM2711_ARMC_IRQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x48) <br>
> +#define BCM2711_ARMC_IRQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x50) <br>
> +#define BCM2711_ARMC_IRQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x54) <br>
> +#define BCM2711_ARMC_IRQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x58) <br>
> +#define BCM2711_ARMC_IRQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x60) <br>
> +#define BCM2711_ARMC_IRQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x64) <br>
> +#define BCM2711_ARMC_IRQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x68) <br>
> +<br>
> +#define BCM2711_ARMC_IRQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x80) <br>
> +#define BCM2711_ARMC_IRQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x84) <br>
> +#define BCM2711_ARMC_IRQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x88) <br>
> +#define BCM2711_ARMC_IRQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x90) <br>
> +#define BCM2711_ARMC_IRQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x94) <br>
> +#define BCM2711_ARMC_IRQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x98) <br>
> +#define BCM2711_ARMC_IRQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xA0) <br>
> +#define BCM2711_ARMC_IRQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xA4) <br>
> +#define BCM2711_ARMC_IRQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xA8) <br>
> +<br>
> +#define BCM2711_ARMC_IRQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0xC0) <br>
> +#define BCM2711_ARMC_IRQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0xC4) <br>
> +#define BCM2711_ARMC_IRQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0xC8) <br>
> +#define BCM2711_ARMC_IRQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0xD0) <br>
> +#define BCM2711_ARMC_IRQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0xD4) <br>
> +#define BCM2711_ARMC_IRQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0xD8) <br>
> +#define BCM2711_ARMC_IRQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xE0) <br>
> +#define BCM2711_ARMC_IRQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xE4) <br>
> +#define BCM2711_ARMC_IRQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xE8)<br>
> +<br>
> +<br>
> +<br>
> +#define BCM2711_ARMC_FIQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x100) <br>
> +#define BCM2711_ARMC_FIQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x104) <br>
> +#define BCM2711_ARMC_FIQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x108) <br>
> +#define BCM2711_ARMC_FIQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x110) <br>
> +#define BCM2711_ARMC_FIQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x114) <br>
> +#define BCM2711_ARMC_FIQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x118) <br>
> +#define BCM2711_ARMC_FIQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x120) <br>
> +#define BCM2711_ARMC_FIQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x124) <br>
> +#define BCM2711_ARMC_FIQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x128)<br>
> +<br>
> +#define BCM2711_ARMC_FIQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x140) <br>
> +#define BCM2711_ARMC_FIQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x144) <br>
> +#define BCM2711_ARMC_FIQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x148) <br>
> +#define BCM2711_ARMC_FIQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x150) <br>
> +#define BCM2711_ARMC_FIQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x154) <br>
> +#define BCM2711_ARMC_FIQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x158) <br>
> +#define BCM2711_ARMC_FIQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x160) <br>
> +#define BCM2711_ARMC_FIQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x164) <br>
> +#define BCM2711_ARMC_FIQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x168)<br>
> +<br>
> +#define BCM2711_ARMC_FIQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x180) <br>
> +#define BCM2711_ARMC_FIQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x184) <br>
> +#define BCM2711_ARMC_FIQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x188) <br>
> +#define BCM2711_ARMC_FIQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x190) <br>
> +#define BCM2711_ARMC_FIQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x194) <br>
> +#define BCM2711_ARMC_FIQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x198) <br>
> +#define BCM2711_ARMC_FIQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1A0) <br>
> +#define BCM2711_ARMC_FIQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1A4) <br>
> +#define BCM2711_ARMC_FIQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1A8)<br>
> +<br>
> +#define BCM2711_ARMC_FIQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x1C0) <br>
> +#define BCM2711_ARMC_FIQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x1C4) <br>
> +#define BCM2711_ARMC_FIQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x1C8) <br>
> +#define BCM2711_ARMC_FIQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1D0) <br>
> +#define BCM2711_ARMC_FIQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1D4) <br>
> +#define BCM2711_ARMC_FIQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1D8) <br>
> +#define BCM2711_ARMC_FIQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1E0) <br>
> +#define BCM2711_ARMC_FIQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1E4) <br>
> +#define BCM2711_ARMC_FIQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1E8)<br>
> +<br>
> +#define BCM2711_ARMC_SWIRQ_SET (BCM2711_ARMC_REGS_BASE + 0x1F0) <br>
> +#define BCM2711_ARMC_SWIRQ_CLEAR (BCM2711_ARMC_REGS_BASE + 0x1F4) <br>
> + <br>
> +<br>
> +<br>
> +<br>
> +<br>
> +/** @} */<br>
> +<br>
> +#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */<br>
> diff --git a/bsps/aarch64/raspberrypi/include/tm27.h b/bsps/aarch64/raspberrypi/include/tm27.h<br>
> new file mode 100644<br>
> index 0000000000..653f88ed01<br>
> --- /dev/null<br>
> +++ b/bsps/aarch64/raspberrypi/include/tm27.h<br>
> @@ -0,0 +1,46 @@<br>
> +/* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> +/**<br>
> + * @file<br>
> + *<br>
> + * @ingroup RTEMSBSPsAArch64Raspberrypi4<br>
> + *<br>
> + * @brief BSP tm27 header<br>
> + */<br>
> +<br>
> +/*<br>
> + * Copyright (C) 2022 Mohd Noor Aman<br>
> + *<br>
> + *<br>
> + * Redistribution and use in source and binary forms, with or without<br>
> + * modification, are permitted provided that the following conditions<br>
> + * are met:<br>
> + * 1. Redistributions of source code must retain the above copyright<br>
> + * notice, this list of conditions and the following disclaimer.<br>
> + * 2. Redistributions in binary form must reproduce the above copyright<br>
> + * notice, this list of conditions and the following disclaimer in the<br>
> + * documentation and/or other materials provided with the distribution.<br>
> + *<br>
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
> + * POSSIBILITY OF SUCH DAMAGE.<br>
> + */<br>
> +<br>
> +#ifndef _RTEMS_TMTEST27<br>
> +#error "This is an RTEMS internal file you must not include directly."<br>
> +#endif<br>
> +<br>
> +#ifndef __tm27_h<br>
> +#define __tm27_h<br>
> +<br>
> +#include <dev/irq/arm-gic-tm27.h><br>
> +<br>
> +#endif /* __tm27_h */<br>
> \ No newline at end of file<br>
> diff --git a/bsps/aarch64/raspberrypi/start/bspstart.c b/bsps/aarch64/raspberrypi/start/bspstart.c<br>
> new file mode 100644<br>
> index 0000000000..56f52a2231<br>
> --- /dev/null<br>
> +++ b/bsps/aarch64/raspberrypi/start/bspstart.c<br>
> @@ -0,0 +1,49 @@<br>
> +/* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> +/**<br>
> + * @file<br>
> + *<br>
> + * @ingroup RTEMSBSPsAArch64Raspberrypi4<br>
> + *<br>
> + * @brief BSP Startup<br>
> + */<br>
> +<br>
> +/*<br>
> + * Copyright (C) 2022 Mohd Noor Aman<br>
> + * <br>
> + *<br>
> + * Redistribution and use in source and binary forms, with or without<br>
> + * modification, are permitted provided that the following conditions<br>
> + * are met:<br>
> + * 1. Redistributions of source code must retain the above copyright<br>
> + * notice, this list of conditions and the following disclaimer.<br>
> + * 2. Redistributions in binary form must reproduce the above copyright<br>
> + * notice, this list of conditions and the following disclaimer in the<br>
> + * documentation and/or other materials provided with the distribution.<br>
> + *<br>
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
> + * POSSIBILITY OF SUCH DAMAGE.<br>
> + */<br>
> +<br>
> +#include <bsp.h><br>
> +#include <bsp/bootcard.h><br>
> +#include <bsp/irq-generic.h><br>
> +#include <bsp/linker-symbols.h><br>
> +<br>
> +void bsp_start( void )<br>
> +{<br>
> + bsp_interrupt_initialize();<br>
> + rtems_cache_coherent_add_area(<br>
> + bsp_section_nocacheheap_begin,<br>
> + (uintptr_t) bsp_section_nocacheheap_size<br>
> + );<br>
> +}<br>
> diff --git a/bsps/aarch64/raspberrypi/start/bspstarthooks.c b/bsps/aarch64/raspberrypi/start/bspstarthooks.c<br>
> new file mode 100644<br>
> index 0000000000..fe0fe77c09<br>
> --- /dev/null<br>
> +++ b/bsps/aarch64/raspberrypi/start/bspstarthooks.c<br>
> @@ -0,0 +1,53 @@<br>
> +/* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> +/**<br>
> + * @file<br>
> + *<br>
> + * @ingroup RTEMSBSPsAArch64Raspberrypi4<br>
> + *<br>
> + * @brief BSP Startup Hooks<br>
> + */<br>
> +<br>
> +/*<br>
> + * Copyright (C) 2022 Mohd Noor Aman<br>
> + *<br>
> + *<br>
> + * Redistribution and use in source and binary forms, with or without<br>
> + * modification, are permitted provided that the following conditions<br>
> + * are met:<br>
> + * 1. Redistributions of source code must retain the above copyright<br>
> + * notice, this list of conditions and the following disclaimer.<br>
> + * 2. Redistributions in binary form must reproduce the above copyright<br>
> + * notice, this list of conditions and the following disclaimer in the<br>
> + * documentation and/or other materials provided with the distribution.<br>
> + *<br>
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
> + * POSSIBILITY OF SUCH DAMAGE.<br>
> + */<br>
> +<br>
> +#include <bsp.h><br>
> +#include <bsp/irq-generic.h><br>
> +#include <bsp/start.h><br>
> +#include <rtems/score/cpu.h><br>
> +<br>
> +BSP_START_TEXT_SECTION void bsp_start_hook_0(void)<br>
> +{<br>
> + /* Do nothing */<br>
> +}<br>
> +<br>
> +BSP_START_TEXT_SECTION void bsp_start_hook_1(void)<br>
> +{<br>
> + AArch64_start_set_vector_base();<br>
> + bsp_start_copy_sections();<br>
> + raspberrypi_4_setup_mmu_and_cache();<br>
> + bsp_start_clear_bss();<br>
> +}<br>
> \ No newline at end of file<br>
> diff --git a/bsps/aarch64/raspberrypi/start/bspstartmmu.c b/bsps/aarch64/raspberrypi/start/bspstartmmu.c<br>
> new file mode 100644<br>
> index 0000000000..ab12020a2a<br>
> --- /dev/null<br>
> +++ b/bsps/aarch64/raspberrypi/start/bspstartmmu.c<br>
> @@ -0,0 +1,84 @@<br>
> +/* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> +/**<br>
> + * @file<br>
> + *<br>
> + * @ingroup RTEMSBSPsAArch64Raspberrypi4<br>
> + *<br>
> + * @brief This source file contains the default MMU tables and setup.<br>
> + */<br>
> +<br>
> +/*<br>
> + * Copyright (C) 2022 Mohd Noor Aman<br>
> + *<br>
> + *<br>
> + * Redistribution and use in source and binary forms, with or without<br>
> + * modification, are permitted provided that the following conditions<br>
> + * are met:<br>
> + * 1. Redistributions of source code must retain the above copyright<br>
> + * notice, this list of conditions and the following disclaimer.<br>
> + * 2. Redistributions in binary form must reproduce the above copyright<br>
> + * notice, this list of conditions and the following disclaimer in the<br>
> + * documentation and/or other materials provided with the distribution.<br>
> + *<br>
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
> + * POSSIBILITY OF SUCH DAMAGE.<br>
> + */<br>
> +<br>
> +#include <bsp.h><br>
> +#include <bsp/start.h><br>
> +#include <bsp/aarch64-mmu.h><br>
> +#include <bsp/raspberrypi.h><br>
> +#include <libcpu/mmu-vmsav8-64.h><br>
> +<br>
> +<br>
> +BSP_START_DATA_SECTION static const aarch64_mmu_config_entry<br>
> +raspberrypi_4_mmu_config_table[] = {<br>
> + AARCH64_MMU_DEFAULT_SECTIONS,<br>
> + <br>
> + { /* RPI peripheral address */<br>
> + .begin = (unsigned)RPI_PERIPHERAL_BASE,<br>
> + .end = (unsigned)RPI_PERIPHERAL_BASE + (unsigned)RPI_PERIPHERAL_SIZE,<br>
> + .flags = AARCH64_MMU_DEVICE<br>
> + },<br>
> +<br>
> + { /* RPI ARM local registers */<br>
> + .begin = (unsigned)BCM2711_LOCAL_REGS_BASE,<br>
> + .end = (unsigned)BCM2711_LOCAL_REGS_BASE + (unsigned)BCM2711_LOCAL_REGS_SIZE,<br>
> + .flags = AARCH64_MMU_DEVICE<br>
> + },<br>
> +<br>
> + { /* RPI GIC Interface address */<br>
> + .begin = 0xFF800000U,<br>
> + .end = 0xFFA00000U,<br>
> + .flags = AARCH64_MMU_DEVICE<br>
> + }<br>
> +<br>
> +};<br>
> +/*<br>
> + * Make weak and let the user override.<br>
> + */<br>
> +BSP_START_TEXT_SECTION void<br>
> +raspberrypi_4_setup_mmu_and_cache( void ) __attribute__ ((weak));<br>
> +<br>
> +BSP_START_TEXT_SECTION void<br>
> +raspberrypi_4_setup_mmu_and_cache( void )<br>
> +{<br>
> + aarch64_mmu_setup();<br>
> +<br>
> + aarch64_mmu_setup_translation_table(<br>
> + &raspberrypi_4_mmu_config_table[ 0 ],<br>
> + RTEMS_ARRAY_SIZE( raspberrypi_4_mmu_config_table )<br>
> + );<br>
> +<br>
> + aarch64_mmu_enable();<br>
> +}<br>
> \ No newline at end of file<br>
> diff --git a/spec/build/bsps/aarch64/raspberrypi/abi.yml b/spec/build/bsps/aarch64/raspberrypi/abi.yml<br>
> new file mode 100644<br>
> index 0000000000..5e3e0a4975<br>
> --- /dev/null<br>
> +++ b/spec/build/bsps/aarch64/raspberrypi/abi.yml<br>
> @@ -0,0 +1,21 @@<br>
> +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>
> +actions:<br>
> +- get-string: null<br>
> +- split: null<br>
> +- env-append: null<br>
> +build-type: option<br>
> +copyrights:<br>
> +- Copyright (C) 2022 Mohd Noor Aman<br>
> +default:<br>
> +- -mcpu=cortex-a72<br>
> +- -march=armv8-a <br>
> +<br>
> +default-by-variant: []<br>
> +includes: []<br>
> +description: |<br>
> + ABI flags<br>
> +links: []<br>
> +enabled-by: true<br>
> +name: ABI_FLAGS<br>
> +type: build<br>
> + <br>
> \ No newline at end of file<br>
> diff --git a/spec/build/bsps/aarch64/raspberrypi/bspraspberrypi4.yml b/spec/build/bsps/aarch64/raspberrypi/bspraspberrypi4.yml<br>
> new file mode 100644<br>
> index 0000000000..d2ff76d351<br>
> --- /dev/null<br>
> +++ b/spec/build/bsps/aarch64/raspberrypi/bspraspberrypi4.yml<br>
> @@ -0,0 +1,81 @@<br>
> +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>
> +arch: aarch64<br>
> +bsp: raspberrypi4b<br>
> +build-type: bsp<br>
> +cflags: []<br>
> +copyrights:<br>
> +- Copyright (C) 2022 Mohd Noor Aman<br>
> +cppflags: []<br>
> +enabled-by: true<br>
> +family: raspberrypi<br>
> +includes: []<br>
> +install:<br>
> +- destination: ${BSP_INCLUDEDIR}<br>
> + source:<br>
> + - bsps/aarch64/raspberrypi/include/bsp.h<br>
> + - bsps/aarch64/raspberrypi/include/tm27.h<br>
> +<br>
> +- destination: ${BSP_INCLUDEDIR}/bsp<br>
> + source:<br>
> + - bsps/aarch64/raspberrypi/include/bsp/irq.h<br>
> + - bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h<br>
> +<br>
> +source:<br>
> +- bsps/aarch64/raspberrypi/console/console.c<br>
> +- bsps/aarch64/raspberrypi/start/bspstart.c<br>
> +- bsps/aarch64/raspberrypi/start/bspstarthooks.c<br>
> +- bsps/aarch64/raspberrypi/start/bspstartmmu.c<br>
> +- bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c<br>
> +- bsps/aarch64/shared/cache/cache.c<br>
> +- bsps/aarch64/shared/mmu/vmsav8-64.c<br>
> +- bsps/shared/dev/clock/arm-generic-timer.c<br>
> +- bsps/shared/dev/irq/arm-gicv2.c<br>
> +- bsps/shared/dev/irq/arm-gicv2-get-attributes.c<br>
> +- bsps/shared/dev/serial/console-termios-init.c<br>
> +- bsps/shared/dev/serial/console-termios.c<br>
> +- bsps/shared/dev/serial/arm-pl011.c<br>
> +- bsps/shared/dev/getentropy/getentropy-cpucounter.c<br>
> +- bsps/shared/dev/btimer/btimer-cpucounter.c<br>
> +- bsps/shared/irq/irq-default-handler.c<br>
> +- bsps/shared/irq/irq-handler-install.c<br>
> +- bsps/shared/irq/irq-generic.c<br>
> +- bsps/shared/irq/irq-lock.c<br>
> +- bsps/shared/start/bspfatal-default.c<br>
> +- bsps/shared/start/bspreset-arm-psci.c<br>
> +- bsps/shared/start/gettargethash-default.c<br>
> +- bsps/shared/start/sbrk.c<br>
> +- bsps/shared/start/wkspaceinitone.c<br>
> +- bsps/shared/start/mallocinitmulti.c<br>
> +- bsps/shared/start/bspgetworkarea-default.c<br>
> +<br>
> +links:<br>
> +- role: build-dependency<br>
> + uid: ../grp<br>
> +- role: build-dependency<br>
> + uid: ../start<br>
> +- role: build-dependency<br>
> + uid: ../optmmupages<br>
> +- role: build-dependency<br>
> + uid: ../optgtusevirt<br>
> +- role: build-dependency<br>
> + uid: ../optgtuseps<br>
> +- role: build-dependency<br>
> + uid: abi<br>
> +- role: build-dependency<br>
> + uid: ../../optcachedata<br>
> +- role: build-dependency<br>
> + uid: ../../optcacheinst<br>
> +- role: build-dependency<br>
> + uid: ../../opto2<br>
> +- role: build-dependency<br>
> + uid: ../../bspopts<br>
> +- role: build-dependency<br>
> + uid: linkercmds<br>
> +- role: build-dependency<br>
> + uid: ../../obj<br>
> +- role: build-dependency<br>
> + uid: ../../objirq<br>
> + <br>
> +type: build<br>
> +<br>
> +<br>
> diff --git a/spec/build/bsps/aarch64/raspberrypi/linkercmds.yml b/spec/build/bsps/aarch64/raspberrypi/linkercmds.yml<br>
> new file mode 100644<br>
> index 0000000000..8598b89cba<br>
> --- /dev/null<br>
> +++ b/spec/build/bsps/aarch64/raspberrypi/linkercmds.yml<br>
> @@ -0,0 +1,76 @@<br>
> +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>
> +build-type: config-file<br>
> +content: |<br>
> + /* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> + /*<br>
> + * Copyright (C) 2022 Mohd Noor Aman <br>
> + *<br>
> + * Redistribution and use in source and binary forms, with or without<br>
> + * modification, are permitted provided that the following conditions<br>
> + * are met:<br>
> + * 1. Redistributions of source code must retain the above copyright<br>
> + * notice, this list of conditions and the following disclaimer.<br>
> + * 2. Redistributions in binary form must reproduce the above copyright<br>
> + * notice, this list of conditions and the following disclaimer in the<br>
> + * documentation and/or other materials provided with the distribution.<br>
> + *<br>
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
> + * POSSIBILITY OF SUCH DAMAGE.<br>
> + */<br>
> +<br>
> + MEMORY {<br>
> + RAM_MMU : ORIGIN = 0x0, LENGTH = (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})<br>
> + RAM : ORIGIN = 0x80000, LENGTH = 1024M<br>
> + }<br>
> +<br>
> + REGION_ALIAS ("REGION_START", RAM);<br>
> + REGION_ALIAS ("REGION_VECTOR", RAM);<br>
> + REGION_ALIAS ("REGION_TEXT", RAM);<br>
> + REGION_ALIAS ("REGION_TEXT_LOAD", RAM);<br>
> + REGION_ALIAS ("REGION_RODATA", RAM);<br>
> + REGION_ALIAS ("REGION_RODATA_LOAD", RAM);<br>
> + REGION_ALIAS ("REGION_DATA", RAM);<br>
> + REGION_ALIAS ("REGION_DATA_LOAD", RAM);<br>
> + REGION_ALIAS ("REGION_FAST_TEXT", RAM);<br>
> + REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);<br>
> + REGION_ALIAS ("REGION_FAST_DATA", RAM);<br>
> + REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);<br>
> + REGION_ALIAS ("REGION_BSS", RAM);<br>
> + REGION_ALIAS ("REGION_WORK", RAM);<br>
> + REGION_ALIAS ("REGION_STACK", RAM);<br>
> + REGION_ALIAS ("REGION_NOCACHE", RAM);<br>
> + REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM);<br>
> +<br>
> + bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;<br>
> +<br>
> + bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;<br>
> +<br>
> + bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 1024;<br>
> +<br>
> + bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;<br>
> +<br>
> + bsp_vector_table_in_start_section = 1;<br>
> + bsp_translation_table_base = ORIGIN (RAM_MMU);<br>
> + bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);<br>
> +<br>
> + OUTPUT_FORMAT ("elf64-littleaarch64")<br>
> + OUTPUT_ARCH (aarch64)<br>
> +<br>
> + INCLUDE linkcmds.base<br>
> +copyrights:<br>
> +- Copyright (C) 2022 Mohd Noor Aman<br>
> +enabled-by: true<br>
> +install-path: ${BSP_LIBDIR}<br>
> +links: []<br>
> +target: linkcmds<br>
> +type: build<br>
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</blockquote></div></div></div>