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--></style></head><body lang=EN-US link=blue vlink="#954F72" style='word-wrap:break-word'><div class=WordSection1><p class=MsoNormal>I agree – I am working on a riscv BSP variant (Sipeed MAIX Bit with K210 CPU) where the RTEMS image can be flashed directly to the board and boots without a bootloader.</p><p class=MsoNormal>I was also wondering if the statement “<span style='color:#404040;background:#FCFCFC'>Each variant corresponds to a GCC multilib” is still accurate as BSP variants such as the FE310Arty and Microchip Polarfire are added?<o:p></o:p></span></p><p class=MsoNormal><span style='color:#404040;background:#FCFCFC'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='color:#404040;background:#FCFCFC'>Alan<o:p></o:p></span></p><div style='mso-element:para-border-div;border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal style='border:none;padding:0in'><b>From: </b><a href="mailto:heshamelmatary@gmail.com">heshamelmatary@gmail.com</a><br><b>Sent: </b>Tuesday, October 25, 2022 1:48 PM<br><b>To: </b><a href="mailto:devel@rtems.org">devel@rtems.org</a><br><b>Subject: </b>[PATCH 1/2] bsps/riscv: Remove inaccurate statement about reliance on a boot loader</p></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>From: Hesham Almatary <hesham.almatary@cl.cam.ac.uk></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The BSP is capable of initialising the hardware being the first software</p><p class=MsoNormal>that takes control on hardware reset (after the bootrom). For instance,</p><p class=MsoNormal>using on QEMU's virt platforms, RTEMS runs as a bios without BBL.</p><p class=MsoNormal>Similarily, RTEMS can also be run on harware/FPGA and loaded using</p><p class=MsoNormal>GDB; the bootrom (or a GDB script) should just set the a0/a1 registers</p><p class=MsoNormal>with the boot HART ID and DTB address respectively.</p><p class=MsoNormal>---</p><p class=MsoNormal> user/bsps/bsps-riscv.rst | 4 +---</p><p class=MsoNormal> 1 file changed, 1 insertion(+), 3 deletions(-)</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst</p><p class=MsoNormal>index 48e7ee7..224506d 100644</p><p class=MsoNormal>--- a/user/bsps/bsps-riscv.rst</p><p class=MsoNormal>+++ b/user/bsps/bsps-riscv.rst</p><p class=MsoNormal>@@ -43,9 +43,7 @@ This BSP offers 15 variants:</p><p class=MsoNormal> Each variant corresponds to a GCC multilib. A particular variant reflects an</p><p class=MsoNormal> ISA with ABI and code model choice.</p><p class=MsoNormal> </p><p class=MsoNormal>-The basic hardware initialization is not performed by the BSP. A boot loader</p><p class=MsoNormal>-with device tree support must be used to start the BSP, e.g. BBL. The BSP must</p><p class=MsoNormal>-be started im machine mode.</p><p class=MsoNormal>+The BSP must be started im machine mode.</p><p class=MsoNormal> </p><p class=MsoNormal> The reference platform for this BSP is the Qemu `virt` machine.</p><p class=MsoNormal> </p><p class=MsoNormal>-- </p><p class=MsoNormal>2.25.1</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>_______________________________________________</p><p class=MsoNormal>devel mailing list</p><p class=MsoNormal>devel@rtems.org</p><p class=MsoNormal>http://lists.rtems.org/mailman/listinfo/devel</p><p class=MsoNormal><o:p> </o:p></p></div></body></html>