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<div>Hi Sebastian,</div>
<div><br>
</div>
<div>The "Store/AMO address misaligned" trap occured in the "<b>start.S</b>"</div>
<div> at "<b>amoswap.w zero, zero, 0(t0)</b>" while testing the sample</div>
<div> application with the latest RTEMS master for RISC-V on</div>
<div>the Microchip PolarFire SoC.</div>
<div><br>
</div>
<div>The trap occured after this <a href="https://devel.rtems.org/changeset/89ba2a9838558841c4f38283e84b99173790d61c/rtems">89ba2a98/rtems</a> <span style="font-size: 14.666667px;">latest commit for riscv</span></div>
<div><span style="font-size: 14.666667px;">(</span>bsps/riscv: Workaround for sporadic linker issues<span style="font-size: 14.666667px;">).</span></div>
<div><span style="font-size: 14.666667px;"><br>
</span></div>
<div><span style="font-size: 14.666667px;">Regards</span></div>
<div><span style="font-size: 14.666667px;">Padmarao</span></div>
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