<div dir="ltr"><div>Thanks for taking a look. Comments below.</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Mar 13, 2023 at 11:04 AM Gedare Bloom <<a href="mailto:gedare@rtems.org">gedare@rtems.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On Thu, Mar 9, 2023 at 8:48 PM Alan Cudmore <<a href="mailto:alan.cudmore@gmail.com" target="_blank">alan.cudmore@gmail.com</a>> wrote:<br>
><br>
> This patch set adds support for the Kendryte K210 RISC-V BSP variant.<br>
> The SoC uses existing PLIC, Timer, and console UART. It only needs<br>
> SoC specific initalization and an embedded device tree binary similar<br>
> to the polarfire SoC BSP.<br>
><br>
> Updates #4876<br>
> ---<br>
> bsps/riscv/riscv/config/kendrytek210.cfg | 9 +<br>
> bsps/riscv/riscv/console/console-config.c | 10 +-<br>
> bsps/riscv/riscv/console/fe310-uart.c | 2 +-<br>
> bsps/riscv/riscv/dts/kendryte-k210.dts | 216 ++++++++++++<br>
> bsps/riscv/riscv/include/bsp.h | 4 +<br>
> bsps/riscv/riscv/include/bsp/k210.h | 91 +++++<br>
> .../riscv/include/bsp/kendryte-k210-dtb.h | 315 ++++++++++++++++++<br>
> bsps/riscv/riscv/include/bsp/riscv.h | 4 +<br>
> bsps/riscv/riscv/start/bspstart.c | 42 +++<br>
> 9 files changed, 687 insertions(+), 6 deletions(-)<br>
> create mode 100644 bsps/riscv/riscv/config/kendrytek210.cfg<br>
> create mode 100644 bsps/riscv/riscv/dts/kendryte-k210.dts<br>
> create mode 100644 bsps/riscv/riscv/include/bsp/k210.h<br>
> create mode 100644 bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h<br>
><br>
> diff --git a/bsps/riscv/riscv/config/kendrytek210.cfg b/bsps/riscv/riscv/config/kendrytek210.cfg<br>
> new file mode 100644<br>
> index 0000000000..b04e78b0e9<br>
> --- /dev/null<br>
> +++ b/bsps/riscv/riscv/config/kendrytek210.cfg<br>
> @@ -0,0 +1,9 @@<br>
> +include $(RTEMS_ROOT)/make/custom/default.cfg<br>
> +<br>
> +RTEMS_CPU = riscv<br>
> +<br>
> +CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany<br>
> +<br>
> +LDFLAGS = -Wl,--gc-sections<br>
> +<br>
> +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections<br>
> diff --git a/bsps/riscv/riscv/console/console-config.c b/bsps/riscv/riscv/console/console-config.c<br>
> index 4916191e0b..72743fe9d5 100644<br>
> --- a/bsps/riscv/riscv/console/console-config.c<br>
> +++ b/bsps/riscv/riscv/console/console-config.c<br>
> @@ -55,7 +55,7 @@<br>
> #include <libfdt.h><br>
> #include <string.h><br>
><br>
> -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0<br>
> +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0<br>
> #include <bsp/fe310-uart.h><br>
> static fe310_uart_context fe310_uart_instance;<br>
> #endif<br>
> @@ -239,7 +239,7 @@ static void riscv_console_probe(void)<br>
> }<br>
> #endif<br>
><br>
> -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0<br>
> +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0<br>
> if (fdt_stringlist_contains(compat, compat_len, "sifive,uart0")) {<br>
> fe310_uart_context *ctx;<br>
><br>
> @@ -255,7 +255,7 @@ static void riscv_console_probe(void)<br>
> riscv_console.getchar = fe310_uart_read;<br>
> }<br>
><br>
> - rtems_termios_device_context_initialize(&ctx->base, "FE310UART");<br>
> + rtems_termios_device_context_initialize(&ctx->base, "SIFIVEUART");<br>
> }<br>
> #endif<br>
><br>
> @@ -290,7 +290,7 @@ rtems_status_code console_initialize(<br>
> size_t i;<br>
> #endif<br>
><br>
> -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0<br>
> +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0<br>
> fe310_uart_context *ctx;<br>
> char fe310_path[] = "/dev/ttyS0";<br>
> #endif<br>
> @@ -326,7 +326,7 @@ rtems_status_code console_initialize(<br>
> }<br>
> #endif<br>
><br>
> -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0<br>
> +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0<br>
> ctx = &fe310_uart_instance;<br>
> rtems_termios_device_install(<br>
> fe310_path,<br>
> diff --git a/bsps/riscv/riscv/console/fe310-uart.c b/bsps/riscv/riscv/console/fe310-uart.c<br>
> index 506521add0..ddabcff4c8 100644<br>
> --- a/bsps/riscv/riscv/console/fe310-uart.c<br>
> +++ b/bsps/riscv/riscv/console/fe310-uart.c<br>
> @@ -53,7 +53,7 @@ static void fe310_uart_write (<br>
> fe310_uart_context * ctx = (fe310_uart_context*) base;<br>
> size_t i;<br>
><br>
> - ctx->regs->div = riscv_get_core_frequency() / 115200 - 1;<br>
> + ctx->regs->div = (riscv_get_core_frequency() / 115200 - 1) & 0xFFFF;<br>
> ctx->regs->txctrl |= 1;<br>
> ctx->regs->rxctrl |= 1;<br>
><br>
> diff --git a/bsps/riscv/riscv/dts/kendryte-k210.dts b/bsps/riscv/riscv/dts/kendryte-k210.dts<br>
> new file mode 100644<br>
> index 0000000000..379aaf01a3<br>
> --- /dev/null<br>
> +++ b/bsps/riscv/riscv/dts/kendryte-k210.dts<br>
> @@ -0,0 +1,216 @@<br>
> +/* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> +/*<br>
> + * Copyright (C) Alan Cudmore<br>
> + * Copyright (C) Padmarao Begari<br>
> + * Copyright (C) 2022 Microchip Technology Inc.<br>
> + *<br>
> + * Redistribution and use in source and binary forms, with or without<br>
> + * modification, are permitted provided that the following conditions<br>
> + * are met:<br>
> + * 1. Redistributions of source code must retain the above copyright<br>
> + * notice, this list of conditions and the following disclaimer.<br>
> + * 2. Redistributions in binary form must reproduce the above copyright<br>
> + * notice, this list of conditions and the following disclaimer in the<br>
> + * documentation and/or other materials provided with the distribution.<br>
> + *<br>
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
> + * POSSIBILITY OF SUCH DAMAGE.<br>
> + */<br>
> +<br>
> + /* This is a device tree for the Kendryte K210 SoC. It is a simplified tree<br>
> + * to support the current RTEMS BSP, but it is not sufficient enough for<br>
> + * full linux or u-boot support.<br>
> + * The file structure is based on the device tree source for the<br>
> + * Polarfire SoC created by Padmaro Begari. The K210 device trees from<br>
> + * u-boot were originally used to bring up the RTEMS BSP and were<br>
> + * referenced to develop this file.<br>
> + */<br>
> +<br>
> +/dts-v1/;<br>
> +<br>
> +/ {<br>
> + /* 32 bit address bus - upper 32 bits are ignored */<br>
> + #address-cells = <1>;<br>
> + #size-cells = <1>;<br>
> +<br>
> + model = "Kendtryte K210 generic";<br>
> + compatible = "canaan,kendryte-k210";<br>
> +<br>
> + aliases {<br>
> + serial0 = &uarths0;<br>
> + serial1 = &uart1;<br>
> + /* serial2 = &uart2; */<br>
> + /* serial3 = &uart3; */<br>
> + };<br>
> +<br>
> + chosen {<br>
> + stdout-path = "serial0";<br>
> + };<br>
> +<br>
> + cpus {<br>
> + #address-cells = <1>;<br>
> + #size-cells = <0>;<br>
> +<br>
> + timebase-frequency = <7800000>;<br>
> +<br>
> + cpu0: cpu@0 {<br>
> + compatible = "canaan,k210", "riscv";<br>
> + device_type = "cpu";<br>
> + reg = <0>;<br>
> + riscv,isa = "rv64imafdc";<br>
> + i-cache-block-size = <64>;<br>
> + i-cache-size = <0x8000>;<br>
> + d-cache-block-size = <64>;<br>
> + d-cache-size = <0x8000>;<br>
> + cpu0_intc: interrupt-controller {<br>
> + #interrupt-cells = <1>;<br>
> + compatible = "riscv,cpu-intc";<br>
> + interrupt-controller;<br>
> + };<br>
> + };<br>
> + cpu1: cpu@1 {<br>
> + compatible = "canaan,k210", "riscv";<br>
> + device_type = "cpu";<br>
> + reg = <1>;<br>
> + riscv,isa = "rv64imafdc";<br>
> + i-cache-block-size = <64>;<br>
> + i-cache-size = <0x8000>;<br>
> + d-cache-block-size = <64>;<br>
> + d-cache-size = <0x8000>;<br>
> + cpu1_intc: interrupt-controller {<br>
> + #interrupt-cells = <1>;<br>
> + compatible = "riscv,cpu-intc";<br>
> + interrupt-controller;<br>
> + };<br>
> + };<br>
> +<br>
> + };<br>
> +<br>
> + clocks {<br>
> + in0: oscillator {<br>
> + compatible = "fixed-clock";<br>
> + #clock-cells = <0>;<br>
> + clock-frequency = <26000000>;<br>
> + };<br>
> + };<br>
> +<br>
> + sram: memory@80000000 {<br>
> + device_type = "memory";<br>
> + compatible = "canaan,k210-sram";<br>
> + reg = <0x80000000 0x400000>,<br>
> + <0x80400000 0x200000>,<br>
> + <0x80600000 0x200000>;<br>
> + reg-names = "sram0",<br>
> + "sram1",<br>
> + "aisram";<br>
> +<br>
> + };<br>
> +<br>
> + soc: soc {<br>
> + #address-cells = <1>;<br>
> + #size-cells = <1>;<br>
> + compatible = "simple-bus";<br>
> + ranges;<br>
> + interrupt-parent = <&plic0>;<br>
> +<br>
> + rom0: nvmem@1000 {<br>
> + reg = <0x1000 0x1000>;<br>
> + read-only;<br>
> + };<br>
> +<br>
> + clint0: timer@2000000 {<br>
> + compatible = "riscv,clint0","sifive,clint0";<br>
> + reg = <0x2000000 0xC000>;<br>
> + interrupts-extended = <&cpu0_intc 3>,<&cpu0_intc 7>,<br>
> + <&cpu1_intc 3>,<&cpu1_intc 7>;<br>
> + };<br>
> +<br>
> + plic0: interrupt-controller@c000000 {<br>
> + #interrupt-cells = <1>;<br>
> + #address-cells = <0>;<br>
> + compatible = "riscv,plic0","sifive,plic-1.0.0";<br>
> + reg = <0xC000000 0x4000000>;<br>
> + riscv,ndev = <65>;<br>
> + interrupt-controller;<br>
> + interrupts-extended =<br>
> + <&cpu0_intc 11>, <&cpu0_intc 9>,<br>
> + <&cpu1_intc 11>, <&cpu1_intc 9>;<br>
> + };<br>
> +<br>
> + uarths0: serial@38000000 {<br>
> + compatible = "canaan,k210-uarths","sifive,uart0";<br>
> + reg = <0x38000000 0x1000>;<br>
> + interrupts = <33>;<br>
> + clocks = <&sysclk 0>;<br>
> +<br>
> + };<br>
> +<br>
> + /* apb0 has gpio1 and additional uarts */<br>
> + apb0: bus@50200000 {<br>
> + #address-cells = <1>;<br>
> + #size-cells = <1>;<br>
> + compatible = "simple-pm-bus";<br>
> + ranges;<br>
> + clocks = <&sysclk 8>;<br>
> +<br>
> + uart1: serial@50210000 {<br>
> + compatible = "snps,dw-apb-uart";<br>
> + reg = <0x50210000 0x100>;<br>
> + interrupts = <11>;<br>
> + clocks = <&sysclk 30>,<br>
> + <&sysclk 8>;<br>
> + clock-namees = "baudclk", "abp_pclk";<br>
> + resets = <&sysrst 16>;<br>
> + reg-io-width = <4>;<br>
> + reg-shift = <2>;<br>
> + dcd-override;<br>
> + dsr-override;<br>
> + cts-override;<br>
> + ri-override;<br>
> + };<br>
> + };<br>
> +<br>
> + apb1: bus@50400000 {<br>
> + #address-cells = <1>;<br>
> + #size-cells = <1>;<br>
> + compatible = "simple-pm-bus";<br>
> + ranges;<br>
> + clocks = <&sysclk 9>;<br>
> +<br>
> + sysctl: syscon@50440000 {<br>
> + compatible = "canaan,k210-sysctl","syscon",<br>
> + "simple-mfd";<br>
> + reg = <0x50440000 0x100>;<br>
> + clocks = <&sysclk 9>;<br>
> + clock-names = "pclk";<br>
> + sysclk: clock-controller {<br>
> + #clock-cells = <1>;<br>
> + compatible = "canaan,k210-rst";<br>
> + clock = <&in0>;<br>
> + };<br>
> + sysrst: reset-coontroller {<br>
> + compatible = "canaan,k210-rst";<br>
> + #reset-cells = <1>;<br>
> + };<br>
> + reboot: syscon-reboot {<br>
> + compatible = "syscon-reboot";<br>
> + regmap = <&sysctl>;<br>
> + offset = <48>;<br>
> + mask = <1>;<br>
> + value = <1>;<br>
> + };<br>
> + };<br>
> + };<br>
> +<br>
> + };<br>
> +};<br>
> diff --git a/bsps/riscv/riscv/include/bsp.h b/bsps/riscv/riscv/include/bsp.h<br>
> index 911b85f4a3..c33de42aa7 100644<br>
> --- a/bsps/riscv/riscv/include/bsp.h<br>
> +++ b/bsps/riscv/riscv/include/bsp.h<br>
> @@ -60,6 +60,10 @@<br>
><br>
> #include <rtems/devnull.h><br>
><br>
> +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0<br>
> + #include <bsp/k210.h><br>
> +#endif<br>
> +<br>
> #ifdef __cplusplus<br>
> extern "C" {<br>
> #endif<br>
> diff --git a/bsps/riscv/riscv/include/bsp/k210.h b/bsps/riscv/riscv/include/bsp/k210.h<br>
> new file mode 100644<br>
> index 0000000000..558502cd11<br>
> --- /dev/null<br>
> +++ b/bsps/riscv/riscv/include/bsp/k210.h<br>
> @@ -0,0 +1,91 @@<br>
> +/* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> +/**<br>
> + * @file<br>
> + *<br>
> + * @ingroup k210_regs<br>
> + *<br>
> + * @brief k210 RISC-V CPU defines.<br>
> + */<br>
> +<br>
> +/*<br>
> + *<br>
> + * Copyright (c) 2022 Alan Cudmore<br>
> + *<br>
> + * The license and distribution terms for this file may be<br>
> + * found in the file LICENSE in this distribution or at<br>
> + *<br>
> + * <a href="http://www.rtems.org/license/LICENSE" rel="noreferrer" target="_blank">http://www.rtems.org/license/LICENSE</a><br>
<br></blockquote><div><br></div><div>OK - I'll update this</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
Please use the 2-BSD boilerplate consistent with the SPDX above.<br>
<br>
> + *<br>
> + */<br>
> +<br>
> +#ifndef LIBBSP_RISCV_RISCV_K210_H<br>
> +#define LIBBSP_RISCV_RISCV_K210_H<br>
> +<br>
> +#include <bspopts.h><br>
> +#include <stdint.h><br>
> +#include <bsp/utility.h><br>
> +<br>
> +/**<br>
> + * @defgroup K210 RISC V Register Definitions<br>
> + *<br>
> + * @ingroup RTEMSBSPsriscv<br>
> + *<br>
> + * @brief Register Definitions<br>
> + *<br>
> + * @{<br>
> + */<br>
> +<br>
> +#ifdef __cplusplus<br>
> +extern "C" {<br>
> +#endif<br>
> +<br>
> +/* For PLL / Clocks */<br>
> +#define K210_SYSCTL_BASE 0x50440000<br>
> +<br>
> +#define PLL_CLK_R(n) (n & 0x00000F)<br>
Usually good practice to put parens around CPP macro arguments, e.g.,<br>
((n) & 0x00000F)<br>
<br>
> +#define PLL_CLK_F(n) ((n & 0x0003F0) >> 4)<br>
> +#define PLL_CLK_OD(n) ((n & 0x003C00) >> 10)<br>
> +#define CLKSEL0_ACLK_SEL(n) (n & 0x00000001)<br>
> +<br>
> +typedef struct {<br>
> + uint32_t git_id;<br>
> + uint32_t clk_freq;<br>
> + uint32_t pll0;<br>
> + uint32_t pll1;<br>
> + uint32_t pll2;<br>
> + uint32_t resv5;<br>
> + uint32_t pll_lock;<br>
> + uint32_t rom_error;<br>
> + uint32_t clk_sel0;<br>
> + uint32_t clk_sel1;<br>
> + uint32_t clk_en_cent;<br>
> + uint32_t clk_en_peri;<br>
> + uint32_t soft_reset;<br>
> + uint32_t peri_reset;<br>
> + uint32_t clk_th0;<br>
> + uint32_t clk_th1;<br>
> + uint32_t clk_th2;<br>
> + uint32_t clk_th3;<br>
> + uint32_t clk_th4;<br>
> + uint32_t clk_th5;<br>
> + uint32_t clk_th6;<br>
> + uint32_t misc;<br>
> + uint32_t peri;<br>
> + uint32_t spi_sleep;<br>
> + uint32_t reset_status;<br>
> + uint32_t dma_sel0;<br>
> + uint32_t dma_sel1;<br>
> + uint32_t power_sel;<br>
> + uint32_t resv28;<br>
> + uint32_t resv29;<br>
> + uint32_t resv30;<br>
> + uint32_t resv31;<br>
> +} k210_sysctl_t;<br>
> +<br>
> +#ifdef __cplusplus<br>
> +}<br>
> +#endif<br>
> +<br>
> +/** @} */<br>
> +#endif /* LIBBSP_RISCV_RISCV_K210_H */<br>
> diff --git a/bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h b/bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h<br>
> new file mode 100644<br>
> index 0000000000..ad13aefdbf<br>
> --- /dev/null<br>
> +++ b/bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h<br>
> @@ -0,0 +1,315 @@<br>
> +/* SPDX-License-Identifier: BSD-2-Clause */<br>
> +<br>
> +/*<br>
> + * Declarations for C structure representing binary file system.dtb<br>
> + *<br>
> + * WARNING: Automatically generated -- do not edit!<br>
> + */<br>
> +<br>
> +/*<br>
> + * Copyright (C) Alan Cudmore<br>
> + *<br>
> + * Redistribution and use in source and binary forms, with or without<br>
> + * modification, are permitted provided that the following conditions<br>
> + * are met:<br>
> + * 1. Redistributions of source code must retain the above copyright<br>
> + * notice, this list of conditions and the following disclaimer.<br>
> + * 2. Redistributions in binary form must reproduce the above copyright<br>
> + * notice, this list of conditions and the following disclaimer in the<br>
> + * documentation and/or other materials provided with the distribution.<br>
> + *<br>
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
> + * POSSIBILITY OF SUCH DAMAGE.<br>
> + */<br>
> +<br>
> +#ifndef __kendryte_k210_dtb_h<br>
> +#define __kendryte_k210_dtb_h<br>
> +<br>
> +#include <rtems/score/basedefs.h><br>
> +#include <sys/types.h><br>
> +<br>
> +const unsigned char system_dtb[] RTEMS_ALIGNED(8) = {<br>
> + 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x0c, 0xa7, 0x00, 0x00, 0x00, 0x38,<br>
> + 0x00, 0x00, 0x0a, 0xb4, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,<br>
> + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf3,<br>
> + 0x00, 0x00, 0x0a, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x1b,<br>
> + 0x4b, 0x65, 0x6e, 0x64, 0x74, 0x72, 0x79, 0x74, 0x65, 0x20, 0x4b, 0x32,<br>
> + 0x31, 0x30, 0x20, 0x67, 0x65, 0x6e, 0x65, 0x72, 0x69, 0x63, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x21,<br>
> + 0x63, 0x61, 0x6e, 0x61, 0x61, 0x6e, 0x2c, 0x6b, 0x65, 0x6e, 0x64, 0x72,<br>
> + 0x79, 0x74, 0x65, 0x2d, 0x6b, 0x32, 0x31, 0x30, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x61, 0x6c, 0x69, 0x61, 0x73, 0x65, 0x73, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x2c,<br>
> + 0x2f, 0x73, 0x6f, 0x63, 0x2f, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x40,<br>
> + 0x33, 0x38, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x34,<br>
> + 0x2f, 0x73, 0x6f, 0x63, 0x2f, 0x62, 0x75, 0x73, 0x40, 0x35, 0x30, 0x32,<br>
> + 0x30, 0x30, 0x30, 0x30, 0x30, 0x2f, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c,<br>
> + 0x40, 0x35, 0x30, 0x32, 0x31, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x63, 0x68, 0x6f, 0x73,<br>
> + 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,<br>
> + 0x00, 0x00, 0x00, 0x3c, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x30, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x73,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x48,<br>
> + 0x00, 0x77, 0x04, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x40,<br>
> + 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12,<br>
> + 0x00, 0x00, 0x00, 0x21, 0x63, 0x61, 0x6e, 0x61, 0x61, 0x6e, 0x2c, 0x6b,<br>
> + 0x32, 0x31, 0x30, 0x00, 0x72, 0x69, 0x73, 0x63, 0x76, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x5b,<br>
> + 0x63, 0x70, 0x75, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x6b, 0x72, 0x76, 0x36, 0x34,<br>
> + 0x69, 0x6d, 0x61, 0x66, 0x64, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x40,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x88,<br>
> + 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xa8, 0x00, 0x00, 0x80, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70,<br>
> + 0x74, 0x2d, 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0xb5, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x21, 0x72, 0x69, 0x73, 0x63,<br>
> + 0x76, 0x2c, 0x63, 0x70, 0x75, 0x2d, 0x69, 0x6e, 0x74, 0x63, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xdb,<br>
> + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x40, 0x31, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x21,<br>
> + 0x63, 0x61, 0x6e, 0x61, 0x61, 0x6e, 0x2c, 0x6b, 0x32, 0x31, 0x30, 0x00,<br>
> + 0x72, 0x69, 0x73, 0x63, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x5b, 0x63, 0x70, 0x75, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x67,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b,<br>
> + 0x00, 0x00, 0x00, 0x6b, 0x72, 0x76, 0x36, 0x34, 0x69, 0x6d, 0x61, 0x66,<br>
> + 0x64, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x80, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x95,<br>
> + 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0xa8, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f,<br>
> + 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xb5,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0f,<br>
> + 0x00, 0x00, 0x00, 0x21, 0x72, 0x69, 0x73, 0x63, 0x76, 0x2c, 0x63, 0x70,<br>
> + 0x75, 0x2d, 0x69, 0x6e, 0x74, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xdb, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x73, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x6f, 0x73, 0x63, 0x69, 0x6c, 0x6c, 0x61, 0x74,<br>
> + 0x6f, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,<br>
> + 0x00, 0x00, 0x00, 0x21, 0x66, 0x69, 0x78, 0x65, 0x64, 0x2d, 0x63, 0x6c,<br>
> + 0x6f, 0x63, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x8c, 0xba, 0x80,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xdb,<br>
> + 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x6d, 0x65, 0x6d, 0x6f, 0x72, 0x79, 0x40, 0x38,<br>
> + 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x5b, 0x6d, 0x65, 0x6d, 0x6f,<br>
> + 0x72, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x11,<br>
> + 0x00, 0x00, 0x00, 0x21, 0x63, 0x61, 0x6e, 0x61, 0x61, 0x6e, 0x2c, 0x6b,<br>
> + 0x32, 0x31, 0x30, 0x2d, 0x73, 0x72, 0x61, 0x6d, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x67,<br>
> + 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x80, 0x40, 0x00, 0x00,<br>
> + 0x00, 0x20, 0x00, 0x00, 0x80, 0x60, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x01, 0x00,<br>
> + 0x73, 0x72, 0x61, 0x6d, 0x30, 0x00, 0x73, 0x72, 0x61, 0x6d, 0x31, 0x00,<br>
> + 0x61, 0x69, 0x73, 0x72, 0x61, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x73, 0x6f, 0x63, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b,<br>
> + 0x00, 0x00, 0x00, 0x21, 0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x2d, 0x62,<br>
> + 0x75, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x01, 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x6e, 0x76, 0x6d, 0x65, 0x6d, 0x40, 0x31, 0x30, 0x30, 0x30, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x67,<br>
> + 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x22, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x74, 0x69, 0x6d, 0x65, 0x72, 0x40, 0x32, 0x30,<br>
> + 0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x1b, 0x00, 0x00, 0x00, 0x21, 0x72, 0x69, 0x73, 0x63,<br>
> + 0x76, 0x2c, 0x63, 0x6c, 0x69, 0x6e, 0x74, 0x30, 0x00, 0x73, 0x69, 0x66,<br>
> + 0x69, 0x76, 0x65, 0x2c, 0x63, 0x6c, 0x69, 0x6e, 0x74, 0x30, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x67,<br>
> + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x2c, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x07,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f,<br>
> + 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x40, 0x63, 0x30, 0x30,<br>
> + 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xb5, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x1e,<br>
> + 0x00, 0x00, 0x00, 0x21, 0x72, 0x69, 0x73, 0x63, 0x76, 0x2c, 0x70, 0x6c,<br>
> + 0x69, 0x63, 0x30, 0x00, 0x73, 0x69, 0x66, 0x69, 0x76, 0x65, 0x2c, 0x70,<br>
> + 0x6c, 0x69, 0x63, 0x2d, 0x31, 0x2e, 0x30, 0x2e, 0x30, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x67,<br>
> + 0x0c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x41,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x2c,<br>
> + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xdb, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x73, 0x65, 0x72, 0x69,<br>
> + 0x61, 0x6c, 0x40, 0x33, 0x38, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x21,<br>
> + 0x63, 0x61, 0x6e, 0x61, 0x61, 0x6e, 0x2c, 0x6b, 0x32, 0x31, 0x30, 0x2d,<br>
> + 0x75, 0x61, 0x72, 0x74, 0x68, 0x73, 0x00, 0x73, 0x69, 0x66, 0x69, 0x76,<br>
> + 0x65, 0x2c, 0x75, 0x61, 0x72, 0x74, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x67, 0x38, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x01, 0x4b, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x56, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x62, 0x75, 0x73, 0x40, 0x35, 0x30, 0x32, 0x30, 0x30, 0x30, 0x30, 0x30,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x21,<br>
> + 0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x2d, 0x70, 0x6d, 0x2d, 0x62, 0x75,<br>
> + 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,<br>
> + 0x00, 0x00, 0x01, 0x56, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x40, 0x35,<br>
> + 0x30, 0x32, 0x31, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x21, 0x73, 0x6e, 0x70, 0x73,<br>
> + 0x2c, 0x64, 0x77, 0x2d, 0x61, 0x70, 0x62, 0x2d, 0x75, 0x61, 0x72, 0x74,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,<br>
> + 0x00, 0x00, 0x00, 0x67, 0x50, 0x21, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x4b,<br>
> + 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,<br>
> + 0x00, 0x00, 0x01, 0x56, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x1e,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x01, 0x5d, 0x62, 0x61, 0x75, 0x64,<br>
> + 0x63, 0x6c, 0x6b, 0x00, 0x61, 0x62, 0x70, 0x5f, 0x70, 0x63, 0x6c, 0x6b,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,<br>
> + 0x00, 0x00, 0x01, 0x6a, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x10,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x71,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x01, 0x7e, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x95, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa2, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xaf, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x62, 0x75, 0x73, 0x40,<br>
> + 0x35, 0x30, 0x34, 0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x21, 0x73, 0x69, 0x6d, 0x70,<br>
> + 0x6c, 0x65, 0x2d, 0x70, 0x6d, 0x2d, 0x62, 0x75, 0x73, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0a,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x56,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x73, 0x79, 0x73, 0x63, 0x6f, 0x6e, 0x40, 0x35, 0x30, 0x34, 0x34, 0x30,<br>
> + 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x25,<br>
> + 0x00, 0x00, 0x00, 0x21, 0x63, 0x61, 0x6e, 0x61, 0x61, 0x6e, 0x2c, 0x6b,<br>
> + 0x32, 0x31, 0x30, 0x2d, 0x73, 0x79, 0x73, 0x63, 0x74, 0x6c, 0x00, 0x73,<br>
> + 0x79, 0x73, 0x63, 0x6f, 0x6e, 0x00, 0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65,<br>
> + 0x2d, 0x6d, 0x66, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x67, 0x50, 0x44, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,<br>
> + 0x00, 0x00, 0x01, 0x56, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x09,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0xbb,<br>
> + 0x70, 0x63, 0x6c, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xdb, 0x00, 0x00, 0x00, 0x07,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x63, 0x6f,<br>
> + 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe3,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,<br>
> + 0x00, 0x00, 0x00, 0x21, 0x63, 0x61, 0x6e, 0x61, 0x61, 0x6e, 0x2c, 0x6b,<br>
> + 0x32, 0x31, 0x30, 0x2d, 0x72, 0x73, 0x74, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0xc7, 0x00, 0x00, 0x00, 0x06,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xdb,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x72, 0x65, 0x73, 0x65, 0x74, 0x2d, 0x63, 0x6f, 0x6f, 0x6e, 0x74, 0x72,<br>
> + 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x21, 0x63, 0x61, 0x6e, 0x61,<br>
> + 0x61, 0x6e, 0x2c, 0x6b, 0x32, 0x31, 0x30, 0x2d, 0x72, 0x73, 0x74, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0xcd,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x00, 0xdb, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x73, 0x79, 0x73, 0x63, 0x6f, 0x6e, 0x2d, 0x72,<br>
> + 0x65, 0x62, 0x6f, 0x6f, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x21, 0x73, 0x79, 0x73, 0x63,<br>
> + 0x6f, 0x6e, 0x2d, 0x72, 0x65, 0x62, 0x6f, 0x6f, 0x74, 0x00, 0x00, 0x00,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0xda,<br>
> + 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,<br>
> + 0x00, 0x00, 0x01, 0xe1, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x03,<br>
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0xe8, 0x00, 0x00, 0x00, 0x01,<br>
> + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0xed,<br>
> + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,<br>
> + 0x00, 0x00, 0x00, 0x09, 0x23, 0x61, 0x64, 0x64, 0x72, 0x65, 0x73, 0x73,<br>
> + 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x23, 0x73, 0x69, 0x7a, 0x65,<br>
> + 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x6c,<br>
> + 0x00, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, 0x62, 0x6c, 0x65, 0x00,<br>
> + 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x30, 0x00, 0x73, 0x65, 0x72, 0x69,<br>
> + 0x61, 0x6c, 0x31, 0x00, 0x73, 0x74, 0x64, 0x6f, 0x75, 0x74, 0x2d, 0x70,<br>
> + 0x61, 0x74, 0x68, 0x00, 0x74, 0x69, 0x6d, 0x65, 0x62, 0x61, 0x73, 0x65,<br>
> + 0x2d, 0x66, 0x72, 0x65, 0x71, 0x75, 0x65, 0x6e, 0x63, 0x79, 0x00, 0x64,<br>
> + 0x65, 0x76, 0x69, 0x63, 0x65, 0x5f, 0x74, 0x79, 0x70, 0x65, 0x00, 0x72,<br>
> + 0x65, 0x67, 0x00, 0x72, 0x69, 0x73, 0x63, 0x76, 0x2c, 0x69, 0x73, 0x61,<br>
> + 0x00, 0x69, 0x2d, 0x63, 0x61, 0x63, 0x68, 0x65, 0x2d, 0x62, 0x6c, 0x6f,<br>
> + 0x63, 0x6b, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x00, 0x69, 0x2d, 0x63, 0x61,<br>
> + 0x63, 0x68, 0x65, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x00, 0x64, 0x2d, 0x63,<br>
> + 0x61, 0x63, 0x68, 0x65, 0x2d, 0x62, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x73,<br>
> + 0x69, 0x7a, 0x65, 0x00, 0x64, 0x2d, 0x63, 0x61, 0x63, 0x68, 0x65, 0x2d,<br>
> + 0x73, 0x69, 0x7a, 0x65, 0x00, 0x23, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72,<br>
> + 0x75, 0x70, 0x74, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x69, 0x6e,<br>
> + 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f, 0x6e, 0x74,<br>
> + 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x70, 0x68, 0x61, 0x6e, 0x64,<br>
> + 0x6c, 0x65, 0x00, 0x23, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x63, 0x65,<br>
> + 0x6c, 0x6c, 0x73, 0x00, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x66, 0x72,<br>
> + 0x65, 0x71, 0x75, 0x65, 0x6e, 0x63, 0x79, 0x00, 0x72, 0x65, 0x67, 0x2d,<br>
> + 0x6e, 0x61, 0x6d, 0x65, 0x73, 0x00, 0x72, 0x61, 0x6e, 0x67, 0x65, 0x73,<br>
> + 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x70,<br>
> + 0x61, 0x72, 0x65, 0x6e, 0x74, 0x00, 0x72, 0x65, 0x61, 0x64, 0x2d, 0x6f,<br>
> + 0x6e, 0x6c, 0x79, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70,<br>
> + 0x74, 0x73, 0x2d, 0x65, 0x78, 0x74, 0x65, 0x6e, 0x64, 0x65, 0x64, 0x00,<br>
> + 0x72, 0x69, 0x73, 0x63, 0x76, 0x2c, 0x6e, 0x64, 0x65, 0x76, 0x00, 0x69,<br>
> + 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x73, 0x00, 0x63, 0x6c,<br>
> + 0x6f, 0x63, 0x6b, 0x73, 0x00, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x6e,<br>
> + 0x61, 0x6d, 0x65, 0x65, 0x73, 0x00, 0x72, 0x65, 0x73, 0x65, 0x74, 0x73,<br>
> + 0x00, 0x72, 0x65, 0x67, 0x2d, 0x69, 0x6f, 0x2d, 0x77, 0x69, 0x64, 0x74,<br>
> + 0x68, 0x00, 0x72, 0x65, 0x67, 0x2d, 0x73, 0x68, 0x69, 0x66, 0x74, 0x00,<br>
> + 0x64, 0x63, 0x64, 0x2d, 0x6f, 0x76, 0x65, 0x72, 0x72, 0x69, 0x64, 0x65,<br>
> + 0x00, 0x64, 0x73, 0x72, 0x2d, 0x6f, 0x76, 0x65, 0x72, 0x72, 0x69, 0x64,<br>
> + 0x65, 0x00, 0x63, 0x74, 0x73, 0x2d, 0x6f, 0x76, 0x65, 0x72, 0x72, 0x69,<br>
> + 0x64, 0x65, 0x00, 0x72, 0x69, 0x2d, 0x6f, 0x76, 0x65, 0x72, 0x72, 0x69,<br>
> + 0x64, 0x65, 0x00, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x6e, 0x61, 0x6d,<br>
> + 0x65, 0x73, 0x00, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x00, 0x23, 0x72, 0x65,<br>
> + 0x73, 0x65, 0x74, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x72, 0x65,<br>
> + 0x67, 0x6d, 0x61, 0x70, 0x00, 0x6f, 0x66, 0x66, 0x73, 0x65, 0x74, 0x00,<br>
> + 0x6d, 0x61, 0x73, 0x6b, 0x00, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x00,<br>
> +};<br>
> +<br>
> +const size_t system_dtb_size = sizeof(system_dtb);<br>
> +<br>
> +#endif /* __kendryte_k210_dtb_h */<br>
> diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h<br>
> index bbaaa246c1..d294f1ae58 100644<br>
> --- a/bsps/riscv/riscv/include/bsp/riscv.h<br>
> +++ b/bsps/riscv/riscv/include/bsp/riscv.h<br>
> @@ -56,6 +56,10 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle);<br>
> void htif_poweroff(void);<br>
> #endif<br>
><br>
> +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0<br>
> +uint32_t k210_get_frequency(void);<br>
> +#endif<br>
> +<br>
> #ifdef __cplusplus<br>
> }<br>
> #endif<br>
> diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c<br>
> index 30d479ce88..a0b6e683f6 100644<br>
> --- a/bsps/riscv/riscv/start/bspstart.c<br>
> +++ b/bsps/riscv/riscv/start/bspstart.c<br>
> @@ -201,6 +201,14 @@ static uint32_t get_core_frequency(void)<br>
> return fdt32_to_cpu(*val);<br>
> }<br>
> #endif<br>
> +<br>
> +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0<br>
> + uint32_t cpu_clock;<br>
> +<br>
> + cpu_clock = k210_get_frequency();<br>
> + return cpu_clock;<br>
> +#endif<br>
> +<br>
> return 0;<br></blockquote><div><br></div><div>When you choose the kendrtyek210 BSP variant, the RISCV_ENABLE_KENDRYTE_K210_SUPPORT is set to true enabling the code that is needed for frequency calculation in this file. I tried to follow the same pattern for the MPFS and FRDME310ARTY variants here.</div><div>The K210, FRME310ARTY, and MPFS options could probably use refactoring, but I was reluctant to change existing code for the MPFS and 310ARTY since I do not have a way of testing them.</div><div><br></div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
This code is unreachable if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0.<br>
<br>
> }<br>
><br>
> @@ -215,6 +223,40 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)<br>
> return RISCV_INTERRUPT_VECTOR_EXTERNAL(intr[0]);<br>
> }<br>
><br>
> +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0<br>
> +uint32_t k210_get_frequency(void)<br>
> +{<br>
> + k210_sysctl_t *sysctl = (k210_sysctl_t *)K210_SYSCTL_BASE;<br>
> + uint32_t cpu_clock = 0;<br>
> + uint32_t clk_freq;<br>
> + uint32_t pll0, nr, nf, od;<br>
> + uint32_t node;<br>
> + const char *fdt;<br>
> + const fdt32_t *val;<br>
> + int len;<br>
> +<br>
> + fdt = bsp_fdt_get();<br>
> + node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");<br>
> + val = fdt_getprop(fdt, node, "clock-frequency", &len);<br>
> + if (val != NULL && len == 4) {<br>
> + clk_freq = fdt32_to_cpu(*val);<br>
> +<br>
> + if (CLKSEL0_ACLK_SEL(sysctl->clk_sel0) == 1) {<br>
> + /* PLL0 selected */<br>
> + pll0 = sysctl->pll0;<br>
> + nr = PLL_CLK_R(pll0) + 1;<br>
> + nf = PLL_CLK_F(pll0) + 1;<br>
> + od = PLL_CLK_OD(pll0) + 1;<br>
> + cpu_clock = (clk_freq / nr * nf / od)/2;<br>
> + } else {<br>
> + /* OSC selected */<br>
> + cpu_clock = clk_freq;<br>
> + }<br>
> + }<br>
> + return cpu_clock;<br>
> +}<br>
> +#endif<br>
> +<br>
> void bsp_start(void)<br>
> {<br>
> riscv_find_harts();<br>
> --<br>
> 2.25.1<br>
><br>
> _______________________________________________<br>
> devel mailing list<br>
> <a href="mailto:devel@rtems.org" target="_blank">devel@rtems.org</a><br>
> <a href="http://lists.rtems.org/mailman/listinfo/devel" rel="noreferrer" target="_blank">http://lists.rtems.org/mailman/listinfo/devel</a><br>
</blockquote></div></div>