<div dir="ltr"><div>This patch adds support for running RTEMS on the RPU (cortex R5) cores of the ZynqMP.  This is only a basic BSP and does not yet support the following:</div><div>- SMP<br></div><div>- Cache</div><div>- MPU</div><div><br></div><div>Also, everything except for the startup and exception vectors runs out of DRAM, which is slow without cache.  At some point in the future, I plan to move some of the fast memory sections to ATCM and BTCM and enable cache.</div><div><br></div><div>Lastly, credit to Stanislav (<span class="gmail-gI"><span class="gmail-qu" role="gridcell" tabindex="-1"><span class="gmail-go"><span aria-hidden="true"></span><a href="mailto:s.pankevich@gmail.com">s.pankevich@gmail.com</a><span aria-hidden="true">, also on this mailing list), for internal reviews and feedback.<br></span></span></span></span></div><div><br></div><div>The steps done to implement this BSP are as follows:<br>- to xilinx_zynqmp_ultra96 bsp (spec/build/bsps/arm/xilinx-zynqmp/*)<br>  - Added optprocunitapu.yml to pass C define ZYNQMP_PROC_UNIT_APU<br>- Copied xilinx_zynqmp_ultra96 bsp to xilinx_zynqmp_mercuryxu5_rpu in spec/build/bsps/arm/xilinx-zynqmp-rpu/*<br>- In new BSP<br>  - changed optprocunitapu.yml to optprocunitrpu.yml to pass C define ZYNQMP_PROC_UNIT_RPU<br>  - Removed all things regarding MMU, and SMP<br>  - Changed source: bsps/arm/shared/cache/cache-cp15.c to bsps/shared/cache/nocache.c<br>  - Removed all other references to cache<br>  - Changed abi flags<br>  - Updated the linkcmds to remove MMU and cache sections.<br>  - Updated optint0len, optint0ori, optint1len, and optint1ori to target ATCM and BTCM.<br>  - Updated linkcmds to place START and VECTOR regions in ATCM<br>- In BSP C sources<br>  - Used ZYNQMP_PROC_UNIT_APU and ZYNQMP_PROC_UNIT_RPU to enable/disable MPU, SMP, and cache.<br>  - Used PROC_UNIT flags to control GIC address.<br>  - Added hook0 code for RPU code to make sure SCTLR[M, I, A, C, V] are cleared<br>  - Created a timer driver for the Triple Timer Counter (TTC) module since the RPU doesn't have an ARM generic timer<br></div><div><br></div><div>---</div><div>diff --git a/bsps/arm/xilinx-zynqmp/clock/clock-ttc.c b/bsps/arm/xilinx-zynqmp/clock/clock-ttc.c<br>new file mode 100644<br>index 0000000000..dd0bc3a3c9<br>--- /dev/null<br>+++ b/bsps/arm/xilinx-zynqmp/clock/clock-ttc.c<br>@@ -0,0 +1,219 @@<br>+/**<br>+ * @file<br>+ *<br>+ * @ingroup RTEMSBSPsARMZynqMP<br>+ *<br>+ * @brief Triple Timer Counter clock functions definitions.<br>+ */<br>+<br>+/*<br>+ * SPDX-License-Identifier: BSD-2-Clause<br>+ *<br>+ * Copyright (C) 2023 Reflex Aerospace GmbH<br>+ *<br>+ * Written by Philip Kirkpatrick <<a href="mailto:p.kirkpatrick@reflexaerospace.com">p.kirkpatrick@reflexaerospace.com</a>><br>+ *<br>+ * Redistribution and use in source and binary forms, with or without<br>+ * modification, are permitted provided that the following conditions<br>+ * are met:<br>+ * 1. Redistributions of source code must retain the above copyright<br>+ *    notice, this list of conditions and the following disclaimer.<br>+ * 2. Redistributions in binary form must reproduce the above copyright<br>+ *    notice, this list of conditions and the following disclaimer in the<br>+ *    documentation and/or other materials provided with the distribution.<br>+ *<br>+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>+ * POSSIBILITY OF SUCH DAMAGE.<br>+ */<br>+<br>+#include <stdlib.h><br>+<br>+#include <rtems.h><br>+#include <bsp.h><br>+#include <bsp/irq.h><br>+#include <bsp/zynqmp.h><br>+#include <bsp/xttcps_hw.h><br>+#include <rtems/timecounter.h><br>+<br>+static struct timecounter zynqmp_ttc_tc;<br>+<br>+#define TTC_REFERENCE_CLOCK 100000000<br>+<br>+/* This is defined in dev/clock/clockimpl.h */<br>+void Clock_isr(rtems_irq_hdl_param arg);<br>+<br>+static uint32_t irq_match_interval;<br>+<br>+static uint32_t zynqmp_ttc_get_timecount(struct timecounter *tc)<br>+{<br>+  uint32_t time;<br>+  time = XTtcPs_ReadReg(ZYNQMP_TTC0, XTTCPS_COUNT_VALUE_OFFSET);<br>+  return time;<br>+}<br>+<br>+/**<br>+ *  @brief Initialize the HW peripheral for clock driver<br>+ *<br>+ *  Clock driver is implemented by RTI module<br>+ *<br>+ * @retval Void<br>+ */<br>+static void zynqmp_ttc_clock_driver_support_initialize_hardware( void )<br>+{<br>+<br>+  uint32_t microsec_per_tick;<br>+  uint16_t clock_ratio;<br>+  uint8_t  index;<br>+  uint32_t frequency;<br>+  uint32_t prescaler;<br>+  uint32_t tmp_reg_val;<br>+<br>+  microsec_per_tick = rtems_configuration_get_microseconds_per_tick();<br>+<br>+  /* Check the TTC is OFF before reconfiguring */<br>+  XTtcPs_WriteReg(ZYNQMP_TTC0, XTTCPS_CNT_CNTRL_OFFSET, XTTCPS_CNT_CNTRL_DIS_MASK |<br>+        XTTCPS_CNT_CNTRL_EN_WAVE_MASK);  // Don't enable waveform output (active low)<br>+<br>+  /* Prescaler value is 2^(N + 1) */<br>+  /* Divide down the clock as much as possible while still retaining a */<br>+  /* frequency that is an integer multiple of 1MHz.  This maximizes time to */<br>+  /* overflow while minimizing rounding errors in 1us periods */<br>+  clock_ratio = TTC_REFERENCE_CLOCK / 1000000;<br>+  /* Search for the highest set bit.  This is effectively min(log2(ratio))*/<br>+  for(index = sizeof(clock_ratio) * 8 - 1; index > 0; index--)<br>+  {<br>+    if((clock_ratio >> (index)) & 0x01)<br>+    {<br>+        break;<br>+    }<br>+  }<br>+  if(index == 0 && (clock_ratio & 0x01 == 0))<br>+  {<br>+    // No prescaler<br>+    frequency = TTC_REFERENCE_CLOCK;<br>+    XTtcPs_WriteReg(ZYNQMP_TTC0, XTTCPS_CLK_CNTRL_OFFSET, 0);<br>+  }<br>+  else<br>+  {<br>+    prescaler = index - 1;<br>+    frequency = TTC_REFERENCE_CLOCK / (1 << (prescaler + 1));<br>+    XTtcPs_WriteReg(ZYNQMP_TTC0, XTTCPS_CLK_CNTRL_OFFSET, <br>+        prescaler << XTTCPS_CLK_CNTRL_PS_VAL_SHIFT |<br>+        XTTCPS_CLK_CNTRL_PS_EN_MASK);<br>+  }<br>+<br>+  /* Max out the counter interval */<br>+  tmp_reg_val = XTTCPS_INTERVAL_VAL_MASK;<br>+  XTtcPs_WriteReg(ZYNQMP_TTC0, XTTCPS_INTERVAL_VAL_OFFSET, tmp_reg_val);<br>+<br>+  /* Setup match register to generate tick IRQ */<br>+  irq_match_interval = (uint32_t) ((frequency * microsec_per_tick) / 1000000);<br>+  XTtcPs_WriteReg(ZYNQMP_TTC0, XTTCPS_MATCH_0_OFFSET, irq_match_interval);<br>+  /* Clear interupts (clear on read) */<br>+  XTtcPs_ReadReg(ZYNQMP_TTC0, XTTCPS_ISR_OFFSET);<br>+  /* Enable interupt for match register */<br>+  XTtcPs_WriteReg(ZYNQMP_TTC0, XTTCPS_IER_OFFSET, XTTCPS_IXR_MATCH_0_MASK);<br>+  /* Configure, reset, and enable counter */<br>+  XTtcPs_WriteReg(ZYNQMP_TTC0, XTTCPS_CNT_CNTRL_OFFSET, <br>+        XTTCPS_CNT_CNTRL_EN_WAVE_MASK |  /* Don't enable waveform output (active low) */<br>+        XTTCPS_CNT_CNTRL_RST_MASK |      /* Reset count and start counter */<br>+        XTTCPS_CNT_CNTRL_MATCH_MASK      /* Enable match mode */<br>+        /* Increment mode */<br>+        /* Overflow mode */<br>+        /* Not disabled */<br>+        );<br>+<br>+  /* set timecounter */<br>+  zynqmp_ttc_tc.tc_get_timecount = zynqmp_ttc_get_timecount;<br>+  zynqmp_ttc_tc.tc_counter_mask = XTTCPS_COUNT_VALUE_MASK;<br>+  zynqmp_ttc_tc.tc_frequency = frequency;<br>+  zynqmp_ttc_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;<br>+  rtems_timecounter_install(&zynqmp_ttc_tc);<br>+}<br>+<br>+/**<br>+ * @brief Clears interrupt source<br>+ *<br>+ * @retval Void<br>+ */<br>+static uint32_t tick_miss = 0;<br>+static void zynqmp_ttc_clock_driver_support_at_tick( void )<br>+{<br>+  uint32_t irq_flags;<br>+  uint32_t cval;<br>+  uint32_t now;<br>+  uint32_t delta;<br>+<br>+  /* Get and clear interupts (clear on read) */<br>+  irq_flags = XTtcPs_ReadReg(ZYNQMP_TTC0, XTTCPS_ISR_OFFSET);<br>+<br>+  if(irq_flags & XTTCPS_IXR_MATCH_0_MASK)<br>+  {<br>+    /* Update match */<br>+    cval = XTtcPs_ReadReg(ZYNQMP_TTC0, XTTCPS_MATCH_0_OFFSET);<br>+    /* Check that the match for the next tick is in the future */<br>+    /* If no, then set the match for one irq interval from now */<br>+    /*   This will have the effect that your timebase will slip but */<br>+    /*   won't hang waiting for the counter to wrap around. */<br>+    /* If this happens durring normal opteration, there is a problem */<br>+    /*   causing this interrupt to not be serviced quickly enough */<br>+    /* If this happens during debugging, that is normal and expected */<br>+    /*   becaue the TTC does NOT pause when the CPU is halted on a breakpoint */<br>+    now = XTtcPs_ReadReg(ZYNQMP_TTC0, XTTCPS_COUNT_VALUE_OFFSET);<br>+    delta = now - cval;<br>+    if(delta > irq_match_interval)<br>+    {<br>+           cval = now;<br>+        tick_miss++;<br>+    }<br>+    cval += irq_match_interval;<br>+    XTtcPs_WriteReg(ZYNQMP_TTC0, XTTCPS_MATCH_0_OFFSET, cval);<br>+  }<br>+  /* Else, something is set up wrong, only match should be enabled */<br>+}<br>+<br>+/**<br>+ * @brief registers RTI interrupt handler<br>+ *<br>+ * @param[in] Clock_isr new ISR handler<br>+ * @param[in] Old_ticker old ISR handler (unused and type broken)<br>+ *<br>+ * @retval Void<br>+ */<br>+static void zynqmp_ttc_clock_driver_support_install_isr(<br>+  rtems_isr_entry Clock_isr<br>+)<br>+{<br>+  rtems_status_code sc = RTEMS_SUCCESSFUL;<br>+<br>+  sc = rtems_interrupt_handler_install(<br>+    ZYNQMP_IRQ_TTC_0_0,<br>+    "Clock",<br>+    RTEMS_INTERRUPT_UNIQUE,<br>+    (rtems_interrupt_handler) Clock_isr,<br>+    NULL<br>+  );<br>+  if ( sc != RTEMS_SUCCESSFUL ) {<br>+    rtems_fatal_error_occurred(0xdeadbeef);<br>+  }<br>+}<br>+<br>+#define Clock_driver_support_at_tick \<br>+                        zynqmp_ttc_clock_driver_support_at_tick<br>+<br>+#define Clock_driver_support_initialize_hardware \<br>+                        zynqmp_ttc_clock_driver_support_initialize_hardware<br>+                        <br>+#define Clock_driver_support_install_isr(Clock_isr) \<br>+              zynqmp_ttc_clock_driver_support_install_isr( Clock_isr )<br>+<br>+#include "../../../shared/dev/clock/clockimpl.h"<br>diff --git a/bsps/arm/xilinx-zynqmp/config/xilinx_zynqmp_rpu.inc b/bsps/arm/xilinx-zynqmp/config/xilinx_zynqmp_rpu.inc<br>new file mode 100644<br>index 0000000000..f97f4d5018<br>--- /dev/null<br>+++ b/bsps/arm/xilinx-zynqmp/config/xilinx_zynqmp_rpu.inc<br>@@ -0,0 +1,10 @@<br>+include $(RTEMS_ROOT)/make/custom/default.cfg<br>+<br>+RTEMS_CPU = arm<br>+<br>+CPU_CFLAGS = -march=armv7-r -mthumb -mfpu=vfpv3-d16 -mfloat-abi=hard<br>+<br>+CFLAGS_OPTIMIZE_V ?= -O2 -g<br>+CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections<br>+<br>+LDFLAGS = -Wl,--gc-sections<br>diff --git a/bsps/arm/xilinx-zynqmp/include/bsp.h b/bsps/arm/xilinx-zynqmp/include/bsp.h<br>index 9d33cf6134..d0b4b9d644 100644<br>--- a/bsps/arm/xilinx-zynqmp/include/bsp.h<br>+++ b/bsps/arm/xilinx-zynqmp/include/bsp.h<br>@@ -64,9 +64,17 @@<br> extern "C" {<br> #endif /* __cplusplus */<br> <br>+#ifdef ZYNQMP_PROC_UNIT_APU<br> #define BSP_ARM_GIC_CPUIF_BASE 0xf9020000<br> <br> #define BSP_ARM_GIC_DIST_BASE 0xf9010000<br>+#endif<br>+<br>+#ifdef ZYNQMP_PROC_UNIT_RPU<br>+#define BSP_ARM_GIC_CPUIF_BASE 0x00F9001000<br>+<br>+#define BSP_ARM_GIC_DIST_BASE 0xF9000000<br>+#endif<br> <br> #define BSP_ARM_A9MPCORE_SCU_BASE 0<br> <br>diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h<br>index 9aae8168db..a8271bebb5 100644<br>--- a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h<br>+++ b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h<br>@@ -56,17 +56,32 @@ extern "C" {<br>  * @brief Interrupt Support<br>  * @{<br>  */<br>-<br> /* PPIs */<br>+#ifdef ZYNQMP_PROC_UNIT_APU<br> #define ZYNQMP_IRQ_HYP_TIMER 26<br> #define ZYNQMP_IRQ_VIRT_TIMER 27<br> #define ZYNQMP_IRQ_S_PHYS_TIMER 29<br> #define ZYNQMP_IRQ_NS_PHYS_TIMER 30<br>+#endif<br> <br> /* SPIs */<br> #define ZYNQMP_IRQ_UART_0 53<br> #define ZYNQMP_IRQ_UART_1 54<br> <br>+#define ZYNQMP_IRQ_TTC_0_0 68<br>+#define ZYNQMP_IRQ_TTC_0_1 69<br>+#define ZYNQMP_IRQ_TTC_0_2 70<br>+#define ZYNQMP_IRQ_TTC_1_0 71<br>+#define ZYNQMP_IRQ_TTC_1_1 72<br>+#define ZYNQMP_IRQ_TTC_1_2 73<br>+#define ZYNQMP_IRQ_TTC_2_0 74<br>+#define ZYNQMP_IRQ_TTC_2_1 75<br>+#define ZYNQMP_IRQ_TTC_2_2 76<br>+#define ZYNQMP_IRQ_TTC_3_0 77<br>+#define ZYNQMP_IRQ_TTC_3_1 78<br>+#define ZYNQMP_IRQ_TTC_3_2 79<br>+<br>+<br> #define BSP_INTERRUPT_VECTOR_COUNT 188<br> <br> /** @} */<br>diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/xttcps_hw.h b/bsps/arm/xilinx-zynqmp/include/bsp/xttcps_hw.h<br>new file mode 100644<br>index 0000000000..ba0d559b07<br>--- /dev/null<br>+++ b/bsps/arm/xilinx-zynqmp/include/bsp/xttcps_hw.h<br>@@ -0,0 +1,223 @@<br>+/******************************************************************************<br>+* Copyright (C) 2010 - 2021 Xilinx, Inc.  All rights reserved.<br>+* SPDX-License-Identifier: MIT<br>+******************************************************************************/<br>+<br>+/*****************************************************************************/<br>+/**<br>+*<br>+* @file xttcps_hw.h<br>+* @addtogroup ttcps_v3_14<br>+* @{<br>+*<br>+* This file defines the hardware interface to one of the three timer counters<br>+* in the Ps block.<br>+*<br>+*<br>+* <pre><br>+* MODIFICATION HISTORY:<br>+*<br>+* Ver   Who    Date     Changes<br>+* ----- ------ -------- -------------------------------------------------<br>+* 1.00a drg/jz 01/21/10 First release<br>+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.<br>+* 3.5   srm    10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,<br>+*                       XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to<br>+*                       mask 16 bit values for zynq and 32 bit values for<br>+*                       zynq ultrascale+mpsoc "<br>+* </pre><br>+*<br>+******************************************************************************/<br>+<br>+#ifndef XTTCPS_HW_H            /* prevent circular inclusions */<br>+#define XTTCPS_HW_H         /* by using protection macros */<br>+<br>+#ifdef __cplusplus<br>+extern "C" {<br>+#endif<br>+<br>+/***************************** Include Files *********************************/<br>+<br>+<br>+#ifndef __rtems__<br>+#include "xil_types.h"<br>+#include "xil_assert.h"<br>+#include "xil_io.h"<br>+#else<br>+#include "xil_types.h"<br>+static inline u32 Xil_In32(UINTPTR Addr)<br>+{<br>+   return *(volatile u32 *) Addr;<br>+}<br>+static inline void Xil_Out32(UINTPTR Addr, u32 Value)<br>+{<br>+       volatile u32 *LocalAddr = (volatile u32 *)Addr;<br>+      *LocalAddr = Value;<br>+}<br>+#endif /* __rtems__ */<br>+<br>+/************************** Constant Definitions *****************************/<br>+/*<br>+ * Flag for a9 processor<br>+ */<br>+#if 0<br>+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)<br>+ #define ARMA9<br>+ #endif<br>+#endif<br>+<br>+/** @name Register Map<br>+ *<br>+ * Register offsets from the base address of the device.<br>+ *<br>+ * @{<br>+ */<br>+#define XTTCPS_CLK_CNTRL_OFFSET              0x00000000U  /**< Clock Control Register */<br>+#define XTTCPS_CNT_CNTRL_OFFSET               0x0000000CU  /**< Counter Control Register*/<br>+#define XTTCPS_COUNT_VALUE_OFFSET    0x00000018U  /**< Current Counter Value */<br>+#define XTTCPS_INTERVAL_VAL_OFFSET     0x00000024U  /**< Interval Count Value */<br>+#define XTTCPS_MATCH_0_OFFSET           0x00000030U  /**< Match 1 value */<br>+#define XTTCPS_MATCH_1_OFFSET          0x0000003CU  /**< Match 2 value */<br>+#define XTTCPS_MATCH_2_OFFSET          0x00000048U  /**< Match 3 value */<br>+#define XTTCPS_ISR_OFFSET                      0x00000054U  /**< Interrupt Status Register */<br>+#define XTTCPS_IER_OFFSET                  0x00000060U  /**< Interrupt Enable Register */<br>+/* @} */<br>+<br>+/** @name Clock Control Register<br>+ * Clock Control Register definitions<br>+ * @{<br>+ */<br>+#define XTTCPS_CLK_CNTRL_PS_EN_MASK         0x00000001U  /**< Prescale enable */<br>+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU  /**< Prescale value */<br>+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT                  1U  /**< Prescale shift */<br>+#define XTTCPS_CLK_CNTRL_PS_DISABLE                           16U  /**< Prescale disable */<br>+#define XTTCPS_CLK_CNTRL_SRC_MASK           0x00000020U  /**< Clock source */<br>+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK  0x00000040U  /**< External Clock edge */<br>+/* @} */<br>+<br>+/** @name Counter Control Register<br>+ * Counter Control Register definitions<br>+ * @{<br>+ */<br>+#define XTTCPS_CNT_CNTRL_DIS_MASK             0x00000001U /**< Disable the counter */<br>+#define XTTCPS_CNT_CNTRL_INT_MASK          0x00000002U /**< Interval mode */<br>+#define XTTCPS_CNT_CNTRL_DECR_MASK               0x00000004U /**< Decrement mode */<br>+#define XTTCPS_CNT_CNTRL_MATCH_MASK             0x00000008U /**< Match mode */<br>+#define XTTCPS_CNT_CNTRL_RST_MASK           0x00000010U /**< Reset counter */<br>+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK    0x00000020U /**< Enable waveform */<br>+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */<br>+#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */<br>+/* @} */<br>+<br>+/** @name Current Counter Value Register<br>+ * Current Counter Value Register definitions<br>+ * @{<br>+ */<br>+#if defined(ARMA9)<br>+#define XTTCPS_COUNT_VALUE_MASK                0x0000FFFFU /**< 16-bit counter value */<br>+#else<br>+#define XTTCPS_COUNT_VALUE_MASK           0xFFFFFFFFU /**< 32-bit counter value */<br>+#endif<br>+/* @} */<br>+<br>+/** @name Interval Value Register<br>+ * Interval Value Register is the maximum value the counter will count up or<br>+ * down to.<br>+ * @{<br>+ */<br>+#if defined(ARMA9)<br>+#define XTTCPS_INTERVAL_VAL_MASK       (u32)(0x0000FFFF) /**< 16-bit Interval value*/<br>+#else<br>+#define XTTCPS_INTERVAL_VAL_MASK    (u32)(0xFFFFFFFF) /**< 32-bit Interval value*/<br>+#endif<br>+/* @} */<br>+<br>+/** @name Match Registers<br>+ * Definitions for Match registers, each timer counter has three match<br>+ * registers.<br>+ * @{<br>+ */<br>+#if defined(ARMA9)<br>+#define XTTCPS_MATCH_MASK            0x0000FFFFU /**< 16-bit Match value */<br>+#else<br>+#define XTTCPS_MATCH_MASK           0xFFFFFFFFU /**< 32-bit Match value */<br>+#endif<br>+#define XTTCPS_NUM_MATCH_REG                        3U /**< Num of Match reg */<br>+/* @} */<br>+<br>+/** @name Interrupt Registers<br>+ * Following register bit mask is for all interrupt registers.<br>+ *<br>+ * @{<br>+ */<br>+#define XTTCPS_IXR_INTERVAL_MASK    0x00000001U  /**< Interval Interrupt */<br>+#define XTTCPS_IXR_MATCH_0_MASK           0x00000002U  /**< Match 1 Interrupt */<br>+#define XTTCPS_IXR_MATCH_1_MASK            0x00000004U  /**< Match 2 Interrupt */<br>+#define XTTCPS_IXR_MATCH_2_MASK            0x00000008U  /**< Match 3 Interrupt */<br>+#define XTTCPS_IXR_CNT_OVR_MASK            0x00000010U  /**< Counter Overflow */<br>+#define XTTCPS_IXR_ALL_MASK                 0x0000001FU  /**< All valid Interrupts */<br>+/* @} */<br>+<br>+<br>+/***************** Macros (Inline Functions) Definitions *********************/<br>+<br>+/****************************************************************************/<br>+/**<br>+*<br>+* Read the given Timer Counter register.<br>+*<br>+* @param        BaseAddress is the base address of the timer counter device.<br>+* @param RegOffset is the register offset to be read<br>+*<br>+* @return     The 32-bit value of the register<br>+*<br>+* @note          C-style signature:<br>+*          u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)<br>+*<br>+*****************************************************************************/<br>+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \<br>+    (Xil_In32((BaseAddress) + (u32)(RegOffset)))<br>+<br>+/****************************************************************************/<br>+/**<br>+*<br>+* Write the given Timer Counter register.<br>+*<br>+* @param        BaseAddress is the base address of the timer counter device.<br>+* @param RegOffset is the register offset to be written<br>+* @param       Data is the 32-bit value to write to the register<br>+*<br>+* @return       None.<br>+*<br>+* @note             C-style signature:<br>+*          void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,<br>+*             u32 Data)<br>+*<br>+*****************************************************************************/<br>+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \<br>+    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))<br>+<br>+/****************************************************************************/<br>+/**<br>+*<br>+* Calculate a match register offset using the Match Register index.<br>+*<br>+* @param  MatchIndex is the 0-2 value of the match register<br>+*<br>+* @return       MATCH_N_OFFSET.<br>+*<br>+* @note           C-style signature:<br>+*          u32 XTtcPs_Match_N_Offset(u8 MatchIndex)<br>+*<br>+*****************************************************************************/<br>+#define XTtcPs_Match_N_Offset(MatchIndex) \<br>+          ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))<br>+<br>+/************************** Function Prototypes ******************************/<br>+<br>+/************************** Variable Definitions *****************************/<br>+#ifdef __cplusplus<br>+}<br>+#endif<br>+#endif /* end of protection macro */<br>+/** @} */<br>diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/zynqmp.h b/bsps/arm/xilinx-zynqmp/include/bsp/zynqmp.h<br>new file mode 100644<br>index 0000000000..7a48810490<br>--- /dev/null<br>+++ b/bsps/arm/xilinx-zynqmp/include/bsp/zynqmp.h<br>@@ -0,0 +1,92 @@<br>+/*<br>+ * SPDX-License-Identifier: BSD-2-Clause<br>+ *<br>+ * Copyright (C) 2023 Reflex Aerospace GmbH<br>+ *<br>+ * Written by Philip Kirkpatrick <<a href="mailto:p.kirkpatrick@reflexaerospace.com">p.kirkpatrick@reflexaerospace.com</a>><br>+ *<br>+ * Redistribution and use in source and binary forms, with or without<br>+ * modification, are permitted provided that the following conditions<br>+ * are met:<br>+ * 1. Redistributions of source code must retain the above copyright<br>+ *    notice, this list of conditions and the following disclaimer.<br>+ * 2. Redistributions in binary form must reproduce the above copyright<br>+ *    notice, this list of conditions and the following disclaimer in the<br>+ *    documentation and/or other materials provided with the distribution.<br>+ *<br>+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>+ * POSSIBILITY OF SUCH DAMAGE.<br>+ */<br>+#ifndef LIBBSP_ARM_ZYNQMP<br>+#define LIBBSP_ARM_ZYNQMP<br>+<br>+/* Data derived from <a href="https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PS-I/O-Peripherals-Registers">https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PS-I/O-Peripherals-Registers</a> */<br>+<br>+/* LPD IO Peripherals */<br>+#define ZYNQMP_UART0 (0xFF000000)<br>+#define ZYNQMP_UART1 (0xFF010000)<br>+#define ZYNQMP_I2C0 (0xFF020000)<br>+#define ZYNQMP_I2C1 (0xFF030000)<br>+#define ZYNQMP_SPI0 (0xFF040000)<br>+#define ZYNQMP_SPI1 (0xFF050000)<br>+#define ZYNQMP_CAN0 (0xFF060000)<br>+#define ZYNQMP_CAN1 (0xFF070000)<br>+#define ZYNQMP_GPIO (0xFF0A0000)<br>+#define ZYNQMP_GEM0 (0xFF0B0000)<br>+#define ZYNQMP_GEM1 (0xFF0C0000)<br>+#define ZYNQMP_GEM2 (0xFF0D0000)<br>+#define ZYNQMP_GEM3 (0xFF0E0000)<br>+#define ZYNQMP_QSPI (0xFF0F0000)<br>+#define ZYNQMP_NAND (0xFF100000)<br>+#define ZYNQMP_SD0 (0xFF160000)<br>+#define ZYNQMP_SD1 (0xFF170000)<br>+#define ZYNQMP_IPI_MSG (0xFF990000)<br>+#define ZYNQMP_USB0 (0xFF9D0000)<br>+#define ZYNQMP_USB1 (0xFF9E0000)<br>+#define ZYNQMP_AMS (0xFFA50000)<br>+#define ZYNQMP_PSSYSMON (0xFFA50800)<br>+#define ZYNQMP_PLSYSMON (0xFFA50C00)<br>+#define ZYNQMP_CSU_SWDT (0xFFCB0000)<br>+<br>+/* FPD IO Peripherals */<br>+#define ZYNQMP_SATA (0xFD0C0000)<br>+#define ZYNQMP_PCIE (0xFD0E0000)<br>+#define ZYNQMP_PCIE_IN (0xFD0E0800)<br>+#define ZYNQMP_PCIE_EG (0xFD0E0C00)<br>+#define ZYNQMP_PCIE_DMA (0xFD0F0000)<br>+#define ZYNQMP_SIOU (0xFD3D0000)<br>+#define ZYNQMP_GTR (0xFD400000)<br>+#define ZYNQMP_PCIE_ATTR (0xFD480000)<br>+#define ZYNQMP_DP (0xFD4A0000)<br>+#define ZYNQMP_GPU (0xFD4B0000)<br>+#define ZYNQMP_DP_DMA (0xFD4C0000)<br>+<br>+/* LPD System Registers */<br>+#define ZYNQMP_IPI (0xFF300000)<br>+#define ZYNQMP_TTC0 (0xFF110000)<br>+#define ZYNQMP_TTC1 (0xFF120000)<br>+#define ZYNQMP_TTC2 (0xFF130000)<br>+#define ZYNQMP_TTC3 (0xFF140000)<br>+#define ZYNQMP_LPD_SWDT (0xFF150000)<br>+#define ZYNQMP_XPPU (0xFF980000)<br>+#define ZYNQMP_XPPU_SINK (0xFF9C0000)<br>+#define ZYNQMP_PL_LPD (0xFF9B0000)<br>+#define ZYNQMP_OCM (0xFFA00000)<br>+#define ZYNQMP_LPD_FPD (0xFFA10000)<br>+#define ZYNQMP_RTC (0xFFA60000)<br>+#define ZYNQMP_OCM_XMPU (0xFFA70000)<br>+#define ZYNQMP_LPD_DMA (0xFFA80000)<br>+#define ZYNQMP_CSU_DMA (0xFFC80000)<br>+#define ZYNQMP_CSU (0xFFCA0000)<br>+#define ZYNQMP_BBRAM (0xFFCD0000)<br>+<br>+#endif /* LIBBSP_ARM_ZYNQMP */<br>diff --git a/bsps/arm/xilinx-zynqmp/start/bspsmp.c b/bsps/arm/xilinx-zynqmp/start/bspsmp.c<br>index 28a4b6d54d..4129e6dd59 100644<br>--- a/bsps/arm/xilinx-zynqmp/start/bspsmp.c<br>+++ b/bsps/arm/xilinx-zynqmp/start/bspsmp.c<br>@@ -34,6 +34,7 @@<br> <br> #include <bsp/start.h><br> <br>+#ifdef ZYNQMP_PROC_UNIT_APU<br> bool _CPU_SMP_Start_processor(uint32_t cpu_index)<br> {<br>   /*<br>@@ -55,3 +56,11 @@ bool _CPU_SMP_Start_processor(uint32_t cpu_index)<br>    */<br>   return _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);<br> }<br>+<br>+#ifdef ZYNQMP_PROC_UNIT_RPU<br>+<br>+/*<br>+ * SMP not currently supported on RPU <br>+ */<br>+<br>+#endif<br>\ No newline at end of file<br>diff --git a/bsps/arm/xilinx-zynqmp/start/bspstart.c b/bsps/arm/xilinx-zynqmp/start/bspstart.c<br>index fe04ef4f8f..2825653557 100644<br>--- a/bsps/arm/xilinx-zynqmp/start/bspstart.c<br>+++ b/bsps/arm/xilinx-zynqmp/start/bspstart.c<br>@@ -38,6 +38,7 @@<br> <br> #include <libcpu/arm-cp15.h><br> <br>+#ifdef ZYNQMP_PROC_UNIT_APU<br> void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq)<br> {<br> #ifdef ARM_GENERIC_TIMER_FREQ<br>@@ -53,12 +54,15 @@ void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq)<br>   *irq = ZYNQMP_IRQ_NS_PHYS_TIMER;<br> #endif<br> }<br>+#endif<br> <br> void bsp_start(void)<br> {<br>   bsp_interrupt_initialize();<br>+#ifdef ZYNQMP_PROC_UNIT_APU<br>   rtems_cache_coherent_add_area(<br>     bsp_section_nocacheheap_begin,<br>     (uintptr_t) bsp_section_nocacheheap_size<br>   );<br>+#endif<br> }<br>diff --git a/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c b/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c<br>index ef76563a38..07f97fb5fd 100644<br>--- a/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c<br>+++ b/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c<br>@@ -35,12 +35,34 @@<br> <br> BSP_START_TEXT_SECTION void bsp_start_hook_0(void)<br> {<br>-  /* Nothing to do */<br>+  #ifdef ZYNQMP_PROC_UNIT_RPU<br>+      /*<br>+     * On reset, V will be set.  This points the exceptions to the FSBL's vectors.  The FSBL<br>+     * should clear this bit before booting RTEMS but in some debugging<br>+     * configurations the bit may not be.  The other bits should already be clear<br>+     * on reset.  Since the correct settings in these bits are critical,<br>+    * make sure SCTLR[M, I, A, C, V] are cleared.  Afterwards, exceptions are<br>+   * handled by RTEMS.<br>+     * Note 1: The APU also does these steps in start.S in _start in the #if block at line 401<br>+     * Note 2: Not all Arm R cores need this (like the TMS570).  So, this probably should<br>+     *         be in this hook and not in start.S<br>+      */<br>+<br>+    __asm__ volatile(<br>+      "mrc   p15, 0, r0, c1, c0, 0   \n"<br>+      "bic   r1, r0, #0x2800 \n"<br>+      "bic   r1, r1, #0x7 \n"<br>+      "mcr      p15, 0, r1, c1, c0, 0 \n"<br>+        : :);<br>+<br>+  #endif<br> }<br> <br> BSP_START_TEXT_SECTION void bsp_start_hook_1(void)<br> {<br>   bsp_start_copy_sections();<br>+#ifdef ZYNQMP_PROC_UNIT_APU<br>   zynqmp_setup_mmu_and_cache();<br>+#endif<br>   bsp_start_clear_bss();<br> }<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml<br>new file mode 100644<br>index 0000000000..829e9c9297<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml<br>@@ -0,0 +1,21 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-string: null<br>+- split: null<br>+- env-append: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2023 Reflex Aerospace GmbH (<a href="https://www.reflexaerospace.com/">https://www.reflexaerospace.com/</a>)<br>+default:<br>+- enabled-by: true<br>+  value:<br>+  - -march=armv7-r<br>+  - -mthumb<br>+  - -mfpu=vfpv3-d16<br>+  - -mfloat-abi=hard<br>+description: |<br>+  ABI flags<br>+enabled-by: true<br>+links: []<br>+name: ABI_FLAGS<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercureyxu5.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercureyxu5.yml<br>new file mode 100644<br>index 0000000000..1b8b16796a<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercureyxu5.yml<br>@@ -0,0 +1,94 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+arch: arm<br>+bsp: xilinx_zynqmp_mercuryxu5_rpu<br>+build-type: bsp<br>+cflags: []<br>+copyrights:<br>+- Copyright (C) 2023 Reflex Aerospace GmbH (<a href="https://www.reflexaerospace.com/">https://www.reflexaerospace.com/</a>)<br>+cppflags: []<br>+enabled-by: true<br>+family: xilinx-zynqmp<br>+includes: <br>+- bsps/include/xil/<br>+install:<br>+- destination: ${BSP_INCLUDEDIR}<br>+  source:<br>+  - bsps/arm/xilinx-zynqmp/include/bsp.h<br>+  - bsps/include/xil/xil_types.h<br>+  - bsps/include/xil/xil_assert.h<br>+  - bsps/include/xil/xil_io.h<br>+- destination: ${BSP_INCLUDEDIR}/bsp<br>+  source:<br>+  - bsps/arm/xilinx-zynqmp/include/bsp/irq.h<br>+  - bsps/arm/xilinx-zynqmp/include/bsp/xttcps_hw.h<br>+  - bsps/arm/xilinx-zynqmp/include/bsp/zynqmp.h<br>+links:<br>+- role: build-dependency<br>+  uid: ../grp<br>+- role: build-dependency<br>+  uid: ../start<br>+- role: build-dependency<br>+  uid: abi<br>+- role: build-dependency<br>+  uid: optclkfastidle<br>+- role: build-dependency<br>+  uid: optclkuart<br>+- role: build-dependency<br>+  uid: optconirq<br>+- role: build-dependency<br>+  uid: ../../optconminor<br>+- role: build-dependency<br>+  uid: optint0len<br>+- role: build-dependency<br>+  uid: optint0ori<br>+- role: build-dependency<br>+  uid: optint1len<br>+- role: build-dependency<br>+  uid: optint1ori<br>+- role: build-dependency<br>+  uid: optramlen<br>+- role: build-dependency<br>+  uid: optramori<br>+- role: build-dependency<br>+  uid: optresetvec<br>+- role: build-dependency<br>+  uid: optprocunitrpu<br>+- role: build-dependency<br>+  uid: ../../obj<br>+- role: build-dependency<br>+  uid: ../../objirq<br>+- role: build-dependency<br>+  uid: ../../objdevserialzynq<br>+- role: build-dependency<br>+  uid: ../../objdevspizynq<br>+- role: build-dependency<br>+  uid: ../../objdevspixil<br>+- role: build-dependency<br>+  uid: ../../objmem<br>+- role: build-dependency<br>+  uid: ../../opto0<br>+- role: build-dependency<br>+  uid: linkcmds<br>+- role: build-dependency<br>+  uid: ../../bspopts<br>+source:<br>+- bsps/shared/cache/nocache.c<br>+- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c<br>+- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c<br>+- bsps/arm/shared/start/bsp-start-memcpy.S<br>+- bsps/arm/xilinx-zynqmp/console/console-config.c<br>+- bsps/arm/xilinx-zynqmp/start/bspreset.c<br>+- bsps/arm/xilinx-zynqmp/start/bspstart.c<br>+- bsps/arm/xilinx-zynqmp/start/bspstarthooks.c<br>+- bsps/arm/xilinx-zynqmp/clock/clock-ttc.c<br>+- bsps/shared/dev/btimer/btimer-cpucounter.c<br>+- bsps/shared/dev/getentropy/getentropy-cpucounter.c<br>+- bsps/shared/dev/irq/arm-gicv2.c<br>+- bsps/shared/dev/irq/arm-gicv2-zynqmp.c<br>+- bsps/shared/dev/serial/console-termios.c<br>+- bsps/shared/irq/irq-default-handler.c<br>+- bsps/shared/start/bspfatal-default.c<br>+- bsps/shared/start/gettargethash-default.c<br>+- bsps/shared/start/sbrk.c<br>+- bsps/shared/start/stackalloc.c<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml<br>new file mode 100644<br>index 0000000000..6208dc4b12<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml<br>@@ -0,0 +1,41 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+build-type: config-file<br>+content: |<br>+  MEMORY {<br>+    RAM_INT_0 : ORIGIN = ${ZYNQMP_RAM_INT_0_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RAM_INT_0_LENGTH:#010x}<br>+    RAM_INT_1 : ORIGIN = ${ZYNQMP_RAM_INT_1_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RAM_INT_1_LENGTH:#010x}<br>+    RAM       : ORIGIN = ${ZYNQMP_RAM_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RAM_LENGTH:#010x} - ${ZYNQMP_RAM_ORIGIN:#010x}<br>+  }<br>+<br>+  REGION_ALIAS ("REGION_START",          RAM_INT_0);<br>+  REGION_ALIAS ("REGION_VECTOR",         RAM_INT_0);<br>+  REGION_ALIAS ("REGION_TEXT",           RAM);<br>+  REGION_ALIAS ("REGION_TEXT_LOAD",      RAM);<br>+  REGION_ALIAS ("REGION_RODATA",         RAM);<br>+  REGION_ALIAS ("REGION_RODATA_LOAD",    RAM);<br>+  REGION_ALIAS ("REGION_DATA",           RAM);<br>+  REGION_ALIAS ("REGION_DATA_LOAD",      RAM);<br>+  REGION_ALIAS ("REGION_FAST_TEXT",      RAM);<br>+  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);<br>+  REGION_ALIAS ("REGION_FAST_DATA",      RAM);<br>+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);<br>+  REGION_ALIAS ("REGION_BSS",            RAM);<br>+  REGION_ALIAS ("REGION_WORK",           RAM);<br>+  REGION_ALIAS ("REGION_STACK",          RAM);<br>+  REGION_ALIAS ("REGION_NOCACHE",        RAM);<br>+  REGION_ALIAS ("REGION_NOCACHE_LOAD",   RAM);<br>+<br>+  bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;<br>+<br>+  bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;<br>+<br>+  bsp_vector_table_in_start_section = 1;<br>+<br>+  INCLUDE linkcmds.armv4<br>+copyrights:<br>+- Copyright (C) 2023 Reflex Aerospace GmbH (<a href="https://www.reflexaerospace.com/">https://www.reflexaerospace.com/</a>)<br>+enabled-by: true<br>+install-path: ${BSP_LIBDIR}<br>+links: []<br>+target: linkcmds<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml<br>new file mode 100644<br>index 0000000000..e303a8bf9f<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml<br>@@ -0,0 +1,21 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-boolean: null<br>+- define-condition: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by:<br>+  - arm/lm3s6965_qemu<br>+  - arm/realview_pbx_a9_qemu<br>+  - arm/xilinx_zynq_a9_qemu<br>+  value: true<br>+- enabled-by: true<br>+  value: false<br>+description: |<br>+  This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing.  This can significantly reduce simulation times.<br>+enabled-by: true<br>+links: []<br>+name: CLOCK_DRIVER_USE_FAST_IDLE<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml<br>new file mode 100644<br>index 0000000000..77c8f30fff<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml<br>@@ -0,0 +1,17 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-integer: null<br>+- define: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by: true<br>+  value: 100000000<br>+description: |<br>+  Zynq UART clock frequency in Hz<br>+enabled-by: true<br>+format: '{}'<br>+links: []<br>+name: ZYNQ_CLOCK_UART<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml<br>new file mode 100644<br>index 0000000000..ea13fa4561<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml<br>@@ -0,0 +1,16 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-boolean: null<br>+- define-condition: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by: true<br>+  value: true<br>+description: |<br>+  use interrupt driven mode for console devices (used by default)<br>+enabled-by: true<br>+links: []<br>+name: ZYNQ_CONSOLE_USE_INTERRUPTS<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml<br>new file mode 100644<br>index 0000000000..774d2c9269<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml<br>@@ -0,0 +1,18 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-integer: null<br>+- assert-uint32: null<br>+- env-assign: null<br>+- format-and-define: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by: true<br>+  value: 0x00010000<br>+description: ''<br>+enabled-by: true<br>+format: '{:#010x}'<br>+links: []<br>+name: ZYNQMP_RAM_INT_0_LENGTH<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml<br>new file mode 100644<br>index 0000000000..3fa03d3129<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml<br>@@ -0,0 +1,18 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-integer: null<br>+- assert-uint32: null<br>+- env-assign: null<br>+- format-and-define: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by: true<br>+  value: 0x00000000<br>+description: ''<br>+enabled-by: true<br>+format: '{:#010x}'<br>+links: []<br>+name: ZYNQMP_RAM_INT_0_ORIGIN<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml<br>new file mode 100644<br>index 0000000000..f179142ed4<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml<br>@@ -0,0 +1,18 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-integer: null<br>+- assert-uint32: null<br>+- env-assign: null<br>+- format-and-define: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by: true<br>+  value: 0x00010000<br>+description: ''<br>+enabled-by: true<br>+format: '{:#010x}'<br>+links: []<br>+name: ZYNQMP_RAM_INT_1_LENGTH<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml<br>new file mode 100644<br>index 0000000000..37bbf4fcd0<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml<br>@@ -0,0 +1,18 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-integer: null<br>+- assert-uint32: null<br>+- env-assign: null<br>+- format-and-define: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by: true<br>+  value: 0x00020000<br>+description: ''<br>+enabled-by: true<br>+format: '{:#010x}'<br>+links: []<br>+name: ZYNQMP_RAM_INT_1_ORIGIN<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml<br>new file mode 100644<br>index 0000000000..9298808b2a<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml<br>@@ -0,0 +1,17 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-boolean: null<br>+- define-condition: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2023 Reflex Aerospace GmbH (<a href="https://www.reflexaerospace.com/">https://www.reflexaerospace.com/</a>)<br>+default:<br>+- enabled-by: true<br>+  value: true<br>+description: |<br>+  Sets the target processing unit to the RPU (R5F) cores.<br>+enabled-by: true<br>+format: '{}'<br>+links: []<br>+name: ZYNQMP_PROC_UNIT_RPU<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml<br>new file mode 100644<br>index 0000000000..5cb5e805cf<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml<br>@@ -0,0 +1,21 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-integer: null<br>+- assert-uint32: null<br>+- env-assign: null<br>+- format-and-define: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by: arm/xilinx_zynqmp_ultra96<br>+  value: 0x80000000<br>+- enabled-by: true<br>+  value: 0x10000000<br>+description: |<br>+  override a BSP's default RAM length<br>+enabled-by: true<br>+format: '{:#010x}'<br>+links: []<br>+name: ZYNQMP_RAM_LENGTH<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml<br>new file mode 100644<br>index 0000000000..6269b662e0<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml<br>@@ -0,0 +1,19 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-integer: null<br>+- assert-uint32: null<br>+- assert-aligned: 1048576<br>+- env-assign: null<br>+- format-and-define: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by: true<br>+  value: 0x00100000<br>+description: ''<br>+enabled-by: true<br>+format: '{:#010x}'<br>+links: []<br>+name: ZYNQMP_RAM_ORIGIN<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml<br>new file mode 100644<br>index 0000000000..bac5c79627<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml<br>@@ -0,0 +1,16 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-boolean: null<br>+- define-condition: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2020 embedded brains GmbH (<a href="http://www.embedded-brains.de">http://www.embedded-brains.de</a>)<br>+default:<br>+- enabled-by: true<br>+  value: false<br>+description: |<br>+  reset vector address for BSP start<br>+enabled-by: true<br>+links: []<br>+name: BSP_START_RESET_VECTOR<br>+type: build<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml<br>index 216cc88360..f14efc2957 100644<br>--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml<br>@@ -62,6 +62,8 @@ links:<br>   uid: optramori<br> - role: build-dependency<br>   uid: optresetvec<br>+- role: build-dependency<br>+  uid: optprocunitapu<br> - role: build-dependency<br>   uid: ../../obj<br> - role: build-dependency<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optprocunitapu.yml b/spec/build/bsps/arm/xilinx-zynqmp/optprocunitapu.yml<br>new file mode 100644<br>index 0000000000..6040891123<br>--- /dev/null<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp/optprocunitapu.yml<br>@@ -0,0 +1,17 @@<br>+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause<br>+actions:<br>+- get-boolean: null<br>+- define-condition: null<br>+build-type: option<br>+copyrights:<br>+- Copyright (C) 2023 Reflex Aerospace GmbH (<a href="https://www.reflexaerospace.com/">https://www.reflexaerospace.com/</a>)<br>+default:<br>+- enabled-by: true<br>+  value: true<br>+description: |<br>+  Sets the target processing unit to the APU (A53) cores.<br>+enabled-by: true<br>+format: '{}'<br>+links: []<br>+name: ZYNQMP_PROC_UNIT_APU<br>+type: build</div></div>