<div dir="ltr">This looks good as far as the functional content is concerned. As a nit, it looks like some unnecessary newlines were added in cgem_set_ref_clk() and the added if() conditional braces are inconsistent in their formatting so feel free to tweak those before commit.<br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Jun 15, 2023 at 12:48 AM <<a href="mailto:aaron.nyholm@unfoldedeffective.com">aaron.nyholm@unfoldedeffective.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: Aaron Nyholm <<a href="mailto:aaron.nyholm@southerninnovation.com" target="_blank">aaron.nyholm@southerninnovation.com</a>><br>
<br>
---<br>
 rtemsbsd/sys/arm64/xilinx/versal_slcr.c | 34 ++++++++++++++++++++++---<br>
 rtemsbsd/sys/arm64/xilinx/versal_slcr.h |  6 +++++<br>
 2 files changed, 36 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/rtemsbsd/sys/arm64/xilinx/versal_slcr.c b/rtemsbsd/sys/arm64/xilinx/versal_slcr.c<br>
index 74ebde91..1f4d48bc 100644<br>
--- a/rtemsbsd/sys/arm64/xilinx/versal_slcr.c<br>
+++ b/rtemsbsd/sys/arm64/xilinx/versal_slcr.c<br>
@@ -78,10 +78,13 @@ SYSCTL_NODE(_hw, OID_AUTO, versal, CTLFLAG_RD, 0, "Xilinx Versal ACAP SLCR");<br>
 int<br>
 cgem_set_ref_clk(int unit, int frequency)<br>
 {<br>
+<br>
        struct versal_slcr_softc *sc = versal_slcr_softc_p;<br>
        int div, last_error = 0;<br>
-       uint64_t clk_ctrl, pll_ctrl;<br>
+       uint64_t clk_ctrl, pll_ctrl, to_xpd_ctrl;<br>
        uint32_t clk_ctrl_val, pll_ctrl_val, pll_freq, pll_reset, pll_bypass;<br>
+       uint32_t clk_src_sel, to_xpd_ctrl_val, to_xpd_div, to_xpd_freq;<br>
+<br>
<br>
        if (!sc)<br>
                return (-1);<br>
@@ -126,15 +129,38 @@ cgem_set_ref_clk(int unit, int frequency)<br>
        }<br>
<br>
        /* Apply divider */<br>
-  pll_freq >>= (pll_ctrl_val & VERSAL_SLCR_PLL_CTRL_DIV_MASK) >> VERSAL_SLCR_PLL_CTRL_DIV_SHIFT;<br>
+       pll_freq >>= (pll_ctrl_val & VERSAL_SLCR_PLL_CTRL_DIV_MASK) >> VERSAL_SLCR_PLL_CTRL_DIV_SHIFT;<br>
+<br>
+       /* Check if routed through {X}PLL_TO_XPD_CLK to GEM{unit}_REF_CLK and adjust */<br>
+       clk_src_sel = (clk_ctrl_val & VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_MASK);<br>
+       to_xpd_ctrl = 0;<br>
+       if (clk_src_sel == VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_P_PLL)<br>
+       {<br>
+               to_xpd_ctrl = VERSAL_SLCR_PPLL_TO_XPD_CTRL;<br>
+       } else if (clk_src_sel == VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_N_PLL)<br>
+       {<br>
+               to_xpd_ctrl = VERSAL_SLCR_NPLL_TO_XPD_CTRL;<br>
+       }<br>
+<br>
+       if (to_xpd_ctrl != 0) {<br>
+               to_xpd_ctrl_val = RD4(sc, to_xpd_ctrl);<br>
+               to_xpd_div = (to_xpd_ctrl_val & VERSAL_SLCR_XPD_CLK_CTRL_DIVISOR_MASK);<br>
+               to_xpd_div = to_xpd_div >> VERSAL_SLCR_XPD_CTRL_DIV_SHIFT;<br>
+               if (to_xpd_div == 0) {<br>
+                       to_xpd_div = 1;<br>
+               }<br>
+               to_xpd_freq = pll_freq / to_xpd_div;<br>
+       } else {<br>
+               to_xpd_freq = pll_freq;<br>
+       }<br>
<br>
        /* Find suitable divisor. Linear search, not the fastest method but hey.<br>
         */<br>
        for (div = 1; div <= VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX; div++) {<br>
-    int div_freq = pll_freq / div;<br>
+               int div_freq = to_xpd_freq / div;<br>
                int error = abs(frequency - div_freq);<br>
                if (error >= last_error && last_error != 0) {<br>
-      div--;<br>
+                       div--;<br>
                        break;<br>
                }<br>
                last_error = error;<br>
diff --git a/rtemsbsd/sys/arm64/xilinx/versal_slcr.h b/rtemsbsd/sys/arm64/xilinx/versal_slcr.h<br>
index e1c967ac..121c1e0a 100644<br>
--- a/rtemsbsd/sys/arm64/xilinx/versal_slcr.h<br>
+++ b/rtemsbsd/sys/arm64/xilinx/versal_slcr.h<br>
@@ -78,6 +78,12 @@<br>
 #define   VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_R_PLL                (1<<0)<br>
 #define   VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_N_PLL                (3<<0)<br>
<br>
+#define VERSAL_SLCR_PPLL_TO_XPD_CTRL           (VERSAL_SLCR_CRF_OFFSET + 0x100)<br>
+#define VERSAL_SLCR_NPLL_TO_XPD_CTRL           (VERSAL_SLCR_CRF_OFFSET + 0x104)<br>
+#define   VERSAL_SLCR_XPD_CLK_CTRL_DIVISOR_MAX         0x3ff<br>
+#define   VERSAL_SLCR_XPD_CLK_CTRL_DIVISOR_MASK        (VERSAL_SLCR_XPD_CLK_CTRL_DIVISOR_MAX<<8)<br>
+#define   VERSAL_SLCR_XPD_CTRL_DIV_SHIFT               8<br>
+<br>
 #define VERSAL_DEFAULT_PS_CLK_FREQUENCY 33333333<br>
<br>
 #ifdef _KERNEL<br>
-- <br>
2.25.1<br>
<br>
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</blockquote></div>