<div dir="ltr"><div>I may have missed something. Commented in one place.</div><div><br></div><div>It looks like mostly spaces inside () and variable/parameter declaration changes.</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Jul 25, 2023 at 4:38 PM Gedare Bloom <<a href="mailto:gedare@rtems.org">gedare@rtems.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">---<br>
cpukit/score/cpu/arm/__aeabi_read_tp.c | 2 +-<br>
cpukit/score/cpu/arm/__tls_get_addr.c | 4 +-<br>
.../score/cpu/arm/aarch32-psma-init-default.c | 2 +-<br>
cpukit/score/cpu/arm/aarch32-psma-init.c | 82 ++++-----<br>
cpukit/score/cpu/arm/arm-exception-default.c | 6 +-<br>
.../score/cpu/arm/arm-exception-frame-print.c | 159 ++++++++----------<br>
cpukit/score/cpu/arm/armv4-sync-synchronize.c | 2 +-<br>
cpukit/score/cpu/arm/armv7-thread-idle.c | 4 +-<br>
.../score/cpu/arm/armv7m-context-initialize.c | 14 +-<br>
cpukit/score/cpu/arm/armv7m-context-restore.c | 4 +-<br>
.../score/cpu/arm/armv7m-exception-default.c | 26 +--<br>
.../cpu/arm/armv7m-exception-handler-get.c | 4 +-<br>
.../cpu/arm/armv7m-exception-handler-set.c | 19 +--<br>
.../cpu/arm/armv7m-exception-priority-get.c | 8 +-<br>
.../arm/armv7m-exception-priority-handler.c | 8 +-<br>
.../cpu/arm/armv7m-exception-priority-set.c | 8 +-<br>
cpukit/score/cpu/arm/armv7m-initialize.c | 2 +-<br>
cpukit/score/cpu/arm/armv7m-isr-dispatch.c | 20 +--<br>
cpukit/score/cpu/arm/armv7m-isr-enter-leave.c | 4 +-<br>
cpukit/score/cpu/arm/armv7m-isr-level-get.c | 2 +-<br>
cpukit/score/cpu/arm/armv7m-isr-level-set.c | 4 +-<br>
.../score/cpu/arm/armv7m-isr-vector-install.c | 8 +-<br>
.../cpu/arm/armv7m-multitasking-start-stop.c | 4 +-<br>
cpukit/score/cpu/arm/cpu.c | 51 +++---<br>
24 files changed, 209 insertions(+), 238 deletions(-)<br>
<br>
diff --git a/cpukit/score/cpu/arm/__aeabi_read_tp.c b/cpukit/score/cpu/arm/__aeabi_read_tp.c<br>
index 0f4eba8d9a..e3bc529f18 100644<br>
--- a/cpukit/score/cpu/arm/__aeabi_read_tp.c<br>
+++ b/cpukit/score/cpu/arm/__aeabi_read_tp.c<br>
@@ -37,8 +37,8 @@<br>
#include "config.h"<br>
#endif<br>
<br>
-#include <rtems/score/thread.h><br>
#include <rtems/score/percpu.h><br>
+#include <rtems/score/thread.h><br>
<br>
#ifndef RTEMS_SMP<br>
<br>
diff --git a/cpukit/score/cpu/arm/__tls_get_addr.c b/cpukit/score/cpu/arm/__tls_get_addr.c<br>
index 7ef42fdcb4..fe38368812 100644<br>
--- a/cpukit/score/cpu/arm/__tls_get_addr.c<br>
+++ b/cpukit/score/cpu/arm/__tls_get_addr.c<br>
@@ -47,8 +47,8 @@ void *__tls_get_addr(const TLS_Index *ti);<br>
void *__tls_get_addr(const TLS_Index *ti)<br>
{<br>
const Thread_Control *executing = _Thread_Get_executing();<br>
- void *tls_data = (char *) executing->Registers.thread_id<br>
- + _TLS_Get_thread_control_block_area_size();<br>
+ void *tls_data = (char *) executing->Registers.thread_id;<br>
+ tls_data += _TLS_Get_thread_control_block_area_size();<br>
<br>
assert(ti->module == 1);<br>
<br>
diff --git a/cpukit/score/cpu/arm/aarch32-psma-init-default.c b/cpukit/score/cpu/arm/aarch32-psma-init-default.c<br>
index 615e7a528a..8ef8b5233a 100644<br>
--- a/cpukit/score/cpu/arm/aarch32-psma-init-default.c<br>
+++ b/cpukit/score/cpu/arm/aarch32-psma-init-default.c<br>
@@ -42,7 +42,7 @@<br>
<br>
#if __ARM_ARCH >= 8 && __ARM_ARCH_PROFILE == 'R'<br>
<br>
-void _AArch32_PMSA_Initialize_default( void )<br>
+void _AArch32_PMSA_Initialize_default(void)<br>
{<br>
_AArch32_PMSA_Initialize(<br>
AARCH32_PMSA_MEM_ATTR(<br>
diff --git a/cpukit/score/cpu/arm/aarch32-psma-init.c b/cpukit/score/cpu/arm/aarch32-psma-init.c<br>
index 93a3673a98..b30cb5e308 100644<br>
--- a/cpukit/score/cpu/arm/aarch32-psma-init.c<br>
+++ b/cpukit/score/cpu/arm/aarch32-psma-init.c<br>
@@ -46,7 +46,7 @@<br>
#include <rtems/score/cpu.h><br>
<br>
#define AARCH32_PMSA_REGION_MAX \<br>
- ( ( AARCH32_MPUIR_REGION_MASK >> AARCH32_MPUIR_REGION_SHIFT ) + 1 )<br>
+ ((AARCH32_MPUIR_REGION_MASK >> AARCH32_MPUIR_REGION_SHIFT) + 1)<br>
<br>
static void _AArch32_PMSA_Configure(<br>
const AArch32_PMSA_Region *regions,<br>
@@ -57,36 +57,36 @@ static void _AArch32_PMSA_Configure(<br>
size_t ri;<br>
uint32_t sctlr;<br>
<br>
- for ( ri = 0 ; ri < region_used; ++ri ) {<br>
+ for ( ri = 0; ri < region_used; ++ri ) {<br>
uint32_t prbar;<br>
uint32_t prlar;<br>
uint32_t attr;<br>
<br>
- prbar = regions[ ri ].base;<br>
- prlar = regions[ ri ].limit;<br>
- attr = regions[ ri ].attributes;<br>
+ prbar = regions[ri].base;<br>
+ prlar = regions[ri].limit;<br>
+ attr = regions[ri].attributes;<br>
<br>
- prbar |= ( attr >> 6 ) & 0x3fU;<br>
+ prbar |= (attr >> 6) & 0x3fU;<br>
prlar |= attr & 0x3fU;<br>
<br>
- _AArch32_Write_prselr( ri );<br>
+ _AArch32_Write_prselr(ri);<br>
_ARM_Instruction_synchronization_barrier();<br>
- _AArch32_Write_prbar( prbar );<br>
- _AArch32_Write_prlar( prlar );<br>
+ _AArch32_Write_prbar(prbar);<br>
+ _AArch32_Write_prlar(prlar);<br>
}<br>
<br>
- for ( ri = region_used ; ri < region_max; ++ri ) {<br>
- _AArch32_Write_prselr( ri );<br>
+ for ( ri = region_used; ri < region_max; ++ri ) {<br>
+ _AArch32_Write_prselr(ri);<br>
_ARM_Instruction_synchronization_barrier();<br>
- _AArch32_Write_prbar( 0 );<br>
- _AArch32_Write_prlar( 0 );<br>
+ _AArch32_Write_prbar(0);<br>
+ _AArch32_Write_prlar(0);<br>
}<br>
<br>
_ARM_Data_synchronization_barrier();<br>
- sctlr = _AArch32_Read_sctlr();<br>
+ sctlr = _AArch32_Read_sctlr();<br>
sctlr |= AARCH32_SCTLR_M | AARCH32_SCTLR_I | AARCH32_SCTLR_C;<br>
- sctlr &= ~( AARCH32_SCTLR_A | AARCH32_SCTLR_BR );<br>
- _AArch32_Write_sctlr( sctlr );<br>
+ sctlr &= ~(AARCH32_SCTLR_A | AARCH32_SCTLR_BR);<br>
+ _AArch32_Write_sctlr(sctlr);<br>
_ARM_Instruction_synchronization_barrier();<br>
}<br>
<br>
@@ -109,16 +109,16 @@ size_t _AArch32_PMSA_Map_sections_to_regions(<br>
uint32_t attr;<br>
uint32_t limit;<br>
<br>
- base = sections[ si ].begin;<br>
- end = sections[ si ].end;<br>
- attr = sections[ si ].attributes;<br>
+ base = sections[si].begin;<br>
+ end = sections[si].end;<br>
+ attr = sections[si].attributes;<br>
<br>
if ( base == end ) {<br>
continue;<br>
}<br>
<br>
- base = RTEMS_ALIGN_DOWN( base, AARCH32_PMSA_MIN_REGION_ALIGN );<br>
- end = RTEMS_ALIGN_UP( end, AARCH32_PMSA_MIN_REGION_ALIGN );<br>
+ base = RTEMS_ALIGN_DOWN(base, AARCH32_PMSA_MIN_REGION_ALIGN);<br>
+ end = RTEMS_ALIGN_UP(end, AARCH32_PMSA_MIN_REGION_ALIGN);<br>
limit = end - AARCH32_PMSA_MIN_REGION_ALIGN;<br>
<br>
for ( ri = 0; ri < region_used; ++ri ) {<br>
@@ -126,16 +126,16 @@ size_t _AArch32_PMSA_Map_sections_to_regions(<br>
uint32_t region_limit;<br>
uint32_t region_attr;<br>
<br>
- region_base = regions[ ri ].base;<br>
- region_limit = regions[ ri ].limit;<br>
- region_attr = regions[ ri ].attributes;<br>
+ region_base = regions[ri].base;<br>
+ region_limit = regions[ri].limit;<br>
+ region_attr = regions[ri].attributes;<br>
<br>
if ( attr == region_attr ) {<br>
uint32_t region_end;<br>
<br>
if ( end - region_base <= AARCH32_PMSA_MIN_REGION_ALIGN ) {<br>
/* Extend the region */<br>
- regions[ ri ].base = base;<br>
+ regions[ri].base = base;<br>
break;<br>
}<br>
<br>
@@ -143,7 +143,7 @@ size_t _AArch32_PMSA_Map_sections_to_regions(<br>
<br>
if ( region_end - base <= AARCH32_PMSA_MIN_REGION_ALIGN ) {<br>
/* Extend the region */<br>
- regions[ ri ].limit = limit;<br>
+ regions[ri].limit = limit;<br>
break;<br>
}<br>
<br>
@@ -161,14 +161,14 @@ size_t _AArch32_PMSA_Map_sections_to_regions(<br>
}<br>
<br>
for ( i = region_used; i > ri; --i ) {<br>
- regions[ i ] = regions[ i - 1 ];<br>
+ regions[i] = regions[i - 1];<br>
}<br>
<br>
/* New first region */<br>
++region_used;<br>
- regions[ ri ].base = base;<br>
- regions[ ri ].limit = limit;<br>
- regions[ ri ].attributes = attr;<br>
+ regions[ri].base = base;<br>
+ regions[ri].limit = limit;<br>
+ regions[ri].attributes = attr;<br>
break;<br>
}<br>
}<br>
@@ -180,9 +180,9 @@ size_t _AArch32_PMSA_Map_sections_to_regions(<br>
<br>
/* New last region */<br>
++region_used;<br>
- regions[ ri ].base = base;<br>
- regions[ ri ].limit = limit;<br>
- regions[ ri ].attributes = attr;<br>
+ regions[ri].base = base;<br>
+ regions[ri].limit = limit;<br>
+ regions[ri].attributes = attr;<br>
}<br>
}<br>
<br>
@@ -196,15 +196,15 @@ void _AArch32_PMSA_Initialize(<br>
size_t section_count<br>
)<br>
{<br>
- AArch32_PMSA_Region regions[ AARCH32_PMSA_REGION_MAX ];<br>
- size_t region_max;<br>
- size_t region_used;<br>
+ AArch32_PMSA_Region regions[AARCH32_PMSA_REGION_MAX];<br>
+ size_t region_max;<br>
+ size_t region_used;<br>
<br>
- _AArch32_Write_mair0( memory_attributes_0 );<br>
- _AArch32_Write_mair1( memory_attributes_1 );<br>
+ _AArch32_Write_mair0(memory_attributes_0);<br>
+ _AArch32_Write_mair1(memory_attributes_1);<br>
<br>
- region_max = ( _AArch32_Read_mpuir() & AARCH32_MPUIR_REGION_MASK ) >><br>
- AARCH32_MPUIR_REGION_SHIFT;<br>
+ region_max = (_AArch32_Read_mpuir() & AARCH32_MPUIR_REGION_MASK) >><br>
+ AARCH32_MPUIR_REGION_SHIFT;<br>
<br>
region_used = _AArch32_PMSA_Map_sections_to_regions(<br>
sections,<br>
@@ -214,7 +214,7 @@ void _AArch32_PMSA_Initialize(<br>
);<br>
<br>
if ( region_used > 0 ) {<br>
- _AArch32_PMSA_Configure( regions, region_used, region_max );<br>
+ _AArch32_PMSA_Configure(regions, region_used, region_max);<br>
}<br>
}<br>
<br>
diff --git a/cpukit/score/cpu/arm/arm-exception-default.c b/cpukit/score/cpu/arm/arm-exception-default.c<br>
index 02df769287..190c2bf68d 100644<br>
--- a/cpukit/score/cpu/arm/arm-exception-default.c<br>
+++ b/cpukit/score/cpu/arm/arm-exception-default.c<br>
@@ -38,10 +38,10 @@<br>
#include "config.h"<br>
#endif<br>
<br>
-#include <rtems/score/cpu.h><br>
#include <rtems/fatal.h><br>
+#include <rtems/score/cpu.h><br>
<br>
-void _ARM_Exception_default( CPU_Exception_frame *frame )<br>
+void _ARM_Exception_default(CPU_Exception_frame *frame)<br>
{<br>
- rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );<br>
+ rtems_fatal(RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame);<br>
}<br>
diff --git a/cpukit/score/cpu/arm/arm-exception-frame-print.c b/cpukit/score/cpu/arm/arm-exception-frame-print.c<br>
index b089648184..c625cf2479 100644<br>
--- a/cpukit/score/cpu/arm/arm-exception-frame-print.c<br>
+++ b/cpukit/score/cpu/arm/arm-exception-frame-print.c<br>
@@ -46,12 +46,12 @@<br>
#endif<br>
#include <rtems/bspIo.h><br>
<br>
-static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )<br>
+static void _ARM_VFP_context_print(const ARM_VFP_context *vfp_context)<br>
{<br>
#ifdef ARM_MULTILIB_VFP<br>
if ( vfp_context != NULL ) {<br>
const uint64_t *dx = &vfp_context->register_d0;<br>
- int i;<br>
+ int i;<br>
<br>
printk(<br>
"FPEXC = 0x%08" PRIx32 "\nFPSCR = 0x%08" PRIx32 "\n",<br>
@@ -67,138 +67,119 @@ static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )<br>
int regcount = 0;<br>
#endif<br>
for ( i = 0; i < regcount; ++i ) {<br>
- uint32_t low = (uint32_t) dx[i];<br>
+ uint32_t low = (uint32_t) dx[i];<br>
uint32_t high = (uint32_t) (dx[i] >> 32);<br>
<br>
- printk( "D%02i = 0x%08" PRIx32 "%08" PRIx32 "\n", i, high, low );<br>
+ printk("D%02i = 0x%08" PRIx32 "%08" PRIx32 "\n", i, high, low);<br>
}<br>
}<br>
#endif<br>
}<br>
<br>
-static void _ARM_Cortex_M_fault_info_print( void )<br>
+static void _ARM_Cortex_M_fault_info_print(void)<br>
{<br>
#if defined(ARM_MULTILIB_ARCH_V7M)<br>
/*<br>
* prints content of additional debugging registers<br>
* available on Cortex-Mx where x > 0 cores.<br>
*/<br>
- uint32_t cfsr = _ARMV7M_SCB->cfsr;<br>
- uint8_t mmfsr = ARMV7M_SCB_CFSR_MMFSR_GET( cfsr );<br>
- uint8_t bfsr = ( ARMV7M_SCB_CFSR_BFSR_GET( cfsr ) >> 8 );<br>
- uint16_t ufsr = ( ARMV7M_SCB_CFSR_UFSR_GET( cfsr ) >> 16 );<br>
- uint32_t hfsr = _ARMV7M_SCB->hfsr;<br>
+ uint32_t cfsr = _ARMV7M_SCB->cfsr;<br>
+ uint8_t mmfsr = ARMV7M_SCB_CFSR_MMFSR_GET(cfsr);<br>
+ uint8_t bfsr = (ARMV7M_SCB_CFSR_BFSR_GET(cfsr) >> 8);<br>
+ uint16_t ufsr = (ARMV7M_SCB_CFSR_UFSR_GET(cfsr) >> 16);<br>
+ uint32_t hfsr = _ARMV7M_SCB->hfsr;<br>
if ( mmfsr > 0 ) {<br>
- printk( "MMFSR= 0x%08" PRIx32 " (memory fault)\n", mmfsr );<br>
- if ( ( mmfsr & 0x1 ) != 0 ) {<br>
- printk( " IACCVIOL : 1 (instruction access violation)\n" );<br>
+ printk("MMFSR= 0x%08" PRIx32 " (memory fault)\n", mmfsr);<br>
+ if ( (mmfsr & 0x1) != 0 ) {<br>
+ printk(" IACCVIOL : 1 (instruction access violation)\n");<br>
}<br>
- if ( ( mmfsr & 0x2 ) != 0 ) {<br>
- printk( " DACCVIOL : 1 (data access violation)\n" );<br>
+ if ( (mmfsr & 0x2) != 0 ) {<br>
+ printk(" DACCVIOL : 1 (data access violation)\n");<br>
}<br>
- if ( (mmfsr & 0x8 ) != 0 ) {<br>
- printk(<br>
- " MUNSTKERR : 1 (fault on unstacking on exception return)\n"<br>
- );<br>
+ if ( (mmfsr & 0x8) != 0 ) {<br>
+ printk(" MUNSTKERR : 1 (fault on unstacking on exception return)\n");<br>
}<br>
- if ( ( mmfsr & 0x10 ) != 0 ) {<br>
- printk( " MSTKERR : 1 (fault on stacking on exception entry)\n" );<br>
+ if ( (mmfsr & 0x10) != 0 ) {<br>
+ printk(" MSTKERR : 1 (fault on stacking on exception entry)\n");<br>
}<br>
- if ( (mmfsr & 0x20 ) != 0 ) {<br>
- printk( " MLSPERR : 1 (fault during lazy FP stack preservation)\n" );<br>
+ if ( (mmfsr & 0x20) != 0 ) {<br>
+ printk(" MLSPERR : 1 (fault during lazy FP stack preservation)\n");<br>
}<br>
- if ( (mmfsr & 0x80 ) != 0 ) {<br>
+ if ( (mmfsr & 0x80) != 0 ) {<br>
printk(<br>
" MMFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n",<br>
- _ARMV7M_SCB->mmfar<br>
+ _ARMV7M_SCB->mmfar<br>
);<br>
- }<br>
- else {<br>
- printk( " MMFARVALID : 0 (undetermined error address)\n" );<br>
+ } else {<br>
+ printk(" MMFARVALID : 0 (undetermined error address)\n");<br>
}<br>
}<br>
if ( bfsr > 0 ) {<br>
- printk( "BFSR = 0x%08" PRIx32 " (bus fault)\n", bfsr );<br>
- if ( ( bfsr & 0x1 ) != 0 ) {<br>
- printk( " IBUSERR : 1 (instruction fetch error)\n" );<br>
+ printk("BFSR = 0x%08" PRIx32 " (bus fault)\n", bfsr);<br>
+ if ( (bfsr & 0x1) != 0 ) {<br>
+ printk(" IBUSERR : 1 (instruction fetch error)\n");<br>
}<br>
- if ( (bfsr & 0x2 ) != 0 ) {<br>
- printk(<br>
- " PRECISERR : 1 (data bus error with known exact location)\n"<br>
- );<br>
+ if ( (bfsr & 0x2) != 0 ) {<br>
+ printk(" PRECISERR : 1 (data bus error with known exact location)\n");<br>
}<br>
- if ( ( bfsr & 0x4) != 0 ) {<br>
- printk(<br>
- " IMPRECISERR: 1 (data bus error without known exact location)\n"<br>
+ if ( (bfsr & 0x4) != 0 ) {<br>
+ printk(" IMPRECISERR: 1 (data bus error without known exact location)\n"<br>
);<br>
}<br>
- if ( (bfsr & 0x8 ) != 0 ) {<br>
- printk(<br>
- " UNSTKERR : 1 (fault on unstacking on exception return)\n"<br>
- );<br>
+ if ( (bfsr & 0x8) != 0 ) {<br>
+ printk(" UNSTKERR : 1 (fault on unstacking on exception return)\n");<br>
}<br>
- if ( ( bfsr & 0x10 ) != 0 ) {<br>
- printk( " STKERR : 1 (fault on stacking on exception entry)\n" );<br>
+ if ( (bfsr & 0x10) != 0 ) {<br>
+ printk(" STKERR : 1 (fault on stacking on exception entry)\n");<br>
}<br>
- if ( ( bfsr & 0x20 ) != 0 ) {<br>
- printk( " LSPERR : 1 (fault during lazy FP stack preservation)\n" );<br>
+ if ( (bfsr & 0x20) != 0 ) {<br>
+ printk(" LSPERR : 1 (fault during lazy FP stack preservation)\n");<br>
}<br>
- if ( (bfsr & 0x80 ) != 0 ) {<br>
+ if ( (bfsr & 0x80) != 0 ) {<br>
printk(<br>
" BFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n",<br>
- _ARMV7M_SCB->bfar<br>
+ _ARMV7M_SCB->bfar<br>
);<br>
- }<br>
- else {<br>
- printk( " BFARVALID : 0 (undetermined error address)\n" );<br>
+ } else {<br>
+ printk(" BFARVALID : 0 (undetermined error address)\n");<br>
}<br>
}<br>
if ( ufsr > 0 ) {<br>
- printk( "UFSR = 0x%08" PRIx32 " (usage fault)\n", ufsr);<br>
- if ( (ufsr & 0x1 ) != 0 ) {<br>
- printk( " UNDEFINSTR : 1 (undefined instruction issued)\n");<br>
+ printk("UFSR = 0x%08" PRIx32 " (usage fault)\n", ufsr);<br>
+ if ( (ufsr & 0x1) != 0 ) {<br>
+ printk(" UNDEFINSTR : 1 (undefined instruction issued)\n");<br>
}<br>
- if ( (ufsr & 0x2 ) != 0 ) {<br>
- printk(<br>
- " INVSTATE : 1"<br>
- " (invalid instruction state"<br>
- " (Thumb not set in EPSR or invalid IT state in EPSR))\n"<br>
- );<br>
+ if ( (ufsr & 0x2) != 0 ) {<br>
+ printk(" INVSTATE : 1"<br>
+ " (invalid instruction state"<br>
+ " (Thumb not set in EPSR or invalid IT state in EPSR))\n");<br>
}<br>
- if ( (ufsr & 0x4 ) != 0 ) {<br>
- printk( " INVPC : 1 (integrity check failure on EXC_RETURN)\n" );<br>
+ if ( (ufsr & 0x4) != 0 ) {<br>
+ printk(" INVPC : 1 (integrity check failure on EXC_RETURN)\n");<br>
}<br>
- if ( (ufsr & 0x8 ) != 0 ) {<br>
- printk(<br>
- " NOCP : 1"<br>
- " (coprocessor instruction issued"<br>
- " but coprocessor disabled or non existent)\n"<br>
- );<br>
+ if ( (ufsr & 0x8) != 0 ) {<br>
+ printk(" NOCP : 1"<br>
+ " (coprocessor instruction issued"<br>
+ " but coprocessor disabled or non existent)\n");<br>
}<br>
- if ( ( ufsr & 0x100) != 0 ) {<br>
- printk( " UNALIGNED : 1 (unaligned access operation occurred)\n" );<br>
+ if ( (ufsr & 0x100) != 0 ) {<br>
+ printk(" UNALIGNED : 1 (unaligned access operation occurred)\n");<br>
}<br>
- if ( ( ufsr & 0x200) != 0 ) {<br>
- printk( " DIVBYZERO : 1 (division by zero)" );<br>
+ if ( (ufsr & 0x200) != 0 ) {<br>
+ printk(" DIVBYZERO : 1 (division by zero)");<br>
}<br>
}<br>
- if ( (hfsr & (<br>
- ARMV7M_SCB_HFSR_VECTTBL_MASK<br>
- | ARMV7M_SCB_HFSR_DEBUGEVT_MASK<br>
- | ARMV7M_SCB_HFSR_FORCED_MASK<br>
- ) ) != 0 ) {<br>
- printk( "HFSR = 0x%08" PRIx32 " (hard fault)\n", hfsr );<br>
- if ( (hfsr & ARMV7M_SCB_HFSR_VECTTBL_MASK ) != 0 ) {<br>
- printk(<br>
- " VECTTBL : 1 (error in address located in vector table)\n"<br>
- );<br>
- }<br>
- if ( (hfsr & ARMV7M_SCB_HFSR_FORCED_MASK ) != 0 ) {<br>
- printk(<br>
- " FORCED : 1 (configurable fault escalated to hard fault)\n"<br>
+ if ( (hfsr & (ARMV7M_SCB_HFSR_VECTTBL_MASK | ARMV7M_SCB_HFSR_DEBUGEVT_MASK |<br>
+ ARMV7M_SCB_HFSR_FORCED_MASK)) != 0 ) {<br>
+ printk("HFSR = 0x%08" PRIx32 " (hard fault)\n", hfsr);<br>
+ if ( (hfsr & ARMV7M_SCB_HFSR_VECTTBL_MASK) != 0 ) {<br>
+ printk(" VECTTBL : 1 (error in address located in vector table)\n");<br>
+ }<br>
+ if ( (hfsr & ARMV7M_SCB_HFSR_FORCED_MASK) != 0 ) {<br>
+ printk(" FORCED : 1 (configurable fault escalated to hard fault)\n"<br>
);<br>
}<br>
- if ( (hfsr & ARMV7M_SCB_HFSR_DEBUGEVT_MASK ) != 0 ) {<br>
+ if ( (hfsr & ARMV7M_SCB_HFSR_DEBUGEVT_MASK) != 0 ) {<br>
printk(<br>
" DEBUGEVT : 1 (debug event occurred with debug system disabled)\n"<br>
);<br>
@@ -206,7 +187,7 @@ static void _ARM_Cortex_M_fault_info_print( void )<br>
}<br>
#endif<br>
}<br>
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )<br>
+void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)<br>
{<br>
printk(<br>
"\n"<br>
@@ -248,6 +229,6 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )<br>
(intptr_t) frame->vector<br>
);<br>
<br>
- _ARM_VFP_context_print( frame->vfp_context );<br>
+ _ARM_VFP_context_print(frame->vfp_context);<br>
_ARM_Cortex_M_fault_info_print();<br>
}<br>
diff --git a/cpukit/score/cpu/arm/armv4-sync-synchronize.c b/cpukit/score/cpu/arm/armv4-sync-synchronize.c<br>
index 2f454306d8..82b0a69566 100644<br>
--- a/cpukit/score/cpu/arm/armv4-sync-synchronize.c<br>
+++ b/cpukit/score/cpu/arm/armv4-sync-synchronize.c<br>
@@ -35,7 +35,7 @@<br>
<br>
#include <rtems/score/cpu.h><br>
<br>
-void __sync_synchronize( void )<br>
+void __sync_synchronize(void)<br>
{<br>
_ARM_Data_memory_barrier();<br>
}<br>
diff --git a/cpukit/score/cpu/arm/armv7-thread-idle.c b/cpukit/score/cpu/arm/armv7-thread-idle.c<br>
index 720cb2be83..c4e8e66210 100644<br>
--- a/cpukit/score/cpu/arm/armv7-thread-idle.c<br>
+++ b/cpukit/score/cpu/arm/armv7-thread-idle.c<br>
@@ -40,8 +40,7 @@<br>
<br>
#include <rtems/score/cpu.h><br>
<br>
-<br>
-void *_CPU_Thread_Idle_body( uintptr_t ignored )<br>
+void *_CPU_Thread_Idle_body(uintptr_t ignored)<br>
{<br>
while ( true ) {<br>
#ifdef ARM_MULTILIB_HAS_WFI<br>
@@ -49,4 +48,3 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )<br>
#endif /* ARM_MULTILIB_HAS_WFI */<br>
}<br>
}<br>
-<br>
diff --git a/cpukit/score/cpu/arm/armv7m-context-initialize.c b/cpukit/score/cpu/arm/armv7m-context-initialize.c<br>
index d67bcf93b5..b0cfbccef2 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-context-initialize.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-context-initialize.c<br>
@@ -48,12 +48,12 @@<br>
<br>
void _CPU_Context_Initialize(<br>
Context_Control *context,<br>
- void *stack_area_begin,<br>
- size_t stack_area_size,<br>
- uint32_t new_level,<br>
- void (*entry_point)( void ),<br>
- bool is_fp,<br>
- void *tls_area<br>
+ void *stack_area_begin,<br>
+ size_t stack_area_size,<br>
+ uint32_t new_level,<br>
+ void (*entry_point)(void),<br>
+ bool is_fp,<br>
+ void *tls_area<br>
)<br>
{<br>
char *stack_area_end = (char *) stack_area_begin + stack_area_size;<br>
@@ -64,7 +64,7 @@ void _CPU_Context_Initialize(<br>
context->register_sp = stack_area_end;<br>
<br>
if ( tls_area != NULL ) {<br>
- context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area );<br>
+ context->thread_id = (uint32_t) _TLS_Initialize_area(tls_area);<br>
}<br>
}<br>
<br>
diff --git a/cpukit/score/cpu/arm/armv7m-context-restore.c b/cpukit/score/cpu/arm/armv7m-context-restore.c<br>
index b888abe29f..625a33c626 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-context-restore.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-context-restore.c<br>
@@ -43,9 +43,7 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-void __attribute__((naked)) _CPU_Context_restore(<br>
- Context_Control *heir<br>
-)<br>
+void __attribute__((naked)) _CPU_Context_restore(Context_Control *heir)<br>
{<br>
__asm__ volatile (<br>
"movw r2, #:lower16:_Per_CPU_Information\n"<br>
diff --git a/cpukit/score/cpu/arm/armv7m-exception-default.c b/cpukit/score/cpu/arm/armv7m-exception-default.c<br>
index 35dde50dc3..6d3eb49ea0 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-exception-default.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-exception-default.c<br>
@@ -42,21 +42,21 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-void __attribute__((naked)) _ARMV7M_Exception_default( void )<br>
+void __attribute__((naked)) _ARMV7M_Exception_default(void)<br>
{<br>
- /* On exception entry, ARMv7M saves context state onto a stack pointed to<br>
- * by either MSP or PSP. The value stored in LR indicates whether we were<br>
- * in Thread or Handler mode, whether we were using the FPU (if any),<br>
- * and which stack pointer we were using.<br>
- * In particular, bit 2 of LR will be 0 if we were using MSP.<br>
- *<br>
- * For a more detailed explanation, see the Exception Entry Behavior<br>
- * section of the ARMv7M Architecture Reference Manual.<br>
- */<br>
+ /* On exception entry, ARMv7M saves context state onto a stack pointed to<br>
+ * by either MSP or PSP. The value stored in LR indicates whether we were<br>
+ * in Thread or Handler mode, whether we were using the FPU (if any),<br>
+ * and which stack pointer we were using.<br>
+ * In particular, bit 2 of LR will be 0 if we were using MSP.<br>
+ *<br>
+ * For a more detailed explanation, see the Exception Entry Behavior<br>
+ * section of the ARMv7M Architecture Reference Manual.<br>
+ */<br>
<br>
- /* As we're in Handler mode here, we'll always operate on MSP.<br>
- * However, we need to store the right SP in our CPU_Exception_frame.<br>
- */<br>
+ /* As we're in Handler mode here, we'll always operate on MSP.<br>
+ * However, we need to store the right SP in our CPU_Exception_frame.<br>
+ */<br>
__asm__ volatile (<br>
"sub sp, %[cpufsz]\n" /* Allocate space for a CPU_Exception_frame. */<br>
"stm sp, {r0-r12}\n"<br>
diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c<br>
index 41effd1e18..c26d783723 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c<br>
@@ -43,9 +43,9 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-ARMV7M_Exception_handler _ARMV7M_Get_exception_handler( int index )<br>
+ARMV7M_Exception_handler _ARMV7M_Get_exception_handler(int index)<br>
{<br>
- return _ARMV7M_SCB->vtor [index];<br>
+ return _ARMV7M_SCB->vtor[index];<br>
}<br>
<br>
#endif /* ARM_MULTILIB_ARCH_V7M */<br>
diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c<br>
index 94c9dc5360..9dd81a5df7 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c<br>
@@ -38,25 +38,22 @@<br>
#include "config.h"<br>
#endif<br>
<br>
-#include <rtems/score/armv7m.h><br>
#include <rtems/rtems/cache.h><br>
+#include <rtems/score/armv7m.h><br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-void _ARMV7M_Set_exception_handler(<br>
- int index,<br>
- ARMV7M_Exception_handler handler<br>
-)<br>
+void _ARMV7M_Set_exception_handler(int index, ARMV7M_Exception_handler handler)<br>
{<br>
- if ( _ARMV7M_SCB->vtor [index] != handler ) {<br>
- _ARMV7M_SCB->vtor [index] = handler;<br>
+ if ( _ARMV7M_SCB->vtor[index] != handler ) {<br>
+ _ARMV7M_SCB->vtor[index] = handler;<br>
rtems_cache_flush_multiple_data_lines(<br>
- &_ARMV7M_SCB->vtor [index],<br>
- sizeof(_ARMV7M_SCB->vtor [index])<br>
+ &_ARMV7M_SCB->vtor[index],<br>
+ sizeof(_ARMV7M_SCB->vtor[index])<br>
);<br>
rtems_cache_invalidate_multiple_instruction_lines(<br>
- &_ARMV7M_SCB->vtor [index],<br>
- sizeof(_ARMV7M_SCB->vtor [index])<br>
+ &_ARMV7M_SCB->vtor[index],<br>
+ sizeof(_ARMV7M_SCB->vtor[index])<br>
);<br>
}<br>
}<br>
diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c<br>
index bb0892a32f..fdcc2f0f68 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c<br>
@@ -42,12 +42,12 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-int _ARMV7M_Get_exception_priority( int vector )<br>
+int _ARMV7M_Get_exception_priority(int vector)<br>
{<br>
- if ( _ARMV7M_Is_vector_an_irq( vector ) ) {<br>
- return _ARMV7M_NVIC_Get_priority( ARMV7M_IRQ_OF_VECTOR( vector ) );<br>
+ if ( _ARMV7M_Is_vector_an_irq(vector) ) {<br>
+ return _ARMV7M_NVIC_Get_priority(ARMV7M_IRQ_OF_VECTOR(vector));<br>
} else if ( vector >= ARMV7M_VECTOR_MEM_MANAGE ) {<br>
- return _ARMV7M_SCB->shpr [vector - 4];<br>
+ return _ARMV7M_SCB->shpr[vector - 4];<br>
} else {<br>
return vector - 4;<br>
}<br>
diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c<br>
index b94366e07c..7f868fed79 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c<br>
@@ -43,13 +43,13 @@<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
void _ARMV7M_Set_exception_priority_and_handler(<br>
- int index,<br>
- int priority,<br>
+ int index,<br>
+ int priority,<br>
ARMV7M_Exception_handler handler<br>
)<br>
{<br>
- _ARMV7M_Set_exception_priority( index, priority );<br>
- _ARMV7M_Set_exception_handler( index, handler );<br>
+ _ARMV7M_Set_exception_priority(index, priority);<br>
+ _ARMV7M_Set_exception_handler(index, handler);<br>
}<br>
<br>
#endif /* ARM_MULTILIB_ARCH_V7M */<br>
diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c<br>
index 05136a47db..0cd7a4f28a 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c<br>
@@ -42,12 +42,12 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-void _ARMV7M_Set_exception_priority( int vector, int priority )<br>
+void _ARMV7M_Set_exception_priority(int vector, int priority)<br>
{<br>
- if ( _ARMV7M_Is_vector_an_irq( vector ) ) {<br>
- _ARMV7M_NVIC_Set_priority( ARMV7M_IRQ_OF_VECTOR( vector ), priority );<br>
+ if ( _ARMV7M_Is_vector_an_irq(vector) ) {<br>
+ _ARMV7M_NVIC_Set_priority(ARMV7M_IRQ_OF_VECTOR(vector), priority);<br>
} else if ( vector >= ARMV7M_VECTOR_MEM_MANAGE ) {<br>
- _ARMV7M_SCB->shpr [vector - 4] = (uint8_t) priority;<br>
+ _ARMV7M_SCB->shpr[vector - 4] = (uint8_t) priority;<br>
}<br>
}<br>
<br>
diff --git a/cpukit/score/cpu/arm/armv7m-initialize.c b/cpukit/score/cpu/arm/armv7m-initialize.c<br>
index 0f47b49af7..1c9a66523b 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-initialize.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-initialize.c<br>
@@ -42,7 +42,7 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-void _CPU_Initialize( void )<br>
+void _CPU_Initialize(void)<br>
{<br>
/*<br>
* The exception handler used to carry out the thead dispatching must have<br>
diff --git a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c<br>
index ea168969ba..dfc125d545 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c<br>
@@ -43,7 +43,7 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void )<br>
+static void __attribute__((naked)) _ARMV7M_Thread_dispatch(void)<br>
{<br>
__asm__ volatile (<br>
"bl _Thread_Dispatch\n"<br>
@@ -53,7 +53,7 @@ static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void )<br>
);<br>
}<br>
<br>
-static void _ARMV7M_Trigger_lazy_floating_point_context_save( void )<br>
+static void _ARMV7M_Trigger_lazy_floating_point_context_save(void)<br>
{<br>
#ifdef ARM_MULTILIB_VFP<br>
__asm__ volatile (<br>
@@ -62,7 +62,7 @@ static void _ARMV7M_Trigger_lazy_floating_point_context_save( void )<br>
#endif<br>
}<br>
<br>
-void _ARMV7M_Pendable_service_call( void )<br>
+void _ARMV7M_Pendable_service_call(void)<br>
{<br>
Per_CPU_Control *cpu_self = _Per_CPU_Get();<br>
<br>
@@ -73,7 +73,7 @@ void _ARMV7M_Pendable_service_call( void )<br>
* this interrupt service may be delayed until interrupts are enable again.<br>
*/<br>
if (<br>
- ( cpu_self->isr_nest_level | cpu_self->thread_dispatch_disable_level ) == 0<br>
+ (cpu_self->isr_nest_level | cpu_self->thread_dispatch_disable_level) == 0<br>
) {<br></blockquote><div><br></div><div>Does this fit on a single line?</div><div><br></div><div>Ignoring the fact it is using bitwise operations on two integer counters. Perhaps</div><div>it should be a <a class="gmail_plusreply" id="plusReplyChip-0">+?</a></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
ARMV7M_Exception_frame *ef;<br>
<br>
@@ -84,29 +84,29 @@ void _ARMV7M_Pendable_service_call( void )<br>
<br>
ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();<br>
--ef;<br>
- _ARMV7M_Set_PSP( (uint32_t) ef );<br>
+ _ARMV7M_Set_PSP((uint32_t) ef);<br>
<br>
/*<br>
* According to "ARMv7-M Architecture Reference Manual" section B1.5.6<br>
* "Exception entry behavior" the return address is half-word aligned.<br>
*/<br>
- ef->register_pc = (void *)<br>
- ((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1));<br>
+ ef->register_pc = (void *) ((uintptr_t) _ARMV7M_Thread_dispatch &<br>
+ ~((uintptr_t) 1));<br>
<br>
ef->register_xpsr = 0x01000000U;<br>
}<br>
}<br>
<br>
-void _ARMV7M_Supervisor_call( void )<br>
+void _ARMV7M_Supervisor_call(void)<br>
{<br>
- Per_CPU_Control *cpu_self = _Per_CPU_Get();<br>
+ Per_CPU_Control *cpu_self = _Per_CPU_Get();<br>
ARMV7M_Exception_frame *ef;<br>
<br>
_ARMV7M_Trigger_lazy_floating_point_context_save();<br>
<br>
ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();<br>
++ef;<br>
- _ARMV7M_Set_PSP( (uint32_t) ef );<br>
+ _ARMV7M_Set_PSP((uint32_t) ef);<br>
<br>
cpu_self->isr_nest_level = 0;<br>
<br>
diff --git a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c<br>
index 1490f6e219..04f7ab1749 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c<br>
@@ -44,7 +44,7 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-void _ARMV7M_Interrupt_service_enter( void )<br>
+void _ARMV7M_Interrupt_service_enter(void)<br>
{<br>
Per_CPU_Control *cpu_self = _Per_CPU_Get();<br>
<br>
@@ -52,7 +52,7 @@ void _ARMV7M_Interrupt_service_enter( void )<br>
++cpu_self->isr_nest_level;<br>
}<br>
<br>
-void _ARMV7M_Interrupt_service_leave( void )<br>
+void _ARMV7M_Interrupt_service_leave(void)<br>
{<br>
Per_CPU_Control *cpu_self = _Per_CPU_Get();<br>
<br>
diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-get.c b/cpukit/score/cpu/arm/armv7m-isr-level-get.c<br>
index cc2b674e13..48b11d923a 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-isr-level-get.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-isr-level-get.c<br>
@@ -41,7 +41,7 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-uint32_t _CPU_ISR_Get_level( void )<br>
+uint32_t _CPU_ISR_Get_level(void)<br>
{<br>
return _ARMV7M_Get_basepri() != 0;<br>
}<br>
diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-set.c b/cpukit/score/cpu/arm/armv7m-isr-level-set.c<br>
index 72c9684025..982c5df687 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-isr-level-set.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-isr-level-set.c<br>
@@ -41,9 +41,9 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-void _CPU_ISR_Set_level( uint32_t level )<br>
+void _CPU_ISR_Set_level(uint32_t level)<br>
{<br>
- _ARMV7M_Set_basepri( 0 );<br>
+ _ARMV7M_Set_basepri(0);<br>
}<br>
<br>
#endif /* ARM_MULTILIB_ARCH_V7M */<br>
diff --git a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c<br>
index c1e9eb70cb..a9e14ba1e6 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c<br>
@@ -51,12 +51,12 @@ void _CPU_ISR_install_vector(<br>
{<br>
uint32_t level;<br>
<br>
- _ISR_Local_disable( level );<br>
+ _ISR_Local_disable(level);<br>
if ( old_handler != NULL ) {<br>
- *old_handler = _ARMV7M_Get_exception_handler( (int) vector );<br>
+ *old_handler = _ARMV7M_Get_exception_handler((int) vector);<br>
}<br>
- _ARMV7M_Set_exception_handler( (int) vector, new_handler );<br>
- _ISR_Local_enable( level );<br>
+ _ARMV7M_Set_exception_handler((int) vector, new_handler);<br>
+ _ISR_Local_enable(level);<br>
}<br>
<br>
#endif /* ARM_MULTILIB_ARCH_V7M */<br>
diff --git a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c<br>
index a9b59dec84..4c6d969f4f 100644<br>
--- a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c<br>
+++ b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c<br>
@@ -42,9 +42,7 @@<br>
<br>
#ifdef ARM_MULTILIB_ARCH_V7M<br>
<br>
-void __attribute__((naked)) _ARMV7M_Start_multitasking(<br>
- Context_Control *heir<br>
-)<br>
+void __attribute__((naked)) _ARMV7M_Start_multitasking(Context_Control *heir)<br>
{<br>
__asm__ volatile (<br>
/* Restore heir context */<br>
diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c<br>
index 65f1ad2014..c7d7527dce 100644<br>
--- a/cpukit/score/cpu/arm/cpu.c<br>
+++ b/cpukit/score/cpu/arm/cpu.c<br>
@@ -61,8 +61,7 @@<br>
#endif<br>
<br>
RTEMS_STATIC_ASSERT(<br>
- offsetof( Context_Control, thread_id )<br>
- == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,<br>
+ offsetof(Context_Control, thread_id) == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,<br>
ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET<br>
);<br>
<br>
@@ -83,23 +82,23 @@ RTEMS_STATIC_ASSERT(<br>
#endif<br>
<br>
RTEMS_STATIC_ASSERT(<br>
- sizeof( CPU_Exception_frame ) == ARM_EXCEPTION_FRAME_SIZE,<br>
+ sizeof(CPU_Exception_frame) == ARM_EXCEPTION_FRAME_SIZE,<br>
ARM_EXCEPTION_FRAME_SIZE<br>
);<br>
<br>
RTEMS_STATIC_ASSERT(<br>
- sizeof( CPU_Exception_frame ) % CPU_STACK_ALIGNMENT == 0,<br>
+ sizeof(CPU_Exception_frame) % CPU_STACK_ALIGNMENT == 0,<br>
CPU_Exception_frame_alignment<br>
);<br>
<br>
RTEMS_STATIC_ASSERT(<br>
- offsetof( CPU_Exception_frame, register_sp )<br>
- == ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET,<br>
+ offsetof(CPU_Exception_frame, register_sp) ==<br>
+ ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET,<br>
ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET<br>
);<br>
<br>
RTEMS_STATIC_ASSERT(<br>
- sizeof( ARM_VFP_context ) == ARM_VFP_CONTEXT_SIZE,<br>
+ sizeof(ARM_VFP_context) == ARM_VFP_CONTEXT_SIZE,<br>
ARM_VFP_CONTEXT_SIZE<br>
);<br>
<br>
@@ -107,12 +106,12 @@ RTEMS_STATIC_ASSERT(<br>
<br>
void _CPU_Context_Initialize(<br>
Context_Control *the_context,<br>
- void *stack_area_begin,<br>
- size_t stack_area_size,<br>
- uint32_t new_level,<br>
- void (*entry_point)( void ),<br>
- bool is_fp,<br>
- void *tls_area<br>
+ void *stack_area_begin,<br>
+ size_t stack_area_size,<br>
+ uint32_t new_level,<br>
+ void (*entry_point)(void),<br>
+ bool is_fp,<br>
+ void *tls_area<br>
)<br>
{<br>
(void) new_level;<br>
@@ -120,14 +119,14 @@ void _CPU_Context_Initialize(<br>
the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;<br>
the_context->register_lr = (uint32_t) entry_point;<br>
the_context->isr_dispatch_disable = 0;<br>
- the_context->thread_id = (uint32_t) tls_area;<br>
+ the_context->thread_id = (uint32_t) tls_area;<br>
<br>
if ( tls_area != NULL ) {<br>
- the_context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area );<br>
+ the_context->thread_id = (uint32_t) _TLS_Initialize_area(tls_area);<br>
}<br>
}<br>
<br>
-void _CPU_ISR_Set_level( uint32_t level )<br>
+void _CPU_ISR_Set_level(uint32_t level)<br>
{<br>
uint32_t arm_switch_reg;<br>
<br>
@@ -144,7 +143,7 @@ void _CPU_ISR_Set_level( uint32_t level )<br>
);<br>
}<br>
<br>
-uint32_t _CPU_ISR_Get_level( void )<br>
+uint32_t _CPU_ISR_Get_level(void)<br>
{<br>
ARM_SWITCH_REGISTERS;<br>
uint32_t level;<br>
@@ -157,7 +156,7 @@ uint32_t _CPU_ISR_Get_level( void )<br>
: [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT<br>
);<br>
<br>
- return ( level & ARM_PSR_I ) != 0;<br>
+ return (level & ARM_PSR_I) != 0;<br>
}<br>
<br>
void _CPU_ISR_install_vector(<br>
@@ -169,34 +168,34 @@ void _CPU_ISR_install_vector(<br>
#pragma GCC diagnostic push<br>
#pragma GCC diagnostic ignored "-Warray-bounds"<br>
/* Redirection table starts at the end of the vector table */<br>
- CPU_ISR_handler volatile *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);<br>
+ CPU_ISR_handler volatile *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);<br>
<br>
- CPU_ISR_handler current_handler = table [vector];<br>
+ CPU_ISR_handler current_handler = table[vector];<br>
<br>
/* The current handler is now the old one */<br>
- if (old_handler != NULL) {<br>
+ if ( old_handler != NULL ) {<br>
*old_handler = current_handler;<br>
}<br>
<br>
/* Write only if necessary to avoid writes to a maybe read-only memory */<br>
- if (current_handler != new_handler) {<br>
- table [vector] = new_handler;<br>
+ if ( current_handler != new_handler ) {<br>
+ table[vector] = new_handler;<br>
}<br>
#pragma GCC diagnostic pop<br>
}<br>
<br>
-void _CPU_Initialize( void )<br>
+void _CPU_Initialize(void)<br>
{<br>
/* Do nothing */<br>
}<br>
<br>
#endif /* ARM_MULTILIB_ARCH_V4 */<br>
<br>
-void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )<br>
+void _CPU_Fatal_halt(uint32_t source, CPU_Uint32ptr error)<br>
{<br>
ISR_Level level;<br>
<br>
- _CPU_ISR_Disable( level );<br>
+ _CPU_ISR_Disable(level);<br>
(void) level;<br>
<br>
__asm__ volatile ("mov r0, %0\n"<br>
-- <br>
2.34.1<br>
<br>
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</blockquote></div></div>