<div dir="ltr">Thanks for the submission. It's a bit hard to review with the patches as attachments rather than having been sent via git send-email but here goes. <br><br>Hopefully someone with more RISC-V knowledge can comment also.<div><br></div><div><br></div><div>0001 - long comment appears to be one line. Please break into multiple lines.<br><div><br></div><div>0001 - riscv/abi.yml is this just adding another set of compiler options? Hard to tell.</div><div><br></div><div>0001 - bspcv32a6.yml - Did this file end up with a copyright?</div><div><br></div><div>0002 - same issue with long comment. Blank line between paragraphs.<br><br>0002 - Is this a common issue which applies to other BSPs?</div><div><br></div><div>0002 - Is there a maximum length of the strings so strnlen() can be used instead of strlen()?</div><div><br></div><div>0002 - Call strlen/strnlen once on stdout_patch and assign to a variable of type size_t</div><div><br></div><div>0003 - This looks like it will break every other architecture since they will not have had restart renamed to start.</div><div>Can you explain what is really not working so we can find a solution that is strictly within the RISC-V? There is</div><div>also a context method which is invoked in the context of the thread once it begins execution. Maybe this will</div><div>work. See threadhandler.c for the call to _Context_Initialization_at_thread_begin.</div><div><br></div><div>I personally am ok for 01 and 02. 03 will require discussion.</div><div><br></div><div>--joel</div><div><br></div></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Aug 1, 2023 at 10:53 AM EYSSARTIER Kevin <<a href="mailto:kevin.eyssartier@thalesgroup.com">kevin.eyssartier@thalesgroup.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="msg-5434843587477748921">
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<p class="MsoNormal"><span lang="EN-US">Hello,<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US"><u></u> <u></u></span></p>
<p class="MsoNormal"><span lang="EN-US">I am working on the port of RTEMS 6 on our RISC-V processor, the CORE-V CVA6 processor
<u></u><u></u></span></p>
<p class="MsoNormal"><a href="https://github.com/ThalesGroup/cva6" target="_blank"><span lang="EN-US" style="color:rgb(5,99,193)">GitHub - ThalesGroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux</span></a><span lang="EN-US"><u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US">The port is working and I think it is a good idea to publish my work on the official repository.<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US">During the port I also found two bugs in the RISC-V generic BSP that I corrected.<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US"><u></u> <u></u></span></p>
<p class="MsoNormal"><span lang="EN-US">I hope it satisfy the quality standards of RTEMS.<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US">Best regards,<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:rgb(0,112,192)">-------</span><span lang="EN-US" style="color:rgb(0,112,192)"><u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:rgb(0,112,192)">Kevin EYSSARTIER, Research Engineer<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:rgb(0,112,192)">Thales Research & Technology France – High Performance Computing Lab<br>
Campus Polytechnique - 1, avenue Augustin Fresnel - 91767 Palaiseau cedex <br>
Phone : +33 (0)1 69 41 55 14 Internal : 341 55 14</span><span style="font-family:Arial,sans-serif"><u></u><u></u></span></p>
<p class="MsoNormal"><u></u> <u></u></p>
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<p align="Center" style="margin:0px"><span style="font-size:10pt;font-family:Calibri;color:rgb(0,128,0)">{THALES GROUP LIMITED DISTRIBUTION}</span></p>
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