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<p class="msipheaderf5bc37b7" style="margin:0cm;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Calibri",sans-serif;color:green">Classified as: {THALES GROUP LIMITED DISTRIBUTION}</span><o:p></o:p></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Thanks for your quick answer Joel.
<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Sorry for not using the “git send-email” command, my company blocks smtp ports on dev machines.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Patch 0001:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:35.4pt"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">I corrected the comment.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:35.4pt"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">The modification in riscv/abi.yml is indeed not needed, it has been removed.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:35.4pt"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">The copyright in bspcv32a6.yml is corrected.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Patch 0002:<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"> I did not check if the stdout-path is correctly handled in other architectures.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"> I used the strlen function because it was the one used previously in fdt_path_offset.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">Patch 0003:<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"> Indeed, my modification will break things.
<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:35.4pt"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">I observe that the interrupts are enabled here : cpukit/score/cpu/riscv/riscv-context-switch.S#L190<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:35.4pt"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">which depends on RTEMS_SMP flag. My bsp does not have multi-processor but I would like multi-tasking
and ISR enabled. <o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:35.4pt"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US">I think something is wrong here, multi-tasking and SMP should be independent.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">De :</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Joel Sherrill <joel@rtems.org>
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<b>Envoyé :</b> mardi 1 août 2023 20:54<br>
<b>À :</b> EYSSARTIER Kevin <kevin.eyssartier@thalesgroup.com><br>
<b>Cc :</b> devel@rtems.org<br>
<b>Objet :</b> Re: CVA6 RISC-V support<o:p></o:p></span></p>
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<p class="MsoNormal">Thanks for the submission. It's a bit hard to review with the patches as attachments rather than having been sent via git send-email but here goes. <br>
<br>
Hopefully someone with more RISC-V knowledge can comment also.<o:p></o:p></p>
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<p class="MsoNormal">0001 - long comment appears to be one line. Please break into multiple lines.<span style="color:#1F497D"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">0001 - riscv/abi.yml is this just adding another set of compiler options?
</span>Hard to tell.<o:p></o:p></p>
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<p class="MsoNormal">0001 - bspcv32a6.yml - Did this file end up with a copyright?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">0002 - same issue with long comment. Blank line between paragraphs.<br>
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0002 - Is this a common issue which applies to other BSPs?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">0002 - Is there a maximum length of the strings so strnlen() can be used instead of strlen()?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">0002 - Call strlen/strnlen once on stdout_patch and assign to a variable of type size_t<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">0003 - This looks like it will break every other architecture since they will not have had restart renamed to start.<o:p></o:p></p>
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<p class="MsoNormal">Can you explain what is really not working so we can find a solution that is strictly within the RISC-V? There is<o:p></o:p></p>
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<p class="MsoNormal">also a context method which is invoked in the context of the thread once it begins execution. Maybe this will<o:p></o:p></p>
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<p class="MsoNormal">work. See threadhandler.c for the call to _Context_Initialization_at_thread_begin.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">I personally am ok for 01 and 02. 03 will require discussion.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">--joel<o:p></o:p></p>
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<p class="MsoNormal">On Tue, Aug 1, 2023 at 10:53 AM EYSSARTIER Kevin <<a href="mailto:kevin.eyssartier@thalesgroup.com">kevin.eyssartier@thalesgroup.com</a>> wrote:<o:p></o:p></p>
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<p style="margin:0cm;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Calibri",sans-serif;color:green">Classified as: {THALES GROUP LIMITED DISTRIBUTION}</span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US">Hello,</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US"> </span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US">I am working on the port of RTEMS 6 on our RISC-V processor, the CORE-V CVA6 processor
</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><a href="https://github.com/ThalesGroup/cva6" target="_blank"><span lang="EN-US" style="color:#0563C1">GitHub - ThalesGroup/cva6: The CORE-V CVA6 is an Application class 6-stage
RISC-V CPU capable of booting Linux</span></a><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US">The port is working and I think it is a good idea to publish my work on the official repository.</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US">During the port I also found two bugs in the RISC-V generic BSP that I corrected.</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US"> </span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US">I hope it satisfy the quality standards of RTEMS.</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US">Best regards,</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US" style="color:#0070C0">-------</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-US" style="color:#0070C0">Kevin EYSSARTIER, Research Engineer</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="color:#0070C0">Thales Research & Technology France – High Performance Computing Lab<br>
Campus Polytechnique - 1, avenue Augustin Fresnel - 91767 Palaiseau cedex <br>
Phone : +33 (0)1 69 41 55 14 Internal : 341 55 14</span><o:p></o:p></p>
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<p class="MsoNormal">_______________________________________________<br>
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