<meta http-equiv="Content-Type" content="text/html; charset=utf-8"><div dir="ltr"><div>Files imported from Xilinx's embeddedsw repository into RTEMS are treated much like imports in libbsd such that modifications should be purely additive and gated by "#ifdef __rtems__" to maintain the ability to update them easily.</div><div><br></div><div>A better way to accomplish the goal of this patch would be to define a BSP option "versal" to trigger the macros you're targeting here since bspopts.h is included via xparameters.h which is included (indirectly) in all the files modified in this patch. This would avoid any modifications to these source files at all.<br></div><div><br></div><div>Kinsey<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Oct 19, 2023 at 12:43 AM <<a href="mailto:aaron.nyholm@unfoldedeffective.com">aaron.nyholm@unfoldedeffective.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: Aaron Nyholm <<a href="mailto:aaron.nyholm@southerninnovation.com" target="_blank">aaron.nyholm@southerninnovation.com</a>><br>
<br>
---<br>
bsps/include/dev/spi/xqspipsu_hw.h | 15 ++++++++-------<br>
bsps/shared/dev/spi/xqspipsu_control.c | 7 ++++---<br>
bsps/shared/dev/spi/xqspipsu_hw.c | 5 +++--<br>
bsps/shared/dev/spi/xqspipsu_options.c | 9 +++++----<br>
4 files changed, 20 insertions(+), 16 deletions(-)<br>
<br>
diff --git a/bsps/include/dev/spi/xqspipsu_hw.h b/bsps/include/dev/spi/xqspipsu_hw.h<br>
index a798f9bb89..61e7b3a240 100644<br>
--- a/bsps/include/dev/spi/xqspipsu_hw.h<br>
+++ b/bsps/include/dev/spi/xqspipsu_hw.h<br>
@@ -43,6 +43,7 @@ extern "C" {<br>
<br>
/***************************** Include Files *********************************/<br>
<br>
+#include <bsp.h><br>
#include "xil_types.h"<br>
#include "xil_assert.h"<br>
#include "xil_io.h"<br>
@@ -57,13 +58,13 @@ extern "C" {<br>
/**<br>
* QSPI Base Address<br>
*/<br>
-#if defined (versal)<br>
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
#define XQSPIPS_BASEADDR 0XF1030000U<br>
#else<br>
#define XQSPIPS_BASEADDR 0XFF0F0000U<br>
#endif<br>
<br>
-#if defined (versal)<br>
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
#define XQSPIPSU_BASEADDR 0XF1030100U<br>
#else<br>
#define XQSPIPSU_BASEADDR 0xFF0F0100U<br>
@@ -141,7 +142,7 @@ extern "C" {<br>
/**<br>
* Register: XQSPIPSU_LQSPI<br>
*/<br>
-#if !defined (versal)<br>
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U<br>
#define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U /**< LQSPI mode enable */<br>
#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U /**< Both memories or one */<br>
@@ -503,7 +504,7 @@ extern "C" {<br>
<br>
#define XQSPIPSU_SEL_SHIFT 0U<br>
#define XQSPIPSU_SEL_WIDTH 1U<br>
-#if !defined (versal)<br>
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
#define XQSPIPSU_SEL_LQSPI_MASK 0X0U<br>
#endif<br>
#define XQSPIPSU_SEL_GQSPI_MASK 0X00000001U<br>
@@ -938,19 +939,19 @@ extern "C" {<br>
* Tapdelay Bypass register<br>
*/<br>
<br>
-#if defined versal<br>
+#if defined LIBBSP_AARCH64_XILINX_VERSAL_BSP_H<br>
#define IOU_TAPDLY_BYPASS_OFFSET 0X0000003CU<br>
#else<br>
#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390U<br>
#endif<br>
<br>
#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U<br>
-#if !defined (versal)<br>
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U<br>
#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U<br>
#endif<br>
<br>
-#if defined versal<br>
+#if defined LIBBSP_AARCH64_XILINX_VERSAL_BSP_H<br>
#define IOU_TAPDLY_RESET_STATE 0x4U<br>
#else<br>
#define IOU_TAPDLY_RESET_STATE 0x7U<br>
diff --git a/bsps/shared/dev/spi/xqspipsu_control.c b/bsps/shared/dev/spi/xqspipsu_control.c<br>
index af2400bf4c..f51e335b60 100644<br>
--- a/bsps/shared/dev/spi/xqspipsu_control.c<br>
+++ b/bsps/shared/dev/spi/xqspipsu_control.c<br>
@@ -30,6 +30,7 @@<br>
<br>
/***************************** Include Files *********************************/<br>
<br>
+#include <bsp.h><br>
#include "xqspipsu_control.h"<br>
<br>
/************************** Constant Definitions *****************************/<br>
@@ -241,7 +242,7 @@ s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler)<br>
<br>
FreqDiv = (InstancePtr->Config.InputClockHz)/Divider;<br>
<br>
-#if defined (versal)<br>
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
if (FreqDiv <= XQSPIPSU_FREQ_37_5MHZ) {<br>
#else<br>
if (FreqDiv <= XQSPIPSU_FREQ_40MHZ) {<br>
@@ -252,7 +253,7 @@ s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler)<br>
Tapdelay |= (TAPDLY_BYPASS_VALVE_100MHZ <<<br>
IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);<br>
LBkModeReg |= (USE_DLY_LPBK << XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT);<br>
-#if defined (versal)<br>
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
delayReg |= (u32)USE_DATA_DLY_ADJ <<<br>
XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT;<br>
#else<br>
@@ -261,7 +262,7 @@ s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler)<br>
((u32)DATA_DLY_ADJ_DLY << XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT);<br>
#endif<br>
} else if (FreqDiv <= XQSPIPSU_FREQ_150MHZ) {<br>
-#if defined (versal)<br>
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
LBkModeReg |= (USE_DLY_LPBK << XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT) |<br>
(LPBK_DLY_ADJ_DLY1 << XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT);<br>
#else<br>
diff --git a/bsps/shared/dev/spi/xqspipsu_hw.c b/bsps/shared/dev/spi/xqspipsu_hw.c<br>
index 6f7708893f..379786ff03 100644<br>
--- a/bsps/shared/dev/spi/xqspipsu_hw.c<br>
+++ b/bsps/shared/dev/spi/xqspipsu_hw.c<br>
@@ -34,6 +34,7 @@<br>
<br>
/***************************** Include Files *********************************/<br>
<br>
+#include <bsp.h><br>
#include "xqspipsu.h"<br>
#include "xqspipsu_control.h"<br>
#if defined (__aarch64__)<br>
@@ -744,11 +745,11 @@ s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass,<br>
if (InstancePtr->IsBusy == (u32)TRUE) {<br>
Status = (s32)XST_DEVICE_BUSY;<br>
} else {<br>
-#if defined (__aarch64__) && (EL1_NONSECURE == 1) && !defined (versal)<br>
+#if defined (__aarch64__) && (EL1_NONSECURE == 1) && !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +<br>
IOU_TAPDLY_BYPASS_OFFSET) | ((u64)(0x4) << 32),<br>
(u64)TapdelayBypass, 0, 0, 0, 0, 0);<br>
-#elif defined (versal)<br>
+#elif defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
XQspiPsu_WriteReg(XQSPIPS_BASEADDR, IOU_TAPDLY_BYPASS_OFFSET,<br>
TapdelayBypass);<br>
#else<br>
diff --git a/bsps/shared/dev/spi/xqspipsu_options.c b/bsps/shared/dev/spi/xqspipsu_options.c<br>
index c889d64abb..d1a286173d 100644<br>
--- a/bsps/shared/dev/spi/xqspipsu_options.c<br>
+++ b/bsps/shared/dev/spi/xqspipsu_options.c<br>
@@ -54,6 +54,7 @@<br>
<br>
/***************************** Include Files *********************************/<br>
<br>
+#include <bsp.h><br>
#include "xqspipsu_control.h"<br>
<br>
/************************** Constant Definitions *****************************/<br>
@@ -80,7 +81,7 @@ static OptionsMap OptionsTable[] = {<br>
{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},<br>
{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},<br>
{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},<br>
-#if !defined (versal)<br>
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
{XQSPIPSU_LQSPI_MODE_OPTION, XQSPIPSU_CFG_WP_HOLD_MASK},<br>
#endif<br>
};<br>
@@ -117,7 +118,7 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)<br>
{<br>
u32 ConfigReg;<br>
u32 Index;<br>
-#if !defined (versal)<br>
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
u32 QspiPsuOptions;<br>
#endif<br>
s32 Status;<br>
@@ -136,7 +137,7 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)<br>
} else {<br>
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,<br>
XQSPIPSU_CFG_OFFSET);<br>
-#if !defined (versal)<br>
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
QspiPsuOptions = OptionsVal & XQSPIPSU_LQSPI_MODE_OPTION;<br>
OptionsVal &= (~XQSPIPSU_LQSPI_MODE_OPTION);<br>
#endif<br>
@@ -164,7 +165,7 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)<br>
if ((OptionsVal & XQSPIPSU_MANUAL_START_OPTION) != (u32)FALSE) {<br>
InstancePtr->IsManualstart = (u8)TRUE;<br>
}<br>
-#if !defined (versal)<br>
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)<br>
if ((QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) != (u32)FALSE) {<br>
if ((Options & XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB) != (u32)FALSE) {<br>
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE);<br>
-- <br>
2.25.1<br>
<br>
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</blockquote></div>