<div dir="ltr"><div>Kinsey,</div><div><br></div><div>I looked this over and built and tested it on actual hardware.  I made the minor changes below, but afterwards it worked as expected.  The change to `bspmercuryxu5.yml` was required to allow my application to find `peripheral_maps/xilinx_zynqmp.h`.  The other changes were not required, but cleaned up some warnings.</div><div><br></div><div>---<br> bsps/arm/xilinx-zynqmp-rpu/include/bsp.h                | 2 +-<br> bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c          | 6 +++---<br> spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml | 4 +++-<br> 3 files changed, 7 insertions(+), 5 deletions(-)<br><br>diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h<br>index db3997677f..e386bd4b26 100644<br>--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h<br>+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h<br>@@ -81,7 +81,7 @@ extern "C" {<br>  *<br>  * Provide in the application to override the defaults in the BSP.<br>  */<br>-BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);<br>+BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void);<br> <br> void zynqmp_debug_console_flush(void);<br> <br>diff --git a/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c b/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c<br>index 7c927058f7..8c591890bf 100644<br>--- a/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c<br>+++ b/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c<br>@@ -123,19 +123,19 @@ static BSP_START_TEXT_SECTION void zynqmp_configure_mpu_sections(void)<br>   Xil_SetMPURegion(addr, size, attrib);<br> <br>   // Add RO region for RO section<br>-  addr = bsp_section_rodata_begin;<br>+  addr = (u32)bsp_section_rodata_begin;<br>   size = bsp_section_rodata_end - bsp_section_rodata_begin;<br>   attrib = NORM_NSHARED_WB_WA | PRIV_RO_USER_RO;<br>   Xil_SetMPURegion(addr, size, attrib);<br> <br>   // Add no cache region for no cache section<br>-  addr = bsp_section_nocache_begin;<br>+  addr = (u32)bsp_section_nocache_begin;<br>   size = bsp_section_nocache_end - bsp_section_nocache_begin;<br>   attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;<br>   Xil_SetMPURegion(addr, size, attrib);<br> <br>   // Add no cache region for no cache no load section<br>-  addr = bsp_section_nocachenoload_begin;<br>+  addr = (u32)bsp_section_nocachenoload_begin;<br>   size = bsp_section_nocachenoload_end - bsp_section_nocachenoload_begin;<br>   attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;<br>   Xil_SetMPURegion(addr, size, attrib);<br>diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml<br>index 342cfdea57..595c1ad507 100644<br>--- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml<br>+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml<br>@@ -16,10 +16,12 @@ install:<br>   source:<br>   - bsps/arm/xilinx-zynqmp-rpu/include/bsp.h<br>   - bsps/include/dev/clock/xttcps_hw.h<br>-  - bsps/include/peripheral_maps/xilinx_zynqmp.h<br> - destination: ${BSP_INCLUDEDIR}/bsp<br>   source:<br>   - bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h<br>+- destination: ${BSP_INCLUDEDIR}/peripheral_maps<br>+  source:<br>+  - bsps/include/peripheral_maps/xilinx_zynqmp.h<br> links:<br> - role: build-dependency<br>   uid: ../grp<br>-- </div><div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Oct 20, 2023 at 7:03 PM Kinsey Moore <<a href="mailto:kinsey.moore@oarcorp.com">kinsey.moore@oarcorp.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div>Philip,</div><div>When you get a chance, could you verify that this refactoring meets your expectations as far as functionality? I'm especially interested in whether the timer interrupts behave as you expect them to on hardware. I don't mind getting the Xilinx support code updates committed, but I'd like some feedback on the BSP itself.<br></div><div><br></div><div>Kinsey<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Oct 12, 2023 at 12:02 PM Kinsey Moore <<a href="mailto:kinsey.moore@oarcorp.com" target="_blank">kinsey.moore@oarcorp.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Changes from v1 (originally submitted by Philip Kirkpatrick):<br>
Refactoring:<br>
* import Xilinx code before modification<br>
* better use the existing Xilinx support code<br>
Other:<br>
* An additional patch to add cache support (also from Philip) has been<br>
  integrated and refactored<br>
<br>
This has been tested on Xilinx's QEMU with Xilinx's device tree<br>
definitions using the following command line options to QEMU:<br>
-no-reboot -nographic -M arm-generic-fdt -serial null -serial mon:stdio \<br>
-device loader,file=<RTEMS exe path>,cpu-num=4 \<br>
-device loader,addr=0xff5e023c,data=0x80088fde,data-len=4 \<br>
-device loader,addr=0xff9a0000,data=0x80000218,data-len=4 \<br>
-hw-dtb <XLNX DTB dir>/LATEST/SINGLE_ARCH/board-zynqmp-zcu102.dtb \<br>
-m 4096 -display none<br>
<br>
hello.exe and ts-validation-cache.exe operated as expected. Ticker<br>
produced output, but the timing and content was incorrect on QEMU.<br>
<br>
<br>
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</blockquote></div>
</blockquote></div>