<meta http-equiv="Content-Type" content="text/html; charset=utf-8"><div dir="ltr"><div>This change looks good.</div><div><br></div><div>Kinsey<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Jan 4, 2024 at 12:54 PM <<a href="mailto:berndmoessner80@gmail.com">berndmoessner80@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: Bernd Moessner <<a href="mailto:berndmoessner80@gmail.com" target="_blank">berndmoessner80@gmail.com</a>><br>
<br>
---<br>
defs/bsps/aarch64/xilinx_zynqmp_base.json | 3 +-<br>
.../src/arm/ARMv8/64bit/xil_cache.h | 75 ----<br>
.../standalone/src/arm/common/xil_exception.h | 408 ------------------<br>
rtemslwip/xilinx/xil_printf.h | 33 --<br>
rtemslwip/xilinx/xil_smc.h | 1 -<br>
5 files changed, 1 insertion(+), 519 deletions(-)<br>
delete mode 100644 embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.h<br>
delete mode 100644 embeddedsw/lib/bsp/standalone/src/arm/common/xil_exception.h<br>
delete mode 100644 rtemslwip/xilinx/xil_printf.h<br>
delete mode 100644 rtemslwip/xilinx/xil_smc.h<br>
<br>
diff --git a/defs/bsps/aarch64/xilinx_zynqmp_base.json b/defs/bsps/aarch64/xilinx_zynqmp_base.json<br>
index 3e47434..600415d 100644<br>
--- a/defs/bsps/aarch64/xilinx_zynqmp_base.json<br>
+++ b/defs/bsps/aarch64/xilinx_zynqmp_base.json<br>
@@ -6,8 +6,7 @@<br>
"embeddedsw/XilinxProcessorIPLib/drivers/emacps/src",<br>
"rtemslwip/xilinx",<br>
"rtemslwip/zynqmp",<br>
- "embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit",<br>
- "embeddedsw/lib/bsp/standalone/src/arm/common"<br>
+ "embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit"<br>
],<br>
"source-files-to-import": [<br>
"rtemslwip/zynqmp/xemacps_g.c",<br>
diff --git a/embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.h b/embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.h<br>
deleted file mode 100644<br>
index b878d05..0000000<br>
--- a/embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.h<br>
+++ /dev/null<br>
@@ -1,75 +0,0 @@<br>
-/******************************************************************************<br>
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.<br>
-* SPDX-License-Identifier: MIT<br>
-******************************************************************************/<br>
-<br>
-/*****************************************************************************/<br>
-/**<br>
-*<br>
-* @file xil_cache.h<br>
-*<br>
-* @addtogroup a53_64_cache_apis Cortex A53 64bit Processor Cache Functions<br>
-*<br>
-* Cache functions provide access to cache related operations such as flush<br>
-* and invalidate for instruction and data caches. It gives option to perform<br>
-* the cache operations on a single cacheline, a range of memory and an entire<br>
-* cache.<br>
-*<br>
-* @{<br>
-*<br>
-* <pre><br>
-* MODIFICATION HISTORY:<br>
-*<br>
-* Ver Who Date Changes<br>
-* ----- ---- -------- -----------------------------------------------<br>
-* 5.00 pkp 05/29/14 First release<br>
-* </pre><br>
-*<br>
-******************************************************************************/<br>
-#ifndef XIL_CACHE_H<br>
-#define XIL_CACHE_H<br>
-<br>
-#include "xil_types.h"<br>
-<br>
-#ifdef __cplusplus<br>
-extern "C" {<br>
-#endif<br>
-<br>
-/**<br>
- *@cond nocomments<br>
- */<br>
-<br>
-/************************** Constant Definitions *****************************/<br>
-#define L1_DATA_PREFETCH_CONTROL_MASK 0xE000<br>
-#define L1_DATA_PREFETCH_CONTROL_SHIFT 13<br>
-<br>
-/**<br>
- *@endcond<br>
- */<br>
-<br>
-/***************** Macros (Inline Functions) Definitions *********************/<br>
-#define Xil_DCacheFlushRange Xil_DCacheInvalidateRange<br>
-<br>
-/************************** Function Prototypes ******************************/<br>
-void Xil_DCacheEnable(void);<br>
-void Xil_DCacheDisable(void);<br>
-void Xil_DCacheInvalidate(void);<br>
-void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len);<br>
-void Xil_DCacheInvalidateLine(INTPTR adr);<br>
-void Xil_DCacheFlush(void);<br>
-void Xil_DCacheFlushLine(INTPTR adr);<br>
-<br>
-void Xil_ICacheEnable(void);<br>
-void Xil_ICacheDisable(void);<br>
-void Xil_ICacheInvalidate(void);<br>
-void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len);<br>
-void Xil_ICacheInvalidateLine(INTPTR adr);<br>
-void Xil_ConfigureL1Prefetch(u8 num);<br>
-#ifdef __cplusplus<br>
-}<br>
-#endif<br>
-<br>
-#endif<br>
-/**<br>
-* @} End of "addtogroup a53_64_cache_apis".<br>
-*/<br>
diff --git a/embeddedsw/lib/bsp/standalone/src/arm/common/xil_exception.h b/embeddedsw/lib/bsp/standalone/src/arm/common/xil_exception.h<br>
deleted file mode 100644<br>
index 144d842..0000000<br>
--- a/embeddedsw/lib/bsp/standalone/src/arm/common/xil_exception.h<br>
+++ /dev/null<br>
@@ -1,408 +0,0 @@<br>
-/******************************************************************************<br>
-* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved.<br>
-* SPDX-License-Identifier: MIT<br>
-******************************************************************************/<br>
-<br>
-/*****************************************************************************/<br>
-/**<br>
-*<br>
-* @file xil_exception.h<br>
-*<br>
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.<br>
-* For exception related functions that can be used across all Xilinx supported<br>
-* processors, please use xil_exception.h.<br>
-*<br>
-* @addtogroup arm_exception_apis ARM Processor Exception Handling<br>
-* @{<br>
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can<br>
-* utilized for enabling/disabling IRQ, registering/removing handler for<br>
-* exceptions or initializing exception vector table with null handler.<br>
-*<br>
-* <pre><br>
-* MODIFICATION HISTORY:<br>
-*<br>
-* Ver Who Date Changes<br>
-* ----- -------- -------- -----------------------------------------------<br>
-* 5.2 pkp 28/05/15 First release<br>
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors<br>
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.<br>
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.<br>
-* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and<br>
-* Xil_ExceptionDisableMask macros to support legacy<br>
-* examples for Cortexa72 EL3 exception level.<br>
-* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and<br>
-* Xil_DisableNestedInterrupts macros for ARMv8.<br>
-* For Cortexa72, these macro's would not be supported<br>
-* at EL3, as Cortexa72 is using GIC-500(GICv3), which<br>
-* triggeres only FIQ at EL3. Fix for CR#1062506<br>
-* 7.6 mus 09/17/21 Updated flag checking to fix warning reported with<br>
-* -Wundef compiler option CR#1110261<br>
-* 7.7 mus 01/31/22 Few of the #defines in xil_exception.h in are treated<br>
-* in different way based on "versal" flag. In existing<br>
-* flow, this flag is defined only in xparameters.h and<br>
-* BSP compiler flags, it is not defined in application<br>
-* compiler flags. So, including xil_exception.h in<br>
-* application source file, without including<br>
-* xparameters.h results in incorrect behavior.<br>
-* Including xparameters.h in xil_exception.h to avoid<br>
-* such issues. It fixes CR#1120498.<br>
-* 7.7 sk 03/02/22 Define XExc_VectorTableEntry structure to fix<br>
-* misra_c_2012_rule_5_6 violation.<br>
-* 7.7 sk 03/02/22 Add XExc_VectorTable as extern to fix misra_c_2012_<br>
-* rule_8_4 violation.<br>
-* </pre><br>
-*<br>
-******************************************************************************/<br>
-<br>
-/**<br>
- *@cond nocomments<br>
- */<br>
-<br>
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */<br>
-#define XIL_EXCEPTION_H /* by using protection macros */<br>
-<br>
-/***************************** Include Files ********************************/<br>
-<br>
-#include "xil_types.h"<br>
-#include "xpseudo_asm.h"<br>
-#include "bspconfig.h"<br>
-#include "xparameters.h"<br>
-<br>
-#ifdef __cplusplus<br>
-extern "C" {<br>
-#endif<br>
-<br>
-/************************** Constant Definitions ****************************/<br>
-<br>
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE<br>
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE<br>
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)<br>
-<br>
-#define XIL_EXCEPTION_ID_FIRST 0U<br>
-#if defined (__aarch64__)<br>
-#define XIL_EXCEPTION_ID_SYNC_INT 1U<br>
-#define XIL_EXCEPTION_ID_IRQ_INT 2U<br>
-#define XIL_EXCEPTION_ID_FIQ_INT 3U<br>
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U<br>
-#define XIL_EXCEPTION_ID_LAST 5U<br>
-#else<br>
-#define XIL_EXCEPTION_ID_RESET 0U<br>
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U<br>
-#define XIL_EXCEPTION_ID_SWI_INT 2U<br>
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U<br>
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U<br>
-#define XIL_EXCEPTION_ID_IRQ_INT 5U<br>
-#define XIL_EXCEPTION_ID_FIQ_INT 6U<br>
-#define XIL_EXCEPTION_ID_LAST 6U<br>
-#endif<br>
-<br>
-/*<br>
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.<br>
- */<br>
-#if defined (versal) && !defined(ARMR5) && EL3<br>
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT<br>
-#else<br>
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT<br>
-#endif<br>
-<br>
-/**************************** Type Definitions ******************************/<br>
-<br>
-/**<br>
- * This typedef is the exception handler function.<br>
- */<br>
-typedef void (*Xil_ExceptionHandler)(void *data);<br>
-typedef void (*Xil_InterruptHandler)(void *data);<br>
-<br>
-typedef struct {<br>
- Xil_ExceptionHandler Handler;<br>
- void *Data;<br>
-} XExc_VectorTableEntry;<br>
-<br>
-extern XExc_VectorTableEntry XExc_VectorTable[];<br>
-<br>
-/**<br>
-*@endcond<br>
-*/<br>
-<br>
-/***************** Macros (Inline Functions) Definitions ********************/<br>
-<br>
-/****************************************************************************/<br>
-/**<br>
-* @brief Enable Exceptions.<br>
-*<br>
-* @param Mask: Value for enabling the exceptions.<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note If bit is 0, exception is enabled.<br>
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)<br>
-*<br>
-******************************************************************************/<br>
-#if defined (versal) && !defined(ARMR5) && EL3<br>
-/*<br>
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports<br>
- * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ<br>
- * ignoring argument passed by user.<br>
- */<br>
-#define Xil_ExceptionEnableMask(Mask) \<br>
- mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))<br>
-#elif defined (__GNUC__) || defined (__ICCARM__)<br>
-#define Xil_ExceptionEnableMask(Mask) \<br>
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))<br>
-#else<br>
-#define Xil_ExceptionEnableMask(Mask) \<br>
- { \<br>
- register u32 Reg __asm("cpsr"); \<br>
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \<br>
- }<br>
-#endif<br>
-/****************************************************************************/<br>
-/**<br>
-* @brief Enable the IRQ exception.<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note None.<br>
-*<br>
-******************************************************************************/<br>
-#if defined (versal) && !defined(ARMR5) && EL3<br>
-#define Xil_ExceptionEnable() \<br>
- Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)<br>
-#else<br>
-#define Xil_ExceptionEnable() \<br>
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)<br>
-#endif<br>
-<br>
-/****************************************************************************/<br>
-/**<br>
-* @brief Disable Exceptions.<br>
-*<br>
-* @param Mask: Value for disabling the exceptions.<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note If bit is 1, exception is disabled.<br>
-* C-Style signature: Xil_ExceptionDisableMask(Mask)<br>
-*<br>
-******************************************************************************/<br>
-#if defined (versal) && !defined(ARMR5) && EL3<br>
-/*<br>
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports<br>
- * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ<br>
- * ignoring argument passed by user.<br>
- */<br>
-#define Xil_ExceptionDisableMask(Mask) \<br>
- mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))<br>
-#elif defined (__GNUC__) || defined (__ICCARM__)<br>
-#define Xil_ExceptionDisableMask(Mask) \<br>
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))<br>
-#else<br>
-#define Xil_ExceptionDisableMask(Mask) \<br>
- { \<br>
- register u32 Reg __asm("cpsr"); \<br>
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \<br>
- }<br>
-#endif<br>
-/****************************************************************************/<br>
-/**<br>
-* Disable the IRQ exception.<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note None.<br>
-*<br>
-******************************************************************************/<br>
-#define Xil_ExceptionDisable() \<br>
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)<br>
-<br>
-#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )<br>
-/****************************************************************************/<br>
-/**<br>
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This<br>
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run<br>
-* at EL3.. However,it is not defined for Versal Cortex-A72 BSP<br>
-* configured to run at EL3. Reason is, Cortex-A72 is coupled<br>
-* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note This macro is supposed to be used from interrupt handlers. In the<br>
-* interrupt handler the interrupts are disabled by default (I bit<br>
-* is set as 1). To allow nesting of interrupts, this macro should be<br>
-* used. It clears the I bit. Once that bit is cleared and provided the<br>
-* preemption of interrupt conditions are met in the GIC, nesting of<br>
-* interrupts will start happening.<br>
-* Caution: This macro must be used with caution. Before calling this<br>
-* macro, the user must ensure that the source of the current IRQ<br>
-* is appropriately cleared. Otherwise, as soon as we clear the I<br>
-* bit, there can be an infinite loop of interrupts with an<br>
-* eventual crash (all the stack space getting consumed).<br>
-******************************************************************************/<br>
-#define Xil_EnableNestedInterrupts() \<br>
- __asm__ __volatile__ ("mrs X1, ELR_EL3"); \<br>
- __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \<br>
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \<br>
- __asm__ __volatile__ ("mrs X1, DAIF"); \<br>
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \<br>
- __asm__ __volatile__ ("msr DAIF, X1"); \<br>
-<br>
-/****************************************************************************/<br>
-/**<br>
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This<br>
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run<br>
-* at EL3.<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note This macro is meant to be called in the interrupt service routines.<br>
-* This macro cannot be used independently. It can only be used when<br>
-* nesting of interrupts have been enabled by using the macro<br>
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first<br>
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate<br>
-* point. The user then must call this macro before exiting the interrupt<br>
-* service routine. This macro puts the ARM back in IRQ mode and<br>
-* hence sets back the I bit.<br>
-******************************************************************************/<br>
-#define Xil_DisableNestedInterrupts() \<br>
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \<br>
- __asm__ __volatile__ ("msr ELR_EL3, X1"); \<br>
- __asm__ __volatile__ ("msr SPSR_EL3, X2"); \<br>
- __asm__ __volatile__ ("mrs X1, DAIF"); \<br>
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \<br>
- __asm__ __volatile__ ("msr DAIF, X1"); \<br>
-<br>
-#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))<br>
-/****************************************************************************/<br>
-/**<br>
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This<br>
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit<br>
-* BSP configured to run at EL1 NON SECURE<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note This macro is supposed to be used from interrupt handlers. In the<br>
-* interrupt handler the interrupts are disabled by default (I bit<br>
-* is set as 1). To allow nesting of interrupts, this macro should be<br>
-* used. It clears the I bit. Once that bit is cleared and provided the<br>
-* preemption of interrupt conditions are met in the GIC, nesting of<br>
-* interrupts will start happening.<br>
-* Caution: This macro must be used with caution. Before calling this<br>
-* macro, the user must ensure that the source of the current IRQ<br>
-* is appropriately cleared. Otherwise, as soon as we clear the I<br>
-* bit, there can be an infinite loop of interrupts with an<br>
-* eventual crash (all the stack space getting consumed).<br>
-******************************************************************************/<br>
-#define Xil_EnableNestedInterrupts() \<br>
- __asm__ __volatile__ ("mrs X1, ELR_EL1"); \<br>
- __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \<br>
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \<br>
- __asm__ __volatile__ ("mrs X1, DAIF"); \<br>
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \<br>
- __asm__ __volatile__ ("msr DAIF, X1"); \<br>
-<br>
-/****************************************************************************/<br>
-/**<br>
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This<br>
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit<br>
-* BSP configured to run at EL1 NON SECURE<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note This macro is meant to be called in the interrupt service routines.<br>
-* This macro cannot be used independently. It can only be used when<br>
-* nesting of interrupts have been enabled by using the macro<br>
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first<br>
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate<br>
-* point. The user then must call this macro before exiting the interrupt<br>
-* service routine. This macro puts the ARM back in IRQ mode and<br>
-* hence sets back the I bit.<br>
-******************************************************************************/<br>
-#define Xil_DisableNestedInterrupts() \<br>
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \<br>
- __asm__ __volatile__ ("msr ELR_EL1, X1"); \<br>
- __asm__ __volatile__ ("msr SPSR_EL1, X2"); \<br>
- __asm__ __volatile__ ("mrs X1, DAIF"); \<br>
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \<br>
- __asm__ __volatile__ ("msr DAIF, X1"); \<br>
-<br>
-#elif (!defined (__aarch64__) && !defined (ARMA53_32))<br>
-/****************************************************************************/<br>
-/**<br>
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This<br>
-* API is defined for cortex-a9 and cortex-r5.<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note This macro is supposed to be used from interrupt handlers. In the<br>
-* interrupt handler the interrupts are disabled by default (I and F<br>
-* are 1). To allow nesting of interrupts, this macro should be<br>
-* used. It clears the I and F bits by changing the ARM mode to<br>
-* system mode. Once these bits are cleared and provided the<br>
-* preemption of interrupt conditions are met in the GIC, nesting of<br>
-* interrupts will start happening.<br>
-* Caution: This macro must be used with caution. Before calling this<br>
-* macro, the user must ensure that the source of the current IRQ<br>
-* is appropriately cleared. Otherwise, as soon as we clear the I and<br>
-* F bits, there can be an infinite loop of interrupts with an<br>
-* eventual crash (all the stack space getting consumed).<br>
-******************************************************************************/<br>
-#define Xil_EnableNestedInterrupts() \<br>
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \<br>
- __asm__ __volatile__ ("mrs lr, spsr"); \<br>
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \<br>
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \<br>
- __asm__ __volatile__ ("stmfd sp!, {lr}");<br>
-/****************************************************************************/<br>
-/**<br>
-* @brief Disable the nested interrupts by setting the I and F bits. This API<br>
-* is defined for cortex-a9 and cortex-r5.<br>
-*<br>
-* @return None.<br>
-*<br>
-* @note This macro is meant to be called in the interrupt service routines.<br>
-* This macro cannot be used independently. It can only be used when<br>
-* nesting of interrupts have been enabled by using the macro<br>
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first<br>
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate<br>
-* point. The user then must call this macro before exiting the interrupt<br>
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and<br>
-* hence sets back the I and F bits.<br>
-******************************************************************************/<br>
-#define Xil_DisableNestedInterrupts() \<br>
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \<br>
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \<br>
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \<br>
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \<br>
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \<br>
-<br>
-#endif<br>
-/************************** Variable Definitions ****************************/<br>
-<br>
-/************************** Function Prototypes *****************************/<br>
-<br>
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,<br>
- Xil_ExceptionHandler Handler,<br>
- void *Data);<br>
-<br>
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);<br>
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,<br>
- Xil_ExceptionHandler *Handler, void **Data);<br>
-<br>
-extern void Xil_ExceptionInit(void);<br>
-#if defined (__aarch64__)<br>
-void Xil_SyncAbortHandler(void *CallBackRef);<br>
-void Xil_SErrorAbortHandler(void *CallBackRef);<br>
-#else<br>
-extern void Xil_DataAbortHandler(void *CallBackRef);<br>
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);<br>
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);<br>
-#endif<br>
-<br>
-#ifdef __cplusplus<br>
-}<br>
-#endif /* __cplusplus */<br>
-<br>
-#endif /* XIL_EXCEPTION_H */<br>
-/**<br>
-* @} End of "addtogroup arm_exception_apis".<br>
-*/<br>
diff --git a/rtemslwip/xilinx/xil_printf.h b/rtemslwip/xilinx/xil_printf.h<br>
deleted file mode 100644<br>
index 3da55bd..0000000<br>
--- a/rtemslwip/xilinx/xil_printf.h<br>
+++ /dev/null<br>
@@ -1,33 +0,0 @@<br>
-/*<br>
- * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)<br>
- * Written by Kinsey Moore <<a href="mailto:kinsey.moore@oarcorp.com" target="_blank">kinsey.moore@oarcorp.com</a>><br>
- *<br>
- * Redistribution and use in source and binary forms, with or without<br>
- * modification, are permitted provided that the following conditions<br>
- * are met:<br>
- * 1. Redistributions of source code must retain the above copyright<br>
- * notice, this list of conditions and the following disclaimer.<br>
- * 2. Redistributions in binary form must reproduce the above copyright<br>
- * notice, this list of conditions and the following disclaimer in the<br>
- * documentation and/or other materials provided with the distribution.<br>
- *<br>
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
- * POSSIBILITY OF SUCH DAMAGE.<br>
- */<br>
-<br>
-#ifndef XIL_PRINTF_H<br>
-#define XIL_PRINTF_H<br>
-<br>
-#define xil_printf( args ... ) printf( args )<br>
-#define print( args ... ) printf( args )<br>
-<br>
-#endif<br>
diff --git a/rtemslwip/xilinx/xil_smc.h b/rtemslwip/xilinx/xil_smc.h<br>
deleted file mode 100644<br>
index d35e631..0000000<br>
--- a/rtemslwip/xilinx/xil_smc.h<br>
+++ /dev/null<br>
@@ -1 +0,0 @@<br>
-/* This file is a stub and intentionally left blank */<br>
-- <br>
2.34.1<br>
<br>
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</blockquote></div>