<meta http-equiv="Content-Type" content="text/html; charset=utf-8"><div dir="ltr"><div dir="ltr"><div>A few comments inline below. For the most part, this looks good.</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sat, Jan 6, 2024 at 9:15 AM <<a href="mailto:berndmoessner80@gmail.com">berndmoessner80@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: Bernd Moessner <<a href="mailto:berndmoessner80@gmail.com" target="_blank">berndmoessner80@gmail.com</a>><br>
<br>
This patch adds support for the Xilinx ZYNQ 7000 series. Please note that this patch also affects ZYNQ Ultrascale+ as I`ve moved some functions from zynqmp/xil_shims.c to xilinx/freertos.c and xilinx/xscugic.c to share them between both families.<br>
---<br>
defs/bsps/aarch64/xilinx_zynqmp_base.json | 2 +<br>
defs/bsps/arm/xilinx_zynq_base.json | 28 ++++++<br>
defs/bsps/arm/xilinx_zynq_picozed.json | 13 +++<br>
.../ports/xilinx/include/netif/xadapter.h | 4 +<br>
.../contrib/ports/xilinx/netif/xemacpsif.c | 18 ++++<br>
.../ports/xilinx/netif/xemacpsif_dma.c | 14 +++<br>
.../bsp/standalone/src/arm/cortexa9/xil_mmu.h | 92 +++++++++++++++++++<br>
rtemslwip/xilinx/freertos.c | 64 +++++++++++++<br>
rtemslwip/xilinx/xpseudo_asm.h | 5 +<br>
rtemslwip/xilinx/xscugic_hw.c | 40 ++++++++<br>
rtemslwip/zynq/common_lwipopts.h | 3 +<br>
rtemslwip/zynq/xil_shims.c | 42 +++++++++<br>
rtemslwip/zynq/xlwipconfig.h | 38 ++++++++<br>
rtemslwip/zynq_picozed/lwipbspopts.h | 1 +<br>
rtemslwip/zynq_picozed/netstart.c | 66 +++++++++++++<br>
rtemslwip/zynq_picozed/xemacps_g.c | 35 +++++++<br>
rtemslwip/zynq_picozed/xparameters_ps.h | 72 +++++++++++++++<br>
rtemslwip/zynq_picozed/xtopology_g.c | 40 ++++++++<br>
rtemslwip/zynqmp/xil_shims.c | 45 ---------<br>
19 files changed, 577 insertions(+), 45 deletions(-)<br>
create mode 100644 defs/bsps/arm/xilinx_zynq_base.json<br>
create mode 100644 defs/bsps/arm/xilinx_zynq_picozed.json<br>
create mode 100644 embeddedsw/lib/bsp/standalone/src/arm/cortexa9/xil_mmu.h<br>
create mode 100644 rtemslwip/xilinx/freertos.c<br>
create mode 100644 rtemslwip/xilinx/xscugic_hw.c<br>
create mode 100644 rtemslwip/zynq/common_lwipopts.h<br>
create mode 100644 rtemslwip/zynq/xil_shims.c<br>
create mode 100644 rtemslwip/zynq/xlwipconfig.h<br>
create mode 100644 rtemslwip/zynq_picozed/lwipbspopts.h<br>
create mode 100644 rtemslwip/zynq_picozed/netstart.c<br>
create mode 100644 rtemslwip/zynq_picozed/xemacps_g.c<br>
create mode 100644 rtemslwip/zynq_picozed/xparameters_ps.h<br>
create mode 100644 rtemslwip/zynq_picozed/xtopology_g.c<br>
<br>
diff --git a/defs/bsps/aarch64/xilinx_zynqmp_base.json b/defs/bsps/aarch64/xilinx_zynqmp_base.json<br>
index 600415d..f8f4c14 100644<br>
--- a/defs/bsps/aarch64/xilinx_zynqmp_base.json<br>
+++ b/defs/bsps/aarch64/xilinx_zynqmp_base.json<br>
@@ -9,6 +9,8 @@<br>
"embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit"<br>
],<br>
"source-files-to-import": [<br>
+ "rtemslwip/xilinx/freertos.c",<br>
+ "rtemslwip/xilinx/xscugic_hw.c",<br>
"rtemslwip/zynqmp/xemacps_g.c",<br>
"rtemslwip/zynqmp/xil_shims.c",<br>
"rtemslwip/zynqmp/xtopology_g.c",<br>
diff --git a/defs/bsps/arm/xilinx_zynq_base.json b/defs/bsps/arm/xilinx_zynq_base.json<br>
new file mode 100644<br>
index 0000000..aad0640<br>
--- /dev/null<br>
+++ b/defs/bsps/arm/xilinx_zynq_base.json<br>
@@ -0,0 +1,28 @@<br>
+{<br>
+ "header-paths-to-import": [<br>
+ "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include",<br>
+ "embeddedsw/lib/bsp/standalone/src/common",<br>
+ "embeddedsw/XilinxProcessorIPLib/drivers/scugic/src",<br>
+ "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src",<br>
+ "rtemslwip/xilinx",<br>
+ "rtemslwip/zynq",<br>
+ "embeddedsw/lib/bsp/standalone/src/arm/cortexa9",<br>
+ "embeddedsw/lib/bsp/standalone/src/arm/common"<br>
+ ],<br>
+ "source-files-to-import": [<br>
+ "rtemslwip/zynq/xil_shims.c",<br>
+ "rtemslwip/xilinx/freertos.c",<br>
+ "rtemslwip/xilinx/xscugic_hw.c",<br>
+ "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xadapter.c",<br>
+ "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xpqueue.c",<br>
+ "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c",<br>
+ "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c",<br>
+ "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_hw.c",<br>
+ "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c",<br>
+ "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src/xemacps_bdring.c",<br>
+ "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c",<br>
+ "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src/xemacps_control.c",<br>
+ "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c",<br>
+ "embeddedsw/lib/bsp/standalone/src/common/xil_assert.c"<br>
+ ]<br>
+}<br>
diff --git a/defs/bsps/arm/xilinx_zynq_picozed.json b/defs/bsps/arm/xilinx_zynq_picozed.json<br>
new file mode 100644<br>
index 0000000..feb4188<br>
--- /dev/null<br>
+++ b/defs/bsps/arm/xilinx_zynq_picozed.json<br>
@@ -0,0 +1,13 @@<br>
+{<br>
+ "includes": [<br>
+ "xilinx_zynq_base"<br>
+ ],<br>
+ "header-paths-to-import": [<br>
+ "rtemslwip/zynq_picozed"<br>
+ ],<br>
+ "source-files-to-import": [<br>
+ "rtemslwip/zynq_picozed/xemacps_g.c",<br>
+ "rtemslwip/zynq_picozed/xtopology_g.c",<br>
+ "rtemslwip/zynq_picozed/netstart.c"<br>
+ ]<br>
+}<br>
diff --git a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include/netif/xadapter.h b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include/netif/xadapter.h<br>
index 4d32b7f..aa491b7 100644<br>
--- a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include/netif/xadapter.h<br>
+++ b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include/netif/xadapter.h<br>
@@ -53,7 +53,11 @@ struct xemac_s {<br>
#if !NO_SYS<br>
sys_sem_t sem_rx_data_available;<br>
#if defined(__arm__) && !defined(ARMR5)<br>
+#ifndef __rtems__<br>
TimerHandle_t xTimer;<br>
+#else /* __rtems__ */<br>
+ rtems_id xTimer;<br>
+#endif<br>
#endif<br>
#endif<br>
};<br>
diff --git a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c<br>
index 5328e86..3e36771 100644<br>
--- a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c<br>
+++ b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c<br>
@@ -329,11 +329,19 @@ s32_t xemacpsif_input(struct netif *netif)<br>
<br>
#if !NO_SYS<br>
#if defined(__arm__) && !defined(ARMR5)<br>
+#ifndef __rtems__<br>
void vTimerCallback( TimerHandle_t pxTimer )<br>
{<br>
/* Do something if the pxTimer parameter is NULL */<br>
configASSERT(pxTimer);<br>
<br>
+#else /* __rtems__ */<br>
+static rtems_timer_service_routine vTimerCallback(<br>
+ rtems_id timer,<br>
+ void *arg<br>
+)<br>
+{<br>
+#endif<br></blockquote><div><br></div><div>I'm surprised you're not getting warnings for unused arguments for timer and arg.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
lExpireCounter++;<br>
/* If the timer has expired 100 times then reset RX */<br>
if(lExpireCounter >= RESETRXTIMEOUT) {<br>
@@ -434,6 +442,7 @@ static err_t low_level_init(struct netif *netif)<br>
XEMACPS_DMACR_OFFSET, dmacrreg);<br>
#if !NO_SYS<br>
#if defined(__arm__) && !defined(ARMR5)<br>
+#ifndef __rtems__<br>
/* Freertos tick is 10ms by default; set period to the same */<br>
xemac->xTimer = xTimerCreate("Timer", 10, pdTRUE, ( void * ) 1, vTimerCallback);<br>
if (xemac->xTimer == NULL) {<br>
@@ -443,6 +452,15 @@ static err_t low_level_init(struct netif *netif)<br>
xil_printf("In %s:Timer start failed....\r\n", __func__);<br>
}<br>
}<br>
+#else /* __rtems__ */<br>
+ rtems_status_code ret = rtems_timer_create( rtems_build_name( 'L', 'W', 'M', 'R' ), &xemac->xTimer);<br>
+ if(RTEMS_SUCCESSFUL == ret){<br>
+ ret = rtems_timer_fire_after(xemac->xTimer, rtems_clock_get_ticks_per_second()/100, vTimerCallback, NULL);<br>
+ }<br>
+ if(RTEMS_SUCCESSFUL != ret){<br>
+ xil_printf("In %s:Timer setup failed....\r\n", __func__);<br>
+ }<br></blockquote><div><br></div><div>Indentation doesn't match surrounding code.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+#endif<br>
#endif<br>
#endif<br>
setup_isr(xemac);<br>
diff --git a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c<br>
index 1d2439a..c222835 100644<br>
--- a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c<br>
+++ b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c<br>
@@ -114,7 +114,15 @@ volatile u32_t notifyinfo[4*XLWIP_CONFIG_N_TX_DESC];<br>
#if defined __aarch64__<br>
u8_t bd_space[0x200000] __attribute__ ((aligned (0x200000)));<br>
#else<br>
+#ifndef __rtems__<br>
u8_t bd_space[0x100000] __attribute__ ((aligned (0x100000)));<br>
+#else /* __rtems__ */<br>
+#if defined(__arm__) && !defined(ARMR5)<br>
+u8_t bd_space[0x100000] __attribute__ ((section(".bsp_nocache"), aligned (0x100000)));<br>
+#else<br>
+u8_t bd_space[0x100000] __attribute__ ((aligned (0x100000)));<br>
+#endif<br>
+#endif<br></blockquote><div><br></div><div>Is there a reason you chose to change this interface instead of defining Xil_SetTlbAttributes to use arm_cp15_start_set_translation_table_entries(bsp_translation_table_base, ...)? The struct passed as the second parameter only needs to exist for the duration of the function call.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
#endif<br>
static volatile u32_t bd_space_index = 0;<br>
static volatile u32_t bd_space_attr_set = 0;<br>
@@ -676,7 +684,13 @@ XStatus init_dma(struct xemac_s *xemac)<br>
#if defined __aarch64__<br>
Xil_SetTlbAttributes((u64)bd_space, NORM_NONCACHE | INNER_SHAREABLE);<br>
#else<br>
+#ifndef __rtems__<br>
Xil_SetTlbAttributes((s32_t)bd_space, DEVICE_MEMORY); // addr, attr<br>
+#else /* __rtems__ */<br>
+#if !defined(__arm__)<br>
+ Xil_SetTlbAttributes((s32_t)bd_space, DEVICE_MEMORY); // addr, attr<br>
+#endif<br>
+#endif<br>
#endif<br>
#endif<br>
bd_space_attr_set = 1;<br></blockquote><div><br></div><div>With the current configuration not using any of the identifiers defined here, this file import (cortexa9/xil_mmu.h) would be better served by a blank stub file. You'll need it if you define Xil_SetTlbAttributes, instead.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
diff --git a/embeddedsw/lib/bsp/standalone/src/arm/cortexa9/xil_mmu.h b/embeddedsw/lib/bsp/standalone/src/arm/cortexa9/xil_mmu.h<br>
new file mode 100644<br>
index 0000000..d21e13a<br>
--- /dev/null<br>
+++ b/embeddedsw/lib/bsp/standalone/src/arm/cortexa9/xil_mmu.h<br>
@@ -0,0 +1,92 @@<br>
+/******************************************************************************<br>
+* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.<br>
+* SPDX-License-Identifier: MIT<br>
+******************************************************************************/<br>
+<br>
+/*****************************************************************************/<br>
+/**<br>
+* @file xil_mmu.h<br>
+*<br>
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions<br>
+*<br>
+* MMU functions equip users to enable MMU, disable MMU and modify default<br>
+* memory attributes of MMU table as per the need.<br>
+*<br>
+* @{<br>
+*<br>
+* <pre><br>
+* MODIFICATION HISTORY:<br>
+*<br>
+* Ver Who Date Changes<br>
+* ----- ---- -------- ---------------------------------------------------<br>
+* 1.00a sdm 01/12/12 Initial version<br>
+* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for<br>
+* u32 which resolves issue of CR#805869<br>
+* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API<br>
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.<br>
+* </pre><br>
+*<br>
+*<br>
+******************************************************************************/<br>
+<br>
+/**<br>
+*@cond nocomments<br>
+*/<br>
+<br>
+#ifndef XIL_MMU_H<br>
+#define XIL_MMU_H<br>
+<br>
+#ifdef __cplusplus<br>
+extern "C" {<br>
+#endif /* __cplusplus */<br>
+<br>
+/***************************** Include Files *********************************/<br>
+<br>
+#include "xil_types.h"<br>
+<br>
+/***************** Macros (Inline Functions) Definitions *********************/<br>
+<br>
+/**************************** Type Definitions *******************************/<br>
+<br>
+/************************** Constant Definitions *****************************/<br>
+<br>
+/* Memory type */<br>
+#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */<br>
+#define STRONG_ORDERED 0xC02 /* Strongly ordered */<br>
+#define DEVICE_MEMORY 0xC06 /* Device memory */<br>
+#define RESERVED 0x0 /* reserved memory */<br>
+<br>
+/* Normal write-through cacheable shareable */<br>
+#define NORM_WT_CACHE 0x16DEA<br>
+<br>
+/* Normal write back cacheable shareable */<br>
+#define NORM_WB_CACHE 0x15DE6<br>
+<br>
+/* shareability attribute */<br>
+#define SHAREABLE (0x1 << 16)<br>
+#define NON_SHAREABLE (~(0x1 << 16))<br>
+<br>
+/* Execution type */<br>
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))<br>
+<br>
+/**<br>
+*@endcond<br>
+*/<br>
+<br>
+/************************** Variable Definitions *****************************/<br>
+<br>
+/************************** Function Prototypes ******************************/<br>
+<br>
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);<br>
+void Xil_EnableMMU(void);<br>
+void Xil_DisableMMU(void);<br>
+void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);<br>
+<br>
+#ifdef __cplusplus<br>
+}<br>
+#endif /* __cplusplus */<br>
+<br>
+#endif /* XIL_MMU_H */<br>
+/**<br>
+* @} End of "addtogroup a9_mmu_apis".<br>
+*/<br>
diff --git a/rtemslwip/xilinx/freertos.c b/rtemslwip/xilinx/freertos.c<br>
new file mode 100644<br>
index 0000000..90d1f83<br>
--- /dev/null<br>
+++ b/rtemslwip/xilinx/freertos.c<br>
@@ -0,0 +1,64 @@<br>
+/*<br>
+ * Copyright (C) 2024 On-Line Applications Research Corporation (OAR)<br>
+ * Written by Kinsey Moore <<a href="mailto:kinsey.moore@oarcorp.com" target="_blank">kinsey.moore@oarcorp.com</a>><br>
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions<br>
+ * are met:<br>
+ * 1. Redistributions of source code must retain the above copyright<br>
+ * notice, this list of conditions and the following disclaimer.<br>
+ * 2. Redistributions in binary form must reproduce the above copyright<br>
+ * notice, this list of conditions and the following disclaimer in the<br>
+ * documentation and/or other materials provided with the distribution.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+ * POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+#include <rtems/rtems/intr.h><br>
+#include <rtems/score/threadimpl.h><br>
+#include <stdio.h><br>
+#include <string.h><br>
+#include "xil_types.h"<br>
+#include "FreeRTOS.h"<br>
+<br>
+<br>
+/*<br>
+ * XInterruptHandler function pointer signature just happens to exactly match<br>
+ * rtems_interrupt_handler<br>
+ */<br>
+BaseType_t xPortInstallInterruptHandler(<br>
+ uint8_t ucInterruptID,<br>
+ XInterruptHandler pxHandler,<br>
+ void *pvCallBackRef<br>
+)<br>
+{<br>
+ char name[10];<br>
+<br>
+ /* Is this running in the context of any interrupt server tasks? */<br>
+ _Thread_Get_name( _Thread_Get_executing(), name, sizeof( name ) );<br>
+ if (strcmp(name, "IRQS") == 0) {<br>
+ /* Can't run this from within an IRQ Server thread context */<br>
+ return RTEMS_ILLEGAL_ON_SELF;<br>
+ }<br>
+<br>
+ rtems_status_code sc = rtems_interrupt_server_handler_install(<br>
+ RTEMS_INTERRUPT_SERVER_DEFAULT,<br>
+ ucInterruptID,<br>
+ "CGEM Handler",<br>
+ RTEMS_INTERRUPT_UNIQUE,<br>
+ pxHandler,<br>
+ pvCallBackRef<br>
+ );<br>
+<br>
+ return sc;<br>
+}<br>
diff --git a/rtemslwip/xilinx/xpseudo_asm.h b/rtemslwip/xilinx/xpseudo_asm.h<br>
index cb51433..0168ce3 100644<br>
--- a/rtemslwip/xilinx/xpseudo_asm.h<br>
+++ b/rtemslwip/xilinx/xpseudo_asm.h<br>
@@ -28,6 +28,11 @@<br>
#define XPSEUDO_ASM_H<br>
<br>
#include <rtems/score/cpu.h><br>
+#if defined(__arm__) && !defined(ARMR5)<br>
+#define dsb() _ARM_Data_synchronization_barrier()<br>
+#define isb() _ARM_Instruction_synchronization_barrier()<br>
+#else<br>
#define dsb() _AARCH64_Data_synchronization_barrier()<br>
+#endif<br>
<br>
#endif<br>
diff --git a/rtemslwip/xilinx/xscugic_hw.c b/rtemslwip/xilinx/xscugic_hw.c<br>
new file mode 100644<br>
index 0000000..9ba14a4<br>
--- /dev/null<br>
+++ b/rtemslwip/xilinx/xscugic_hw.c<br>
@@ -0,0 +1,40 @@<br>
+/*<br>
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)<br>
+ * Written by Kinsey Moore <<a href="mailto:kinsey.moore@oarcorp.com" target="_blank">kinsey.moore@oarcorp.com</a>><br>
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions<br>
+ * are met:<br>
+ * 1. Redistributions of source code must retain the above copyright<br>
+ * notice, this list of conditions and the following disclaimer.<br>
+ * 2. Redistributions in binary form must reproduce the above copyright<br>
+ * notice, this list of conditions and the following disclaimer in the<br>
+ * documentation and/or other materials provided with the distribution.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+ * POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+ #include <rtems/rtems/intr.h><br>
+#include "xil_types.h"<br>
+<br>
+/* Enable the interrupt */<br>
+void XScuGic_EnableIntr ( u32 DistBaseAddress, u32 Int_Id )<br>
+{<br>
+ rtems_interrupt_vector_enable( Int_Id );<br>
+}<br>
+<br>
+/* Disable the interrupt */<br>
+void XScuGic_DisableIntr ( u32 DistBaseAddress, u32 Int_Id )<br>
+{<br>
+ rtems_interrupt_vector_disable( Int_Id );<br>
+}<br>
diff --git a/rtemslwip/zynq/common_lwipopts.h b/rtemslwip/zynq/common_lwipopts.h<br>
new file mode 100644<br>
index 0000000..8b7d870<br>
--- /dev/null<br>
+++ b/rtemslwip/zynq/common_lwipopts.h<br>
@@ -0,0 +1,3 @@<br>
+#include <xparameters_ps.h><br>
+#include <xlwipopts.h><br>
+#define MEM_ALIGNMENT 64<br>
diff --git a/rtemslwip/zynq/xil_shims.c b/rtemslwip/zynq/xil_shims.c<br>
new file mode 100644<br>
index 0000000..50afcf8<br>
--- /dev/null<br>
+++ b/rtemslwip/zynq/xil_shims.c<br>
@@ -0,0 +1,42 @@<br>
+/*<br>
+ * SPDX-License-Identifier: BSD-2-Clause<br>
+ *<br>
+ * Copyright (C) 2024 Bernd Moessner<br>
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions<br>
+ * are met:<br>
+ * 1. Redistributions of source code must retain the above copyright<br>
+ * notice, this list of conditions and the following disclaimer.<br>
+ * 2. Redistributions in binary form must reproduce the above copyright<br>
+ * notice, this list of conditions and the following disclaimer in the<br>
+ * documentation and/or other materials provided with the distribution.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+ * POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+#include "xil_mmu.h"<br>
+#include <rtems/rtems/cache.h><br>
+#include <stdio.h><br>
+#include <string.h><br>
+<br>
+<br>
+void Xil_DCacheInvalidateRange( INTPTR adr, INTPTR len )<br>
+{<br>
+ rtems_cache_flush_multiple_data_lines( (const void *) adr, len );<br>
+}<br>
+<br>
+void Xil_DCacheFlushRange( INTPTR adr, INTPTR len )<br>
+{<br>
+ Xil_DCacheInvalidateRange(adr, len );<br>
+}<br>
diff --git a/rtemslwip/zynq/xlwipconfig.h b/rtemslwip/zynq/xlwipconfig.h<br>
new file mode 100644<br>
index 0000000..8144153<br>
--- /dev/null<br>
+++ b/rtemslwip/zynq/xlwipconfig.h<br>
@@ -0,0 +1,38 @@<br>
+/*<br>
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)<br>
+ * Written by Kinsey Moore <<a href="mailto:kinsey.moore@oarcorp.com" target="_blank">kinsey.moore@oarcorp.com</a>><br></blockquote><div><br></div><div>You should replace the copyright information here.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions<br>
+ * are met:<br>
+ * 1. Redistributions of source code must retain the above copyright<br>
+ * notice, this list of conditions and the following disclaimer.<br>
+ * 2. Redistributions in binary form must reproduce the above copyright<br>
+ * notice, this list of conditions and the following disclaimer in the<br>
+ * documentation and/or other materials provided with the distribution.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+ * POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+#ifndef __XLWIPCONFIG_H_<br>
+#define __XLWIPCONFIG_H_<br>
+<br>
+#define XLWIP_CONFIG_INCLUDE_GEM 1<br>
+#define XLWIP_CONFIG_EMAC_NUMBER 0<br>
+#define XLWIP_CONFIG_N_TX_DESC 64<br>
+#define XLWIP_CONFIG_N_RX_DESC 64<br>
+<br>
+#define XLWIP_CONFIG_N_TX_COALESCE 1<br>
+#define XLWIP_CONFIG_N_RX_COALESCE 1<br>
+<br>
+#endif<br>
diff --git a/rtemslwip/zynq_picozed/lwipbspopts.h b/rtemslwip/zynq_picozed/lwipbspopts.h<br>
new file mode 100644<br>
index 0000000..143e302<br>
--- /dev/null<br>
+++ b/rtemslwip/zynq_picozed/lwipbspopts.h<br>
@@ -0,0 +1 @@<br>
+#include <common_lwipopts.h><br>
diff --git a/rtemslwip/zynq_picozed/netstart.c b/rtemslwip/zynq_picozed/netstart.c<br>
new file mode 100644<br>
index 0000000..2f11979<br>
--- /dev/null<br>
+++ b/rtemslwip/zynq_picozed/netstart.c<br>
@@ -0,0 +1,66 @@<br>
+/*<br>
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)<br>
+ * Written by Kinsey Moore <<a href="mailto:kinsey.moore@oarcorp.com" target="_blank">kinsey.moore@oarcorp.com</a>><br>
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions<br>
+ * are met:<br>
+ * 1. Redistributions of source code must retain the above copyright<br>
+ * notice, this list of conditions and the following disclaimer.<br>
+ * 2. Redistributions in binary form must reproduce the above copyright<br>
+ * notice, this list of conditions and the following disclaimer in the<br>
+ * documentation and/or other materials provided with the distribution.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+ * POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+#include <netstart.h><br>
+#include "netif/xadapter.h"<br>
+#include "xparameters.h"<br>
+#include <lwip/tcpip.h><br>
+<br>
+int start_networking(<br>
+ struct netif *net_interface,<br>
+ ip_addr_t *ipaddr,<br>
+ ip_addr_t *netmask,<br>
+ ip_addr_t *gateway,<br>
+ unsigned char *mac_ethernet_address<br>
+)<br>
+{<br>
+ start_networking_shared();<br>
+<br>
+ if ( !xemac_add(<br>
+ net_interface,<br>
+ ipaddr,<br>
+ netmask,<br>
+ gateway,<br>
+ mac_ethernet_address,<br>
+ XPAR_PS7_ETHERNET_0_BASEADDR<br>
+ ) ) {<br>
+ return 1;<br>
+ }<br>
+<br>
+ netif_set_default( net_interface );<br>
+<br>
+ netif_set_up( net_interface );<br>
+<br>
+ sys_thread_new(<br>
+ "xemacif_input_thread",<br>
+ ( void ( * )( void * ) )xemacif_input_thread,<br>
+ net_interface,<br>
+ 1024,<br>
+ DEFAULT_THREAD_PRIO<br>
+ );<br></blockquote><div><br></div><div>No changes currently required here, but fair warning that I have a patch coming soon that will affect the ZynqMP netstart code. I've received confirmation from Xilinx/AMD that the emacps driver was never meant to be SMP-capable (and it really isn't). This thread creation will be locked to core 0 with the IRQ server servicing thread. I'll update this code when I update the ZynqMP code.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+<br>
+ return 0;<br>
+}<br>
diff --git a/rtemslwip/zynq_picozed/xemacps_g.c b/rtemslwip/zynq_picozed/xemacps_g.c<br>
new file mode 100644<br>
index 0000000..596bc49<br>
--- /dev/null<br>
+++ b/rtemslwip/zynq_picozed/xemacps_g.c<br>
@@ -0,0 +1,35 @@<br>
+/*******************************************************************<br>
+*<br>
+* CAUTION: This file is automatically generated by HSI.<br>
+* Version: 2021.2<br>
+* DO NOT EDIT.<br>
+*<br>
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.<br>
+* SPDX-License-Identifier: MIT<br>
+* <br>
+* Description: Driver configuration<br>
+*<br>
+*******************************************************************/<br>
+<br>
+#include "xparameters.h"<br>
+#include "xparameters_ps.h"<br>
+#include "xemacps.h"<br>
+<br>
+/*<br>
+* The configuration table for devices<br>
+*/<br>
+<br></blockquote><div><br></div><div>This should be made more generic and shared among Zynq hardware if possible by adding the other ethernet interface.</div><div> <br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =<br>
+{<br>
+ {<br>
+ XPAR_PS7_ETHERNET_0_DEVICE_ID,<br>
+ XPAR_PS7_ETHERNET_0_BASEADDR,<br>
+ XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT,<br>
+ XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0,<br>
+ XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1,<br>
+ XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0,<br>
+ XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1,<br>
+ XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0,<br>
+ XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1<br>
+ }<br>
+};<br>
diff --git a/rtemslwip/zynq_picozed/xparameters_ps.h b/rtemslwip/zynq_picozed/xparameters_ps.h<br>
new file mode 100644<br>
index 0000000..d88a3fe<br>
--- /dev/null<br>
+++ b/rtemslwip/zynq_picozed/xparameters_ps.h<br>
@@ -0,0 +1,72 @@<br>
+/*<br>
+ * SPDX-License-Identifier: BSD-2-Clause<br>
+ *<br>
+ * Copyright (C) 2024 Bernd Moessner<br>
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions<br>
+ * are met:<br>
+ * 1. Redistributions of source code must retain the above copyright<br>
+ * notice, this list of conditions and the following disclaimer.<br>
+ * 2. Redistributions in binary form must reproduce the above copyright<br>
+ * notice, this list of conditions and the following disclaimer in the<br>
+ * documentation and/or other materials provided with the distribution.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+ * POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+#ifndef _XPARAMETERS_PS_H_<br>
+#define _XPARAMETERS_PS_H_<br>
+<br>
+#ifdef __cplusplus<br>
+extern "C" {<br>
+#endif<br>
+<br>
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U<br>
+#define XPS_SYS_CTRL_BASEADDR 0xF8000000U<br>
+<br>
+#define XPAR_XEMACPS_NUM_INSTANCES 1<br>
+<br>
+#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0<br>
+#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000<br>
+#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF<br>
+#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000<br>
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8<br>
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1<br>
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8<br>
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5<br>
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8<br>
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50<br>
+#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0<br>
+<br>
+#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0<br>
+#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0<br>
+<br>
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID<br>
+#define XPAR_XEMACPS_0_BASEADDR 0xE000B000<br>
+#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF<br>
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000<br>
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8<br>
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1<br>
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8<br>
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5<br>
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8<br>
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50<br>
+#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0<br>
+<br>
+<br>
+#ifdef __cplusplus<br>
+}<br>
+#endif<br>
+<br>
+#endif<br>
diff --git a/rtemslwip/zynq_picozed/xtopology_g.c b/rtemslwip/zynq_picozed/xtopology_g.c<br>
new file mode 100644<br>
index 0000000..bf0ee25<br>
--- /dev/null<br>
+++ b/rtemslwip/zynq_picozed/xtopology_g.c<br>
@@ -0,0 +1,40 @@<br>
+/*<br>
+ * Copyright (C) 2024 Bernd Moessner<br>
+ *<br>
+ * Redistribution and use in source and binary forms, with or without<br>
+ * modification, are permitted provided that the following conditions<br>
+ * are met:<br>
+ * 1. Redistributions of source code must retain the above copyright<br>
+ * notice, this list of conditions and the following disclaimer.<br>
+ * 2. Redistributions in binary form must reproduce the above copyright<br>
+ * notice, this list of conditions and the following disclaimer in the<br>
+ * documentation and/or other materials provided with the distribution.<br>
+ *<br>
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE<br>
+ * POSSIBILITY OF SUCH DAMAGE.<br>
+ */<br>
+<br>
+#include "netif/xtopology.h"<br>
+#include "xparameters.h"<br>
+<br></blockquote><div><br></div><div>This should be made more generic and shared among Zynq hardware if possible by adding the other ethernet interface</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+struct xtopology_t xtopology[] = {<br>
+ {<br>
+ 0xE000B000,<br>
+ xemac_type_emacps,<br>
+ 0x0,<br>
+ 0x0,<br>
+ 0xF8F00100,<br>
+ 0x36,<br>
+ },<br>
+};<br>
+<br>
+int xtopology_n_emacs = 1;<br>
diff --git a/rtemslwip/zynqmp/xil_shims.c b/rtemslwip/zynqmp/xil_shims.c<br>
index 1b1b3cf..1b566b6 100644<br>
--- a/rtemslwip/zynqmp/xil_shims.c<br>
+++ b/rtemslwip/zynqmp/xil_shims.c<br>
@@ -57,51 +57,6 @@ void Xil_SetTlbAttributes( UINTPTR Addr, u64 attrib )<br>
}<br>
}<br>
<br>
-#include "FreeRTOS.h"<br>
-<br>
-/*<br>
- * XInterruptHandler function pointer signature just happens to exactly match<br>
- * rtems_interrupt_handler<br>
- */<br>
-BaseType_t xPortInstallInterruptHandler(<br>
- uint8_t ucInterruptID,<br>
- XInterruptHandler pxHandler,<br>
- void *pvCallBackRef<br>
-)<br>
-{<br>
- char name[10];<br>
-<br>
- /* Is this running in the context of any interrupt server tasks? */<br>
- _Thread_Get_name( _Thread_Get_executing(), name, sizeof( name ) );<br>
- if (strcmp(name, "IRQS") == 0) {<br>
- /* Can't run this from within an IRQ Server thread context */<br>
- return RTEMS_ILLEGAL_ON_SELF;<br>
- }<br>
-<br>
- rtems_status_code sc = rtems_interrupt_server_handler_install(<br>
- RTEMS_INTERRUPT_SERVER_DEFAULT,<br>
- ucInterruptID,<br>
- "CGEM Handler",<br>
- RTEMS_INTERRUPT_UNIQUE,<br>
- pxHandler,<br>
- pvCallBackRef<br>
- );<br>
-<br>
- return sc;<br>
-}<br>
-<br>
-/* Enable the interrupt */<br>
-void XScuGic_EnableIntr ( u32 DistBaseAddress, u32 Int_Id )<br>
-{<br>
- rtems_interrupt_vector_enable( Int_Id );<br>
-}<br>
-<br>
-/* Disable the interrupt */<br>
-void XScuGic_DisableIntr ( u32 DistBaseAddress, u32 Int_Id )<br>
-{<br>
- rtems_interrupt_vector_disable( Int_Id );<br>
-}<br>
-<br>
/*<br>
* The Xilinx code was written such that it assumed there was no invalidate-only<br>
* functionality on A53 cores. This function must flush and invalidate because<br>
-- <br>
2.34.1<br>
<br>
_______________________________________________<br>
devel mailing list<br>
<a href="mailto:devel@rtems.org" target="_blank">devel@rtems.org</a><br>
<a href="http://lists.rtems.org/mailman/listinfo/devel" rel="noreferrer" target="_blank">http://lists.rtems.org/mailman/listinfo/devel</a><br>
</blockquote></div></div>