<meta http-equiv="Content-Type" content="text/html; charset=utf-8"><div dir="ltr"><div>This adds warnings for arm_interrupt_enable_interrupts and arm_interrupt_restore_interrupts. I suspect a missing header. They also generate a link error on the a53_lp64_qemu bsp. I also dislike the while(true), but I don't think we officially have anything against it and there are existing examples in the codebase.<br></div><div><br></div><div>Kinsey<br></div><div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Apr 16, 2024 at 3:24 AM Sebastian Huber <<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">In addtion to 1023, the GICC_IAR register may return 1022 as a special value.<br>
Simply check for a valid interrupt vector for the dispatching.<br>
<br>
Check the GICC_IAR again after the dispatch to quickly process a next interrupt<br>
without having to go through the interrupt prologue and epiloge.<br>
---<br>
bsps/shared/dev/irq/arm-gicv3.c | 16 +++++++++++-----<br>
1 file changed, 11 insertions(+), 5 deletions(-)<br>
<br>
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c<br>
index 88ac3c8293..dcfada6cd0 100644<br>
--- a/bsps/shared/dev/irq/arm-gicv3.c<br>
+++ b/bsps/shared/dev/irq/arm-gicv3.c<br>
@@ -42,12 +42,18 @@<br>
<br>
void bsp_interrupt_dispatch(void)<br>
{<br>
- uint32_t icciar = READ_SR(ICC_IAR1);<br>
- rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);<br>
- rtems_vector_number spurious = 1023;<br>
+ while (true) {<br>
+ uint32_t icciar = READ_SR(ICC_IAR1);<br>
+ rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);<br>
+ uint32_t status;<br>
<br>
- if (vector != spurious) {<br>
- arm_interrupt_handler_dispatch(vector);<br>
+ if (!bsp_interrupt_is_valid_vector(vector)) {<br>
+ break;<br>
+ }<br>
+<br>
+ status = arm_interrupt_enable_interrupts();<br>
+ bsp_interrupt_handler_dispatch_unchecked(vector);<br>
+ arm_interrupt_restore_interrupts(status);<br>
<br>
WRITE_SR(ICC_EOIR1, icciar);<br>
}<br>
-- <br>
2.35.3<br>
<br>
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</blockquote></div></div>