MC68331 GPT header file
mcollins at hawkeye.sps.mot.com
mcollins at hawkeye.sps.mot.com
Fri Mar 23 00:35:04 UTC 2001
Appended is a header file for the MC68331 general purpose timer. It
closely follows the conventions used in other m68k header files used
by the efi332 BSP.
------------------------------------------------------------------------------
/*
* MC68331 General Purpose Timer definitions
*
* Notes:
*
* 1. Register and bit addresses are dependent upon register sizes;
* 16-bit registers documented as two concatenated 8-bit registers
* (i.e., GPT PDDR/PDR) are defined as separate 8-bit registers.
*
* 2. Register names are concatenation of gpt_<name>, where <name> is
* register name as documented in MC68331 User's Manual.
*
* 3. Test registers are not defined within this file.
*
* 4. This file follows the conventions used within "sim.h".
*/
/*
* These macros make this file usable from assembly.
*/
#ifdef ASM
#define SIM_VOLATILE_USHORT_POINTER
#define SIM_VOLATILE_UCHAR_POINTER
#else
#define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const)
#define SIM_VOLATILE_UCHAR_POINTER (volatile unsigned char * const)
#endif
/*
* GPT_CRB (GPT Control Register Block) base address of the GPT
* control registers
*
* Note: Not certain that SIM_MM will always be known when this file is
* processed. If not, it may be necessary to hard-code GPT_CRB.
*/
#if SIM_MM == 0
#define GPT_CRB 0x7ff900
#else
#undef SIM_MM
#define GPT_MM 1
#define GPT_CRB 0xfff900
#endif
/*
* end not included in ram_init.h
*/
/*
* Configuration Register (MCR)
*/
#define GPT_MCR SIM_VOLATILE_USHORT_POINTER (0x00 + GPT_CRB)
#define GPT_STOP (1 << 15)
#define GPT_FRZ1 (1 << 14)
#define GPT_FRZ0 (1 << 13)
#define GPT_STOPP (1 << 12)
#define GPT_INCP (1 << 11)
#define GPT_SUPV (1 << 7)
#define GPT_IARB3 (1 << 3)
#define GPT_IARB2 (1 << 2)
#define GPT_IARB1 (1 << 1)
#define GPT_IARB0 (1 << 0)
/*
* Interrupt Configuration Register (ICR)
*/
#define GPT_ICR SIM_VOLATILE_USHORT_POINTER (0x04 + GPT_CRB)
/*
* GPT Interrupt vectors are the sum of IVBA (ICR[7:4]) and vector
* values shown below. The first definition is for the Adjust Channel.
*/
#define GPT_AC_VECTOR (1 << 0)
#define GPT_IC1_VECTOR (1 << 1)
#define GPT_IC2_VECTOR (1 << 2)
#define GPT_IC3_VECTOR (1 << 3)
#define GPT_OC1_VECTOR (1 << 4)
#define GPT_OC2_VECTOR (1 << 5)
#define GPT_OC3_VECTOR (1 << 6)
#define GPT_OC4_VECTOR (1 << 7)
#define GPT_IC4OC5_VECTOR (1 << 8)
#define GPT_TOF_VECTOR (1 << 9)
#define GPT_PAOVF_VECTOR (1 << 10)
#define GPT_PAIF_VECTOR (1 << 11)
/*
* Parallel Data Direction Register (PDDR)
*/
#define GPT_PDDR SIM_VOLATILE_UCHAR_POINTER (0x06 + GPT_CRB)
#define GPT_DDRI4O5 (1 << 7)
#define GPT_DDRO4 (1 << 6)
#define GPT_DD5O3 (1 << 5)
#define GPT_DDRO2 (1 << 4)
#define GPT_DDRO1 (1 << 3)
#define GPT_DDRI3 (1 << 2)
#define GPT_DDRI2 (1 << 1)
#define GPT_DDRI1 (1 << 0)
/*
* Parallel Data Register (PDR)
*/
#define GPT_PDR SIM_VOLATILE_UCHAR_POINTER (0x07 + GPT_CRB)
#define GPT_IC4OC5 (1 << 7)
#define GPT_OC4 (1 << 6)
#define GPT_OC3 (1 << 5)
#define GPT_OC2 (1 << 4)
#define GPT_OC1 (1 << 3)
#define GPT_IC3 (1 << 2)
#define GPT_IC2 (1 << 1)
#define GPT_IC1 (1 << 0)
/*
* OC1 Action Mask Register (OC1M)
*/
#define GPT_OC1M SIM_VOLATILE_UCHAR_POINTER (0x08 + GPT_CRB)
#define GPT_OC1M7 (1 << 7)
#define GPT_OC1M6 (1 << 6)
#define GPT_OC1M5 (1 << 5)
#define GPT_OC1M4 (1 << 4)
#define GPT_OC1M3 (1 << 3)
/*
* OC1 Action Data Register (OC1D)
*/
#define GPT_OC1D SIM_VOLATILE_UCHAR_POINTER (0x09 + GPT_CRB)
#define GPT_OC1D7 (1 << 7)
#define GPT_OC1D6 (1 << 6)
#define GPT_OC1D5 (1 << 5)
#define GPT_OC1D4 (1 << 4)
#define GPT_OC1D3 (1 << 3)
/*
* Counter Register (TCNT)
*/
#define GPT_TCNT SIM_VOLATILE_USHORT_POINTER (0x0a + GPT_CRB)
/*
* Pulse Accumulator Control Register (PACTL)
*/
#define GPT_PACTL SIM_VOLATILE_UCHAR_POINTER (0x0c + GPT_CRB)
#define GPT_PAIS (1 << 7)
#define GPT_PAEN (1 << 6)
#define GPT_PAMOD (1 << 5)
#define GPT_PEDGE (1 << 4)
#define GPT_PCLKS (1 << 3)
#define GPT_I4O5 (1 << 2)
#define GPT_PACLK1 (1 << 1)
#define GPT_PACLK0 (1 << 0)
/*
* Pulse Accumulator Counter Register (PACNT)
*/
#define GPT_PACNT SIM_VOLATILE_UCHAR_POINTER (0x0d + GPT_CRB)
#define GPT_PACNT7 (1 << 7)
#define GPT_PACNT6 (1 << 6)
#define GPT_PACNT5 (1 << 5)
#define GPT_PACNT4 (1 << 4)
#define GPT_PACNT3 (1 << 3)
#define GPT_PACNT2 (1 << 2)
#define GPT_PACNT1 (1 << 1)
#define GPT_PACNT0 (1 << 0)
/*
* Input Capture Register 1 (TIC1)
*/
#define GPT_TIC1 SIM_VOLATILE_USHORT_POINTER (0x0e + GPT_CRB)
/*
* Input Capture Register 2 (TIC2)
*/
#define GPT_TIC2 SIM_VOLATILE_USHORT_POINTER (0x10 + GPT_CRB)
/*
* Input Capture Register 3 (TIC3)
*/
#define GPT_TIC3 SIM_VOLATILE_USHORT_POINTER (0x12 + GPT_CRB)
/*
* Output Compare Register 1 (TOC1)
*/
#define GPT_TOC1 SIM_VOLATILE_USHORT_POINTER (0x14 + GPT_CRB)
/*
* Output Compare Register 2 (TOC2)
*/
#define GPT_TOC2 SIM_VOLATILE_USHORT_POINTER (0x16 + GPT_CRB)
/*
* Output Compare Register 3 (TOC3)
*/
#define GPT_TOC3 SIM_VOLATILE_USHORT_POINTER (0x18 + GPT_CRB)
/*
* Output Compare Register 4 (TOC4)
*/
#define GPT_TOC4 SIM_VOLATILE_USHORT_POINTER (0x1a + GPT_CRB)
/*
* Input Capture 4/Ouput Compare 5 Register (TI4O5)
*/
#define GPT_TI4O5 SIM_VOLATILE_USHORT_POINTER (0x1c + GPT_CRB)
/*
* Control Register 1 (TCTL1)
*/
#define GPT_TCTL1 SIM_VOLATILE_UCHAR_POINTER (0x1e + GPT_CRB)
#define GPT_OM5 (1 << 7)
#define GPT_OL5 (1 << 6)
#define GPT_OM4 (1 << 5)
#define GPT_OL4 (1 << 4)
#define GPT_OM3 (1 << 3)
#define GPT_OL3 (1 << 2)
#define GPT_OM2 (1 << 1)
#define GPT_OL2 (1 << 0)
/*
* Control Register 2 (TCTL2)
*/
#define GPT_TCTL2 SIM_VOLATILE_UCHAR_POINTER (0x1f + GPT_CRB)
#define GPT_EDGE4B (1 << 7)
#define GPT_EDGE4A (1 << 6)
#define GPT_EDGE3B (1 << 5)
#define GPT_EDGE3A (1 << 4)
#define GPT_EDGE2B (1 << 3)
#define GPT_EDGE2A (1 << 2)
#define GPT_EDGE1B (1 << 1)
#define GPT_EDGE1A (1 << 0)
/*
* Interrupt Mask Register 1 (TMSK1)
*/
#define GPT_TMSK1 SIM_VOLATILE_UCHAR_POINTER (0x20 + GPT_CRB)
#define GPT_I4O5I (1 << 7)
#define GPT_OC4I (1 << 6)
#define GPT_OC3I (1 << 5)
#define GPT_OC2I (1 << 4)
#define GPT_OC1I (1 << 3)
#define GPT_IC3I (1 << 2)
#define GPT_IC2I (1 << 1)
#define GPT_IC1I (1 << 0)
/*
* Interrupt Mask Register 2 (TMSK2)
*/
#define GPT_TMSK2 SIM_VOLATILE_UCHAR_POINTER (0x21 + GPT_CRB)
#define GPT_TOI (1 << 7)
#define GPT_PAOVI (1 << 5)
#define GPT_PAII (1 << 4)
#define GPT_CPROUT (1 << 3)
#define GPT_CPR2 (1 << 2)
#define GPT_CPR1 (1 << 1)
#define GPT_CPR0 (1 << 0)
/*
* Interrupt Flag Register 1 (TFLG1)
*/
#define GPT_TFLG1 SIM_VOLATILE_UCHAR_POINTER (0x22 + GPT_CRB)
#define GPT_I4O5F (1 << 7)
#define GPT_OC4F (1 << 6)
#define GPT_OC3F (1 << 5)
#define GPT_OC2F (1 << 4)
#define GPT_OC1F (1 << 3)
#define GPT_IC3F (1 << 2)
#define GPT_IC2F (1 << 1)
#define GPT_IC1F (1 << 0)
/*
* Interrupt Flag Register 2 (TFLG2)
*
* TOF bit defined above.
*/
#define GPT_TFLG2 SIM_VOLATILE_UCHAR_POINTER (0x22 + GPT_CRB)
#define GPT_PAOVF (1 << 5)
#define GPT_PAIF (1 << 4)
/*
* Compare Force Register (CFORC)
*/
#define GPT_CFORC SIM_VOLATILE_UCHAR_POINTER (0x24 + GPT_CRB)
#define GPT_FOC5 (1 << 7)
#define GPT_FOC4 (1 << 6)
#define GPT_FOC3 (1 << 5)
#define GPT_FOC2 (1 << 4)
#define GPT_FOC1 (1 << 3)
#define GPT_FPWMA (1 << 1)
#define GPT_FPWMB (1 << 0)
/*
* PWM Control Register (PWMC)
*/
#define GPT_PWMC SIM_VOLATILE_UCHAR_POINTER (0x25 + GPT_CRB)
#define GPT_PPROUT (1 << 7)
#define GPT_PPR2 (1 << 6)
#define GPT_PPR1 (1 << 5)
#define GPT_PPR0 (1 << 4)
#define GPT_SFA (1 << 3)
#define GPT_SFB (1 << 2)
#define GPT_F1A (1 << 1)
#define GPT_F1B (1 << 0)
/*
* PWM Register A (PWMA)
*/
#define GPT_PWMA SIM_VOLATILE_UCHAR_POINTER (0x26 + GPT_CRB)
/*
* PWM Register B (PWMB)
*/
#define GPT_PWMB SIM_VOLATILE_UCHAR_POINTER (0x27 + GPT_CRB)
/*
* PWM Count Register (PWMCNT)
*/
#define GPT_PWMCNT SIM_VOLATILE_USHORT_POINTER (0x28 + GPT_CRB)
/*
* PWM Buffer Register A (PWMABUF)
*/
#define GPT_PWMABUF SIM_VOLATILE_UCHAR_POINTER (0x2a + GPT_CRB)
/*
* PWM Buffer Register B (PWMBBUF)
*/
#define GPT_PWMBBUF SIM_VOLATILE_UCHAR_POINTER (0x2b + GPT_CRB)
/*
* GPT Prescaler (PRESCL)
*/
#define GPT_PRESCL SIM_VOLATILE_USHORT_POINTER (0x2c + GPT_CRB)
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