Eric Valette wrote:
  >Chris Caudle wrote:
  >> If using a typical personal computer style X86, I think that the
  >> machine BIOS should make sure that all of PCI memory space is
  >> non-cacheable for you.

> Not at all : How could the BIOS modyfy the way the CPU 
> access PCI address space?

The BIOS sets up the memory controller.
My experience is with Compaq/HP Proliant servers, where I used RTEMS for testing new ASICS.  The Proliant BIOS is pretty standard X86, nothing really unusual, so I would expect that all Intel processor PC style systems would behave the same way.
When the machine boots, the BIOS finds how much physical memory is installed, and configures the memory controller so that physical memory addresses are marked as cacheable, all other address ranges are not cacheable.
On such a system, you just access memory mapped PCI devices without worrying about cache issues.  It just works.  Cache configuration should be handled by the BSP, and in the case of pc386 that configuration is effectively handled by the bootloader, so there is nothing for the BSP to do.

-- Chris Caudle

