Eric Valette wrote:
> I would like to add to this that for IX86, as registers access 
> region must be mapped non cacheable and the processor 
> does not support cache manipulation without the mmu, you 
> also need to remap the memory address range non cacheable
> via mmu. 

If using a typical personal computer style X86, I think that the machine BIOS should make sure that all of PCI memory space is non-cacheable for you.
Of course, if you are writing for a deeply embedded system where the BSP has to handle all of the MMU setup you need to take this into account, but I don't think the application will have to worry about that detail when running on the pc386 BSP.

-- Chris Caudle



