# # alteraSysConfigMap.txt # # A simple text data file mapping between Altera system.h macro names # and RTEMS alteraSysConfig BSP macro names. This translation is performed # so that we can avoid colisions between the source files in the Altera HAL # and RTEMS source files. # # # # # field 0 (first field - starting on left hand side) # DEFINE - Define the RTEMS bsp macro name from field 1 providing the # value of the Altera system.h macro specified in field 2 for # its value. # IFDEF - If the Altera system.h macro specified in field 2 exists # then define the RTEMS bsp macro name specified in field 1. # # field 1 # RTEMS Nios2 sys configure BSP macro name # # field 2 (last field) # Altera system.h macro name # # # # # RTEMS MACRO NAME Altera SOPC/QSYS/nios2-bsp Macro NAME # DEFINE CPU_ARCHITECTURE ALT_CPU_ARCHITECTURE IFDEF NIOS2_INITDA_SUPPORTED ALT_CPU_INITDA_SUPPORTED IFDEF NIOS2_FLUSHDA_SUPPORTED ALT_CPU_FLUSHDA_SUPPORTED DEFINE NIOS2_ICACHE_LINE_SIZE ALT_CPU_ICACHE_LINE_SIZE DEFINE NIOS2_ICACHE_SIZE ALT_CPU_ICACHE_SIZE DEFINE NIOS2_DCACHE_LINE_SIZE ALT_CPU_DCACHE_LINE_SIZE DEFINE NIOS2_DCACHE_SIZE ALT_CPU_DCACHE_SIZE DEFINE NIOS2_EXCEPTION_ADDR ALT_CPU_EXCEPTION_ADDR DEFINE NIOS2_RESET_ADDR ALT_CPU_RESET_ADDR DEFINE NIOS2_BIG_ENDIAN ALT_CPU_BIG_ENDIAN DEFINE SDRAM_BASE DDR_SDRAM_REGION_BASE DEFINE SDRAM_SPAN DDR_SDRAM_REGION_SPAN DEFINE SSRAM_BASE TSC_SSRAM_REGION_BASE DEFINE SSRAM_SPAN TSC_SSRAM_REGION_SPAN DEFINE RESET_BASE RESET_REGION_BASE DEFINE RESET_SPAN RESET_REGION_SPAN DEFINE FLASH_BASE TSC_FLASH_REGION_BASE DEFINE FLASH_SPAN TSC_FLASH_REGION_SPAN DEFINE TIGHT_COUPLED_CODE_RAM_BASE TIGHT_COUPLED_CODE_RAM_REGION_BASE DEFINE TIGHT_COUPLED_CODE_RAM_SPAN TIGHT_COUPLED_CODE_RAM_REGION_SPAN DEFINE SYS_CONSOLE_JTAG_UART_BASE JTAGUARTS_JTAG_UART_CONSOLE_BASE DEFINE SYS_CONSOLE_JTAG_UART_IRQ JTAGUARTS_JTAG_UART_CONSOLE_IRQ DEFINE SYS_CONSOLE_JTAG_UART_READ_DEPTH JTAGUARTS_JTAG_UART_CONSOLE_READ_DEPTH DEFINE SYS_CONSOLE_JTAG_UART_WRITE_DEPTH JTAGUARTS_JTAG_UART_CONSOLE_WRITE_DEPTH DEFINE SYS_GDB_JTAG_UART_BASE JTAGUARTS_JTAG_UART_GDB_BASE DEFINE SYS_GDB_JTAG_UART_IRQ JTAGUARTS_JTAG_UART_GDB_IRQ DEFINE SYS_GDB_JTAG_UART_READ_DEPTH JTAGUARTS_JTAG_UART_GDB_READ_DEPTH DEFINE SYS_GDB_JTAG_UART_WRITE_DEPTH JTAGUARTS_JTAG_UART_GDB_WRITE_DEPTH DEFINE SYS_BENCHMARK_TIMER_BASE PERIPH_PERFORMANCE_TIMER_BASE DEFINE SYS_BENCHMARK_TIMER_IRQ PERIPH_PERFORMANCE_TIMER_IRQ DEFINE SYS_BENCHMARK_TIMER_FREQ PERIPH_PERFORMANCE_TIMER_FREQ DEFINE SYS_CLK_TIMER_BASE PERIPH_SYS_CLK_TIMER_BASE DEFINE SYS_CLK_TIMER_IRQ PERIPH_SYS_CLK_TIMER_IRQ DEFINE SYS_CLK_TIMER_FREQ PERIPH_SYS_CLK_TIMER_FREQ DEFINE TSE0_MAC_BASE NIF_TSE_MAC_BASE DEFINE TSE0_RX_FIFO_DEPTH NIF_TSE_MAC_RECEIVE_FIFO_DEPTH DEFINE TSE0_TX_FIFO_DEPTH NIF_TSE_MAC_TRANSMIT_FIFO_DEPTH DEFINE TSE0_FIFO_WIDTH NIF_TSE_MAC_FIFO_WIDTH DEFINE TSE0_DESCRIPTOR_MEMORY_BASE NIF_DESCR_RAM_REGION_BASE DEFINE TSE0_DESCRIPTOR_MEMORY_SPAN NIF_DESCR_RAM_REGION_SPAN DEFINE TSE0_RX_SGDMA_BASE NIF_SGDMA_RX_BASE DEFINE TSE0_RX_SGDMA_IRQ NIF_SGDMA_RX_IRQ DEFINE TSE0_RX_SGDMA_UNALIGNED_TRANSFER NIF_SGDMA_RX_UNALIGNED_TRANSFER DEFINE TSE0_TX_SGDMA_BASE NIF_SGDMA_TX_BASE DEFINE TSE0_TX_SGDMA_IRQ NIF_SGDMA_TX_IRQ DEFINE TSE0_TX_SGDMA_UNALIGNED_TRANSFER NIF_SGDMA_TX_UNALIGNED_TRANSFER