<html>
<head>
<meta content="text/html; charset=ISO-8859-1"
http-equiv="Content-Type">
</head>
<body bgcolor="#FFFFFF" text="#000000">
<div class="moz-cite-prefix">Looking at the code suggested that the
FPU is disabled during execution<br>
of exception handlers and interrupts. Because this is quite
complex I also<br>
ran a simple test (rtems 4.9.4) which confirms this: you
definitely run<br>
into an exception if you try to use the FPU from an exception
handler or<br>
ISR.<br>
<br>
For the same reasons we have made all threads implicitly FP
threads<br>
I believe that it would be a good idea to also save (volatile) FP
context<br>
across exceptions. The code would not be very complex and it could<br>
be added in proximity to where altivec context is saved/restored.<br>
<br>
- Till<br>
<br>
BTW: AFAIK the current code saves/restores all FP registers when
performing<br>
a task context switch - wouldn't it be enough to just save/restore
non-volatile<br>
registers?<br>
<br>
<br>
On 12/12/2013 10:06 AM, Joel Sherrill wrote:<br>
</div>
<blockquote
cite="mid:84DFB03DEB1A9C49AC40B1F3F18E72B104B5AD2688E8@OARmail.OARCORP.com"
type="cite">
<meta http-equiv="Content-Type" content="text/html;
charset=ISO-8859-1">
<meta name="Generator" content="Microsoft Exchange Server">
<!-- converted from text -->
<style><!-- .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left: #800000 2px solid; } --></style>
<p dir="ltr">Then the bsp should user the correct cpu cflags and
the isr vectoring code should disable the fpu if possible.</p>
<div class="quote">On Dec 12, 2013 8:45 AM, Sebastian Huber
<a class="moz-txt-link-rfc2396E" href="mailto:sebastian.huber@embedded-brains.de"><sebastian.huber@embedded-brains.de></a> wrote:<br
type="attribution">
</div>
<font size="2">
<div class="PlainText">On 2013-12-12 15:26, Matt Wette wrote:<br>
> But if you don't use FP in ISR you still need to compile
the ISR with<br>
> -fsoft-float because the compiler may dirty the FP
registers otherwise.<br>
> For example: a = b; where a, b are struct timespec may be
implemented in FP<br>
> registers.<br>
<br>
In case the ISR uses operating system services, then this is
highly dangerous <br>
since operating system functions are not compiled with
-msoft-float in this <br>
case. Also on PowerPC the hard-float and soft-float ABIs are
incompatible.<br>
<br>
The distinction between floating-point and non-floating-point
tasks is <br>
questionable with modern compilers.<br>
<br>
-- <br>
Sebastian Huber, embedded brains GmbH<br>
<br>
Address : Dornierstr. 4, D-82178 Puchheim, Germany<br>
Phone : +49 89 189 47 41-16<br>
Fax : +49 89 189 47 41-09<br>
E-Mail : <a class="moz-txt-link-abbreviated" href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a><br>
PGP : Public key available on request.<br>
<br>
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne
des EHUG.<br>
_______________________________________________<br>
rtems-users mailing list<br>
<a class="moz-txt-link-abbreviated" href="mailto:rtems-users@rtems.org">rtems-users@rtems.org</a><br>
<a moz-do-not-send="true"
href="http://www.rtems.org/mailman/listinfo/rtems-users">http://www.rtems.org/mailman/listinfo/rtems-users</a><br>
</div>
</font>
</blockquote>
<br>
</body>
</html>