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<div class="moz-cite-prefix">On 05/02/2017 07:17 PM, Joel Sherrill
wrote:<br>
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cite="mid:CAF9ehCWJ=JedHgML=j4TmBukPXNjvSwjrtqDnz8KiQCbZR9i_g@mail.gmail.com"
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<div class="gmail_quote">On Tue, May 2, 2017 at 12:11 PM,
Molock, Dwaine S. (GSFC-5820) <span dir="ltr"><<a
moz-do-not-send="true"
href="mailto:dwaine.s.molock@nasa.gov" target="_blank">dwaine.s.molock@nasa.gov</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">Hello,<br>
<br>
Is there a RTEMS port available for the RISC-V processor?<br>
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<div>No but it would be something we would be very happy to
see happen. It</div>
<div>looks like an architecture with a great future.</div>
<div><br>
</div>
<div>How it gets done is always the question. It could be
done as a user </div>
<div>submitted port or via sponsorship of core developers
implementing</div>
<div>it. If sponsoring the port is an option, we can follow
up offline.</div>
<div><br>
</div>
<div>--joel<br>
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There is a port at GitHub, see:<br>
<br>
<a class="moz-txt-link-freetext" href="https://github.com/heshamelmatary/rtems-riscv">https://github.com/heshamelmatary/rtems-riscv</a><br>
<br>
Seems fairly complete, so it might be used as a starting point...<br>
<br>
Jiri.<br>
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<br>
Thanks,<br>
Dwaine<br>
<br>
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