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Hi Sebastian,
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<div class="">Will these ports work on the RISC-V designs from SiFive (<a href="https://www.sifive.com" class="">https://www.sifive.com</a>)?</div>
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<div class="">Thanks,</div>
<div class="">Dwaine</div>
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<div class="">On Jun 12, 2018, at 9:25 AM, Sebastian Huber <<a href="mailto:sebastian.huber@embedded-brains.de" class="">sebastian.huber@embedded-brains.de</a>> wrote:</div>
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<div class="">Hello Molock,<br class="">
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we work currently on the SMP support for RISC-V (32-bit and 64-bit). The aim is to run the tests on Qemu and a FPGA Board with two BOOMv2 processors.<br class="">
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<a href="https://devel.rtems.org/ticket/3433" class="">https://devel.rtems.org/ticket/3433</a><br class="">
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My current task is a tool chain update to include a bug fix for:<br class="">
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https://sourceware.org/bugzilla/show_bug.cgi?id=23244<br class="">
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This fix is necessary to run 64-bit applications in an address rage above 0x80000000 (SDRAM address in some standard chips). We need also specialized GCC multilibs for this.<br class="">
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I would like to merge the riscv32 and riscv64 tool chain into one riscv tool chain. There was some discussion necessary with the RISC-V maintainers to achieve this.<br class="">
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The overall work should be finished in two to three months.<br class="">
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-- <br class="">
Sebastian Huber, embedded brains GmbH<br class="">
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Address : Dornierstr. 4, D-82178 Puchheim, Germany<br class="">
Phone : +49 89 189 47 41-16<br class="">
Fax : +49 89 189 47 41-09<br class="">
E-Mail : sebastian.huber@embedded-brains.de<br class="">
PGP : Public key available on request.<br class="">
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Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.<br class="">
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