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<p class="MsoNormal" style="margin-left:.5in"><b><span style="font-size:12.0pt;color:black">From:
</span></b><span style="font-size:12.0pt;color:black">Joel Sherrill <joel@rtems.org><br>
<b>Reply-To: </b>"joel@rtems.org" <joel@rtems.org><br>
<b>Date: </b>Tuesday, November 26, 2019 at 4:37 PM<br>
<b>To: </b>Sebastian Huber <sebastian.huber@embedded-brains.de><br>
<b>Cc: </b>"Molock, Dwaine S. (GSFC-5820)" <dwaine.s.molock@nasa.gov>, "users@rtems.org" <users@rtems.org><br>
<b>Subject: </b>[EXTERNAL] Re: Arm Cortex-R5 RTEMS Port/BSP?<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-left:.5in">On Mon, Nov 25, 2019 at 12:42 AM Sebastian Huber <<a href="mailto:sebastian.huber@embedded-brains.de">sebastian.huber@embedded-brains.de</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal" style="margin-left:.5in">Hello,<br>
<br>
On 22/11/2019 21:57, Molock, Dwaine S. (GSFC-5820) wrote:<br>
> Hello,<br>
> <br>
> Is there an Arm Cortex-R5 RTEMS support and/or Port/BSP available?<br>
<br>
we don't have a port, but may work with a Cortex-R52 in Q1 or Q2 next year.<o:p></o:p></p>
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<p class="MsoNormal" style="margin-left:.5in"><o:p> </o:p></p>
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<p class="MsoNormal" style="margin-left:.5in">There is an R52 in the HPSC and a BSP should be submitted for that in the not so <o:p></o:p></p>
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<p class="MsoNormal" style="margin-left:.5in">distant future to <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__rtems.org&d=DwMFaQ&c=ApwzowJNAKKw3xye91w7BE1XMRKi2LN9kiMk5Csz9Zk&r=QjCnq0zmbpTnLxZlwSp_iFPlpOQ5MQgRjJAOE3tyRuI&m=57xON2vr6nu4RpumebsWl5QM9rFpQT1Lu_q01DdBKhc&s=v6W7yOP4DPuLtRB8EXKz4L3kZaN3ab2dyFq4YnDUQvM&e=">
rtems.org</a>. There is still some work to be done. What has been delivered<o:p></o:p></p>
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<p class="MsoNormal" style="margin-left:.5in">is available at <a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_ISI-2Dapex_rtems&d=DwMFaQ&c=ApwzowJNAKKw3xye91w7BE1XMRKi2LN9kiMk5Csz9Zk&r=QjCnq0zmbpTnLxZlwSp_iFPlpOQ5MQgRjJAOE3tyRuI&m=57xON2vr6nu4RpumebsWl5QM9rFpQT1Lu_q01DdBKhc&s=ToVsK9gAmaCik1EoiDZylI5LspuY2FQN3POQYcvhX9E&e=">https://github.com/ISI-apex/rtems</a><o:p></o:p></p>
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<p class="MsoNormal" style="margin-left:.5in">Do you have a specific target board or SoC in mind?<o:p></o:p></p>
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<p class="MsoNormal" style="margin-left:.5in"><o:p> </o:p></p>
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<p class="MsoNormal" style="margin-left:.5in">--joel<o:p></o:p></p>
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<p class="MsoNormal" style="margin-left:.5in"> <o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I’m using the Xilinx Zynq UltraScale+ MPSoC ZCU104 development board but I do have access to a ZCU102 board.<o:p></o:p></p>
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> <br>
> I see that there are BSP’s for the Arm Cortex-R4. The R5 is a superset <br>
> of the R4 with enhanced error management and extended functional safety <br>
> features.<br>
<br>
One of the main features this that is supports an EL2 which makes it a <br>
better target for hypervisors.<br>
<br>
> <br>
> Can a R4 BSP be executed on a R5 and/or used as the starting point for <br>
> creating a R5 Port and BSP?<br>
<br>
Yes.<br>
<br>
-- <br>
Sebastian Huber, embedded brains GmbH<br>
<br>
Address : Dornierstr. 4, D-82178 Puchheim, Germany<br>
Phone : +49 89 189 47 41-16<br>
Fax : +49 89 189 47 41-09<br>
E-Mail : <a href="mailto:sebastian.huber@embedded-brains.de" target="_blank">sebastian.huber@embedded-brains.de</a><br>
PGP : Public key available on request.<br>
<br>
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.<br>
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